1 /* 2 * ARC Cache Management 3 * 4 * Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com) 5 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com) 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11 12 #include <linux/module.h> 13 #include <linux/mm.h> 14 #include <linux/sched.h> 15 #include <linux/cache.h> 16 #include <linux/mmu_context.h> 17 #include <linux/syscalls.h> 18 #include <linux/uaccess.h> 19 #include <linux/pagemap.h> 20 #include <asm/cacheflush.h> 21 #include <asm/cachectl.h> 22 #include <asm/setup.h> 23 24 static int l2_line_sz; 25 int ioc_exists; 26 volatile int slc_enable = 1, ioc_enable = 1; 27 28 void (*_cache_line_loop_ic_fn)(unsigned long paddr, unsigned long vaddr, 29 unsigned long sz, const int cacheop); 30 31 void (*__dma_cache_wback_inv)(unsigned long start, unsigned long sz); 32 void (*__dma_cache_inv)(unsigned long start, unsigned long sz); 33 void (*__dma_cache_wback)(unsigned long start, unsigned long sz); 34 35 char *arc_cache_mumbojumbo(int c, char *buf, int len) 36 { 37 int n = 0; 38 struct cpuinfo_arc_cache *p; 39 40 #define IS_USED_RUN(v) ((v) ? "" : "(disabled) ") 41 #define PR_CACHE(p, cfg, str) \ 42 if (!(p)->ver) \ 43 n += scnprintf(buf + n, len - n, str"\t\t: N/A\n"); \ 44 else \ 45 n += scnprintf(buf + n, len - n, \ 46 str"\t\t: %uK, %dway/set, %uB Line, %s%s%s\n", \ 47 (p)->sz_k, (p)->assoc, (p)->line_len, \ 48 (p)->vipt ? "VIPT" : "PIPT", \ 49 (p)->alias ? " aliasing" : "", \ 50 IS_ENABLED(cfg) ? "" : " (not used)"); 51 52 PR_CACHE(&cpuinfo_arc700[c].icache, CONFIG_ARC_HAS_ICACHE, "I-Cache"); 53 PR_CACHE(&cpuinfo_arc700[c].dcache, CONFIG_ARC_HAS_DCACHE, "D-Cache"); 54 55 if (!is_isa_arcv2()) 56 return buf; 57 58 p = &cpuinfo_arc700[c].slc; 59 if (p->ver) 60 n += scnprintf(buf + n, len - n, 61 "SLC\t\t: %uK, %uB Line%s\n", 62 p->sz_k, p->line_len, IS_USED_RUN(slc_enable)); 63 64 if (ioc_exists) 65 n += scnprintf(buf + n, len - n, "IOC\t\t:%s\n", 66 IS_USED_RUN(ioc_enable)); 67 68 return buf; 69 } 70 71 /* 72 * Read the Cache Build Confuration Registers, Decode them and save into 73 * the cpuinfo structure for later use. 74 * No Validation done here, simply read/convert the BCRs 75 */ 76 static void read_decode_cache_bcr_arcv2(int cpu) 77 { 78 struct cpuinfo_arc_cache *p_slc = &cpuinfo_arc700[cpu].slc; 79 struct bcr_generic sbcr; 80 81 struct bcr_slc_cfg { 82 #ifdef CONFIG_CPU_BIG_ENDIAN 83 unsigned int pad:24, way:2, lsz:2, sz:4; 84 #else 85 unsigned int sz:4, lsz:2, way:2, pad:24; 86 #endif 87 } slc_cfg; 88 89 struct bcr_clust_cfg { 90 #ifdef CONFIG_CPU_BIG_ENDIAN 91 unsigned int pad:7, c:1, num_entries:8, num_cores:8, ver:8; 92 #else 93 unsigned int ver:8, num_cores:8, num_entries:8, c:1, pad:7; 94 #endif 95 } cbcr; 96 97 READ_BCR(ARC_REG_SLC_BCR, sbcr); 98 if (sbcr.ver) { 99 READ_BCR(ARC_REG_SLC_CFG, slc_cfg); 100 p_slc->ver = sbcr.ver; 101 p_slc->sz_k = 128 << slc_cfg.sz; 102 l2_line_sz = p_slc->line_len = (slc_cfg.lsz == 0) ? 128 : 64; 103 } 104 105 READ_BCR(ARC_REG_CLUSTER_BCR, cbcr); 106 if (cbcr.c && ioc_enable) 107 ioc_exists = 1; 108 } 109 110 void read_decode_cache_bcr(void) 111 { 112 struct cpuinfo_arc_cache *p_ic, *p_dc; 113 unsigned int cpu = smp_processor_id(); 114 struct bcr_cache { 115 #ifdef CONFIG_CPU_BIG_ENDIAN 116 unsigned int pad:12, line_len:4, sz:4, config:4, ver:8; 117 #else 118 unsigned int ver:8, config:4, sz:4, line_len:4, pad:12; 119 #endif 120 } ibcr, dbcr; 121 122 p_ic = &cpuinfo_arc700[cpu].icache; 123 READ_BCR(ARC_REG_IC_BCR, ibcr); 124 125 if (!ibcr.ver) 126 goto dc_chk; 127 128 if (ibcr.ver <= 3) { 129 BUG_ON(ibcr.config != 3); 130 p_ic->assoc = 2; /* Fixed to 2w set assoc */ 131 } else if (ibcr.ver >= 4) { 132 p_ic->assoc = 1 << ibcr.config; /* 1,2,4,8 */ 133 } 134 135 p_ic->line_len = 8 << ibcr.line_len; 136 p_ic->sz_k = 1 << (ibcr.sz - 1); 137 p_ic->ver = ibcr.ver; 138 p_ic->vipt = 1; 139 p_ic->alias = p_ic->sz_k/p_ic->assoc/TO_KB(PAGE_SIZE) > 1; 140 141 dc_chk: 142 p_dc = &cpuinfo_arc700[cpu].dcache; 143 READ_BCR(ARC_REG_DC_BCR, dbcr); 144 145 if (!dbcr.ver) 146 goto slc_chk; 147 148 if (dbcr.ver <= 3) { 149 BUG_ON(dbcr.config != 2); 150 p_dc->assoc = 4; /* Fixed to 4w set assoc */ 151 p_dc->vipt = 1; 152 p_dc->alias = p_dc->sz_k/p_dc->assoc/TO_KB(PAGE_SIZE) > 1; 153 } else if (dbcr.ver >= 4) { 154 p_dc->assoc = 1 << dbcr.config; /* 1,2,4,8 */ 155 p_dc->vipt = 0; 156 p_dc->alias = 0; /* PIPT so can't VIPT alias */ 157 } 158 159 p_dc->line_len = 16 << dbcr.line_len; 160 p_dc->sz_k = 1 << (dbcr.sz - 1); 161 p_dc->ver = dbcr.ver; 162 163 slc_chk: 164 if (is_isa_arcv2()) 165 read_decode_cache_bcr_arcv2(cpu); 166 } 167 168 /* 169 * Line Operation on {I,D}-Cache 170 */ 171 172 #define OP_INV 0x1 173 #define OP_FLUSH 0x2 174 #define OP_FLUSH_N_INV 0x3 175 #define OP_INV_IC 0x4 176 177 /* 178 * I-Cache Aliasing in ARC700 VIPT caches (MMU v1-v3) 179 * 180 * ARC VIPT I-cache uses vaddr to index into cache and paddr to match the tag. 181 * The orig Cache Management Module "CDU" only required paddr to invalidate a 182 * certain line since it sufficed as index in Non-Aliasing VIPT cache-geometry. 183 * Infact for distinct V1,V2,P: all of {V1-P},{V2-P},{P-P} would end up fetching 184 * the exact same line. 185 * 186 * However for larger Caches (way-size > page-size) - i.e. in Aliasing config, 187 * paddr alone could not be used to correctly index the cache. 188 * 189 * ------------------ 190 * MMU v1/v2 (Fixed Page Size 8k) 191 * ------------------ 192 * The solution was to provide CDU with these additonal vaddr bits. These 193 * would be bits [x:13], x would depend on cache-geometry, 13 comes from 194 * standard page size of 8k. 195 * H/w folks chose [17:13] to be a future safe range, and moreso these 5 bits 196 * of vaddr could easily be "stuffed" in the paddr as bits [4:0] since the 197 * orig 5 bits of paddr were anyways ignored by CDU line ops, as they 198 * represent the offset within cache-line. The adv of using this "clumsy" 199 * interface for additional info was no new reg was needed in CDU programming 200 * model. 201 * 202 * 17:13 represented the max num of bits passable, actual bits needed were 203 * fewer, based on the num-of-aliases possible. 204 * -for 2 alias possibility, only bit 13 needed (32K cache) 205 * -for 4 alias possibility, bits 14:13 needed (64K cache) 206 * 207 * ------------------ 208 * MMU v3 209 * ------------------ 210 * This ver of MMU supports variable page sizes (1k-16k): although Linux will 211 * only support 8k (default), 16k and 4k. 212 * However from hardware perspective, smaller page sizes aggrevate aliasing 213 * meaning more vaddr bits needed to disambiguate the cache-line-op ; 214 * the existing scheme of piggybacking won't work for certain configurations. 215 * Two new registers IC_PTAG and DC_PTAG inttoduced. 216 * "tag" bits are provided in PTAG, index bits in existing IVIL/IVDL/FLDL regs 217 */ 218 219 static inline 220 void __cache_line_loop_v2(unsigned long paddr, unsigned long vaddr, 221 unsigned long sz, const int op) 222 { 223 unsigned int aux_cmd; 224 int num_lines; 225 const int full_page = __builtin_constant_p(sz) && sz == PAGE_SIZE; 226 227 if (op == OP_INV_IC) { 228 aux_cmd = ARC_REG_IC_IVIL; 229 } else { 230 /* d$ cmd: INV (discard or wback-n-discard) OR FLUSH (wback) */ 231 aux_cmd = op & OP_INV ? ARC_REG_DC_IVDL : ARC_REG_DC_FLDL; 232 } 233 234 /* Ensure we properly floor/ceil the non-line aligned/sized requests 235 * and have @paddr - aligned to cache line and integral @num_lines. 236 * This however can be avoided for page sized since: 237 * -@paddr will be cache-line aligned already (being page aligned) 238 * -@sz will be integral multiple of line size (being page sized). 239 */ 240 if (!full_page) { 241 sz += paddr & ~CACHE_LINE_MASK; 242 paddr &= CACHE_LINE_MASK; 243 vaddr &= CACHE_LINE_MASK; 244 } 245 246 num_lines = DIV_ROUND_UP(sz, L1_CACHE_BYTES); 247 248 /* MMUv2 and before: paddr contains stuffed vaddrs bits */ 249 paddr |= (vaddr >> PAGE_SHIFT) & 0x1F; 250 251 while (num_lines-- > 0) { 252 write_aux_reg(aux_cmd, paddr); 253 paddr += L1_CACHE_BYTES; 254 } 255 } 256 257 static inline 258 void __cache_line_loop_v3(unsigned long paddr, unsigned long vaddr, 259 unsigned long sz, const int op) 260 { 261 unsigned int aux_cmd, aux_tag; 262 int num_lines; 263 const int full_page = __builtin_constant_p(sz) && sz == PAGE_SIZE; 264 265 if (op == OP_INV_IC) { 266 aux_cmd = ARC_REG_IC_IVIL; 267 aux_tag = ARC_REG_IC_PTAG; 268 } else { 269 aux_cmd = op & OP_INV ? ARC_REG_DC_IVDL : ARC_REG_DC_FLDL; 270 aux_tag = ARC_REG_DC_PTAG; 271 } 272 273 /* Ensure we properly floor/ceil the non-line aligned/sized requests 274 * and have @paddr - aligned to cache line and integral @num_lines. 275 * This however can be avoided for page sized since: 276 * -@paddr will be cache-line aligned already (being page aligned) 277 * -@sz will be integral multiple of line size (being page sized). 278 */ 279 if (!full_page) { 280 sz += paddr & ~CACHE_LINE_MASK; 281 paddr &= CACHE_LINE_MASK; 282 vaddr &= CACHE_LINE_MASK; 283 } 284 num_lines = DIV_ROUND_UP(sz, L1_CACHE_BYTES); 285 286 /* 287 * MMUv3, cache ops require paddr in PTAG reg 288 * if V-P const for loop, PTAG can be written once outside loop 289 */ 290 if (full_page) 291 write_aux_reg(aux_tag, paddr); 292 293 while (num_lines-- > 0) { 294 if (!full_page) { 295 write_aux_reg(aux_tag, paddr); 296 paddr += L1_CACHE_BYTES; 297 } 298 299 write_aux_reg(aux_cmd, vaddr); 300 vaddr += L1_CACHE_BYTES; 301 } 302 } 303 304 /* 305 * In HS38x (MMU v4), although icache is VIPT, only paddr is needed for cache 306 * maintenance ops (in IVIL reg), as long as icache doesn't alias. 307 * 308 * For Aliasing icache, vaddr is also needed (in IVIL), while paddr is 309 * specified in PTAG (similar to MMU v3) 310 */ 311 static inline 312 void __cache_line_loop_v4(unsigned long paddr, unsigned long vaddr, 313 unsigned long sz, const int cacheop) 314 { 315 unsigned int aux_cmd; 316 int num_lines; 317 const int full_page_op = __builtin_constant_p(sz) && sz == PAGE_SIZE; 318 319 if (cacheop == OP_INV_IC) { 320 aux_cmd = ARC_REG_IC_IVIL; 321 } else { 322 /* d$ cmd: INV (discard or wback-n-discard) OR FLUSH (wback) */ 323 aux_cmd = cacheop & OP_INV ? ARC_REG_DC_IVDL : ARC_REG_DC_FLDL; 324 } 325 326 /* Ensure we properly floor/ceil the non-line aligned/sized requests 327 * and have @paddr - aligned to cache line and integral @num_lines. 328 * This however can be avoided for page sized since: 329 * -@paddr will be cache-line aligned already (being page aligned) 330 * -@sz will be integral multiple of line size (being page sized). 331 */ 332 if (!full_page_op) { 333 sz += paddr & ~CACHE_LINE_MASK; 334 paddr &= CACHE_LINE_MASK; 335 } 336 337 num_lines = DIV_ROUND_UP(sz, L1_CACHE_BYTES); 338 339 while (num_lines-- > 0) { 340 write_aux_reg(aux_cmd, paddr); 341 paddr += L1_CACHE_BYTES; 342 } 343 } 344 345 #if (CONFIG_ARC_MMU_VER < 3) 346 #define __cache_line_loop __cache_line_loop_v2 347 #elif (CONFIG_ARC_MMU_VER == 3) 348 #define __cache_line_loop __cache_line_loop_v3 349 #elif (CONFIG_ARC_MMU_VER > 3) 350 #define __cache_line_loop __cache_line_loop_v4 351 #endif 352 353 #ifdef CONFIG_ARC_HAS_DCACHE 354 355 /*************************************************************** 356 * Machine specific helpers for Entire D-Cache or Per Line ops 357 */ 358 359 static inline void __before_dc_op(const int op) 360 { 361 if (op == OP_FLUSH_N_INV) { 362 /* Dcache provides 2 cmd: FLUSH or INV 363 * INV inturn has sub-modes: DISCARD or FLUSH-BEFORE 364 * flush-n-inv is achieved by INV cmd but with IM=1 365 * So toggle INV sub-mode depending on op request and default 366 */ 367 const unsigned int ctl = ARC_REG_DC_CTRL; 368 write_aux_reg(ctl, read_aux_reg(ctl) | DC_CTRL_INV_MODE_FLUSH); 369 } 370 } 371 372 static inline void __after_dc_op(const int op) 373 { 374 if (op & OP_FLUSH) { 375 const unsigned int ctl = ARC_REG_DC_CTRL; 376 unsigned int reg; 377 378 /* flush / flush-n-inv both wait */ 379 while ((reg = read_aux_reg(ctl)) & DC_CTRL_FLUSH_STATUS) 380 ; 381 382 /* Switch back to default Invalidate mode */ 383 if (op == OP_FLUSH_N_INV) 384 write_aux_reg(ctl, reg & ~DC_CTRL_INV_MODE_FLUSH); 385 } 386 } 387 388 /* 389 * Operation on Entire D-Cache 390 * @op = {OP_INV, OP_FLUSH, OP_FLUSH_N_INV} 391 * Note that constant propagation ensures all the checks are gone 392 * in generated code 393 */ 394 static inline void __dc_entire_op(const int op) 395 { 396 int aux; 397 398 __before_dc_op(op); 399 400 if (op & OP_INV) /* Inv or flush-n-inv use same cmd reg */ 401 aux = ARC_REG_DC_IVDC; 402 else 403 aux = ARC_REG_DC_FLSH; 404 405 write_aux_reg(aux, 0x1); 406 407 __after_dc_op(op); 408 } 409 410 /* For kernel mappings cache operation: index is same as paddr */ 411 #define __dc_line_op_k(p, sz, op) __dc_line_op(p, p, sz, op) 412 413 /* 414 * D-Cache Line ops: Per Line INV (discard or wback+discard) or FLUSH (wback) 415 */ 416 static inline void __dc_line_op(unsigned long paddr, unsigned long vaddr, 417 unsigned long sz, const int op) 418 { 419 unsigned long flags; 420 421 local_irq_save(flags); 422 423 __before_dc_op(op); 424 425 __cache_line_loop(paddr, vaddr, sz, op); 426 427 __after_dc_op(op); 428 429 local_irq_restore(flags); 430 } 431 432 #else 433 434 #define __dc_entire_op(op) 435 #define __dc_line_op(paddr, vaddr, sz, op) 436 #define __dc_line_op_k(paddr, sz, op) 437 438 #endif /* CONFIG_ARC_HAS_DCACHE */ 439 440 #ifdef CONFIG_ARC_HAS_ICACHE 441 442 static inline void __ic_entire_inv(void) 443 { 444 write_aux_reg(ARC_REG_IC_IVIC, 1); 445 read_aux_reg(ARC_REG_IC_CTRL); /* blocks */ 446 } 447 448 static inline void 449 __ic_line_inv_vaddr_local(unsigned long paddr, unsigned long vaddr, 450 unsigned long sz) 451 { 452 unsigned long flags; 453 454 local_irq_save(flags); 455 (*_cache_line_loop_ic_fn)(paddr, vaddr, sz, OP_INV_IC); 456 local_irq_restore(flags); 457 } 458 459 #ifndef CONFIG_SMP 460 461 #define __ic_line_inv_vaddr(p, v, s) __ic_line_inv_vaddr_local(p, v, s) 462 463 #else 464 465 struct ic_inv_args { 466 unsigned long paddr, vaddr; 467 int sz; 468 }; 469 470 static void __ic_line_inv_vaddr_helper(void *info) 471 { 472 struct ic_inv_args *ic_inv = info; 473 474 __ic_line_inv_vaddr_local(ic_inv->paddr, ic_inv->vaddr, ic_inv->sz); 475 } 476 477 static void __ic_line_inv_vaddr(unsigned long paddr, unsigned long vaddr, 478 unsigned long sz) 479 { 480 struct ic_inv_args ic_inv = { 481 .paddr = paddr, 482 .vaddr = vaddr, 483 .sz = sz 484 }; 485 486 on_each_cpu(__ic_line_inv_vaddr_helper, &ic_inv, 1); 487 } 488 489 #endif /* CONFIG_SMP */ 490 491 #else /* !CONFIG_ARC_HAS_ICACHE */ 492 493 #define __ic_entire_inv() 494 #define __ic_line_inv_vaddr(pstart, vstart, sz) 495 496 #endif /* CONFIG_ARC_HAS_ICACHE */ 497 498 noinline void slc_op(unsigned long paddr, unsigned long sz, const int op) 499 { 500 #ifdef CONFIG_ISA_ARCV2 501 /* 502 * SLC is shared between all cores and concurrent aux operations from 503 * multiple cores need to be serialized using a spinlock 504 * A concurrent operation can be silently ignored and/or the old/new 505 * operation can remain incomplete forever (lockup in SLC_CTRL_BUSY loop 506 * below) 507 */ 508 static DEFINE_SPINLOCK(lock); 509 unsigned long flags; 510 unsigned int ctrl; 511 512 spin_lock_irqsave(&lock, flags); 513 514 /* 515 * The Region Flush operation is specified by CTRL.RGN_OP[11..9] 516 * - b'000 (default) is Flush, 517 * - b'001 is Invalidate if CTRL.IM == 0 518 * - b'001 is Flush-n-Invalidate if CTRL.IM == 1 519 */ 520 ctrl = read_aux_reg(ARC_REG_SLC_CTRL); 521 522 /* Don't rely on default value of IM bit */ 523 if (!(op & OP_FLUSH)) /* i.e. OP_INV */ 524 ctrl &= ~SLC_CTRL_IM; /* clear IM: Disable flush before Inv */ 525 else 526 ctrl |= SLC_CTRL_IM; 527 528 if (op & OP_INV) 529 ctrl |= SLC_CTRL_RGN_OP_INV; /* Inv or flush-n-inv */ 530 else 531 ctrl &= ~SLC_CTRL_RGN_OP_INV; 532 533 write_aux_reg(ARC_REG_SLC_CTRL, ctrl); 534 535 /* 536 * Lower bits are ignored, no need to clip 537 * END needs to be setup before START (latter triggers the operation) 538 * END can't be same as START, so add (l2_line_sz - 1) to sz 539 */ 540 write_aux_reg(ARC_REG_SLC_RGN_END, (paddr + sz + l2_line_sz - 1)); 541 write_aux_reg(ARC_REG_SLC_RGN_START, paddr); 542 543 while (read_aux_reg(ARC_REG_SLC_CTRL) & SLC_CTRL_BUSY); 544 545 spin_unlock_irqrestore(&lock, flags); 546 #endif 547 } 548 549 /*********************************************************** 550 * Exported APIs 551 */ 552 553 /* 554 * Handle cache congruency of kernel and userspace mappings of page when kernel 555 * writes-to/reads-from 556 * 557 * The idea is to defer flushing of kernel mapping after a WRITE, possible if: 558 * -dcache is NOT aliasing, hence any U/K-mappings of page are congruent 559 * -U-mapping doesn't exist yet for page (finalised in update_mmu_cache) 560 * -In SMP, if hardware caches are coherent 561 * 562 * There's a corollary case, where kernel READs from a userspace mapped page. 563 * If the U-mapping is not congruent to to K-mapping, former needs flushing. 564 */ 565 void flush_dcache_page(struct page *page) 566 { 567 struct address_space *mapping; 568 569 if (!cache_is_vipt_aliasing()) { 570 clear_bit(PG_dc_clean, &page->flags); 571 return; 572 } 573 574 /* don't handle anon pages here */ 575 mapping = page_mapping(page); 576 if (!mapping) 577 return; 578 579 /* 580 * pagecache page, file not yet mapped to userspace 581 * Make a note that K-mapping is dirty 582 */ 583 if (!mapping_mapped(mapping)) { 584 clear_bit(PG_dc_clean, &page->flags); 585 } else if (page_mapped(page)) { 586 587 /* kernel reading from page with U-mapping */ 588 unsigned long paddr = (unsigned long)page_address(page); 589 unsigned long vaddr = page->index << PAGE_CACHE_SHIFT; 590 591 if (addr_not_cache_congruent(paddr, vaddr)) 592 __flush_dcache_page(paddr, vaddr); 593 } 594 } 595 EXPORT_SYMBOL(flush_dcache_page); 596 597 /* 598 * DMA ops for systems with L1 cache only 599 * Make memory coherent with L1 cache by flushing/invalidating L1 lines 600 */ 601 static void __dma_cache_wback_inv_l1(unsigned long start, unsigned long sz) 602 { 603 __dc_line_op_k(start, sz, OP_FLUSH_N_INV); 604 } 605 606 static void __dma_cache_inv_l1(unsigned long start, unsigned long sz) 607 { 608 __dc_line_op_k(start, sz, OP_INV); 609 } 610 611 static void __dma_cache_wback_l1(unsigned long start, unsigned long sz) 612 { 613 __dc_line_op_k(start, sz, OP_FLUSH); 614 } 615 616 /* 617 * DMA ops for systems with both L1 and L2 caches, but without IOC 618 * Both L1 and L2 lines need to be explicity flushed/invalidated 619 */ 620 static void __dma_cache_wback_inv_slc(unsigned long start, unsigned long sz) 621 { 622 __dc_line_op_k(start, sz, OP_FLUSH_N_INV); 623 slc_op(start, sz, OP_FLUSH_N_INV); 624 } 625 626 static void __dma_cache_inv_slc(unsigned long start, unsigned long sz) 627 { 628 __dc_line_op_k(start, sz, OP_INV); 629 slc_op(start, sz, OP_INV); 630 } 631 632 static void __dma_cache_wback_slc(unsigned long start, unsigned long sz) 633 { 634 __dc_line_op_k(start, sz, OP_FLUSH); 635 slc_op(start, sz, OP_FLUSH); 636 } 637 638 /* 639 * DMA ops for systems with IOC 640 * IOC hardware snoops all DMA traffic keeping the caches consistent with 641 * memory - eliding need for any explicit cache maintenance of DMA buffers 642 */ 643 static void __dma_cache_wback_inv_ioc(unsigned long start, unsigned long sz) {} 644 static void __dma_cache_inv_ioc(unsigned long start, unsigned long sz) {} 645 static void __dma_cache_wback_ioc(unsigned long start, unsigned long sz) {} 646 647 /* 648 * Exported DMA API 649 */ 650 void dma_cache_wback_inv(unsigned long start, unsigned long sz) 651 { 652 __dma_cache_wback_inv(start, sz); 653 } 654 EXPORT_SYMBOL(dma_cache_wback_inv); 655 656 void dma_cache_inv(unsigned long start, unsigned long sz) 657 { 658 __dma_cache_inv(start, sz); 659 } 660 EXPORT_SYMBOL(dma_cache_inv); 661 662 void dma_cache_wback(unsigned long start, unsigned long sz) 663 { 664 __dma_cache_wback(start, sz); 665 } 666 EXPORT_SYMBOL(dma_cache_wback); 667 668 /* 669 * This is API for making I/D Caches consistent when modifying 670 * kernel code (loadable modules, kprobes, kgdb...) 671 * This is called on insmod, with kernel virtual address for CODE of 672 * the module. ARC cache maintenance ops require PHY address thus we 673 * need to convert vmalloc addr to PHY addr 674 */ 675 void flush_icache_range(unsigned long kstart, unsigned long kend) 676 { 677 unsigned int tot_sz; 678 679 WARN(kstart < TASK_SIZE, "%s() can't handle user vaddr", __func__); 680 681 /* Shortcut for bigger flush ranges. 682 * Here we don't care if this was kernel virtual or phy addr 683 */ 684 tot_sz = kend - kstart; 685 if (tot_sz > PAGE_SIZE) { 686 flush_cache_all(); 687 return; 688 } 689 690 /* Case: Kernel Phy addr (0x8000_0000 onwards) */ 691 if (likely(kstart > PAGE_OFFSET)) { 692 /* 693 * The 2nd arg despite being paddr will be used to index icache 694 * This is OK since no alternate virtual mappings will exist 695 * given the callers for this case: kprobe/kgdb in built-in 696 * kernel code only. 697 */ 698 __sync_icache_dcache(kstart, kstart, kend - kstart); 699 return; 700 } 701 702 /* 703 * Case: Kernel Vaddr (0x7000_0000 to 0x7fff_ffff) 704 * (1) ARC Cache Maintenance ops only take Phy addr, hence special 705 * handling of kernel vaddr. 706 * 707 * (2) Despite @tot_sz being < PAGE_SIZE (bigger cases handled already), 708 * it still needs to handle a 2 page scenario, where the range 709 * straddles across 2 virtual pages and hence need for loop 710 */ 711 while (tot_sz > 0) { 712 unsigned int off, sz; 713 unsigned long phy, pfn; 714 715 off = kstart % PAGE_SIZE; 716 pfn = vmalloc_to_pfn((void *)kstart); 717 phy = (pfn << PAGE_SHIFT) + off; 718 sz = min_t(unsigned int, tot_sz, PAGE_SIZE - off); 719 __sync_icache_dcache(phy, kstart, sz); 720 kstart += sz; 721 tot_sz -= sz; 722 } 723 } 724 EXPORT_SYMBOL(flush_icache_range); 725 726 /* 727 * General purpose helper to make I and D cache lines consistent. 728 * @paddr is phy addr of region 729 * @vaddr is typically user vaddr (breakpoint) or kernel vaddr (vmalloc) 730 * However in one instance, when called by kprobe (for a breakpt in 731 * builtin kernel code) @vaddr will be paddr only, meaning CDU operation will 732 * use a paddr to index the cache (despite VIPT). This is fine since since a 733 * builtin kernel page will not have any virtual mappings. 734 * kprobe on loadable module will be kernel vaddr. 735 */ 736 void __sync_icache_dcache(unsigned long paddr, unsigned long vaddr, int len) 737 { 738 __dc_line_op(paddr, vaddr, len, OP_FLUSH_N_INV); 739 __ic_line_inv_vaddr(paddr, vaddr, len); 740 } 741 742 /* wrapper to compile time eliminate alignment checks in flush loop */ 743 void __inv_icache_page(unsigned long paddr, unsigned long vaddr) 744 { 745 __ic_line_inv_vaddr(paddr, vaddr, PAGE_SIZE); 746 } 747 748 /* 749 * wrapper to clearout kernel or userspace mappings of a page 750 * For kernel mappings @vaddr == @paddr 751 */ 752 void __flush_dcache_page(unsigned long paddr, unsigned long vaddr) 753 { 754 __dc_line_op(paddr, vaddr & PAGE_MASK, PAGE_SIZE, OP_FLUSH_N_INV); 755 } 756 757 noinline void flush_cache_all(void) 758 { 759 unsigned long flags; 760 761 local_irq_save(flags); 762 763 __ic_entire_inv(); 764 __dc_entire_op(OP_FLUSH_N_INV); 765 766 local_irq_restore(flags); 767 768 } 769 770 #ifdef CONFIG_ARC_CACHE_VIPT_ALIASING 771 772 void flush_cache_mm(struct mm_struct *mm) 773 { 774 flush_cache_all(); 775 } 776 777 void flush_cache_page(struct vm_area_struct *vma, unsigned long u_vaddr, 778 unsigned long pfn) 779 { 780 unsigned int paddr = pfn << PAGE_SHIFT; 781 782 u_vaddr &= PAGE_MASK; 783 784 __flush_dcache_page(paddr, u_vaddr); 785 786 if (vma->vm_flags & VM_EXEC) 787 __inv_icache_page(paddr, u_vaddr); 788 } 789 790 void flush_cache_range(struct vm_area_struct *vma, unsigned long start, 791 unsigned long end) 792 { 793 flush_cache_all(); 794 } 795 796 void flush_anon_page(struct vm_area_struct *vma, struct page *page, 797 unsigned long u_vaddr) 798 { 799 /* TBD: do we really need to clear the kernel mapping */ 800 __flush_dcache_page(page_address(page), u_vaddr); 801 __flush_dcache_page(page_address(page), page_address(page)); 802 803 } 804 805 #endif 806 807 void copy_user_highpage(struct page *to, struct page *from, 808 unsigned long u_vaddr, struct vm_area_struct *vma) 809 { 810 unsigned long kfrom = (unsigned long)page_address(from); 811 unsigned long kto = (unsigned long)page_address(to); 812 int clean_src_k_mappings = 0; 813 814 /* 815 * If SRC page was already mapped in userspace AND it's U-mapping is 816 * not congruent with K-mapping, sync former to physical page so that 817 * K-mapping in memcpy below, sees the right data 818 * 819 * Note that while @u_vaddr refers to DST page's userspace vaddr, it is 820 * equally valid for SRC page as well 821 */ 822 if (page_mapped(from) && addr_not_cache_congruent(kfrom, u_vaddr)) { 823 __flush_dcache_page(kfrom, u_vaddr); 824 clean_src_k_mappings = 1; 825 } 826 827 copy_page((void *)kto, (void *)kfrom); 828 829 /* 830 * Mark DST page K-mapping as dirty for a later finalization by 831 * update_mmu_cache(). Although the finalization could have been done 832 * here as well (given that both vaddr/paddr are available). 833 * But update_mmu_cache() already has code to do that for other 834 * non copied user pages (e.g. read faults which wire in pagecache page 835 * directly). 836 */ 837 clear_bit(PG_dc_clean, &to->flags); 838 839 /* 840 * if SRC was already usermapped and non-congruent to kernel mapping 841 * sync the kernel mapping back to physical page 842 */ 843 if (clean_src_k_mappings) { 844 __flush_dcache_page(kfrom, kfrom); 845 set_bit(PG_dc_clean, &from->flags); 846 } else { 847 clear_bit(PG_dc_clean, &from->flags); 848 } 849 } 850 851 void clear_user_page(void *to, unsigned long u_vaddr, struct page *page) 852 { 853 clear_page(to); 854 clear_bit(PG_dc_clean, &page->flags); 855 } 856 857 858 /********************************************************************** 859 * Explicit Cache flush request from user space via syscall 860 * Needed for JITs which generate code on the fly 861 */ 862 SYSCALL_DEFINE3(cacheflush, uint32_t, start, uint32_t, sz, uint32_t, flags) 863 { 864 /* TBD: optimize this */ 865 flush_cache_all(); 866 return 0; 867 } 868 869 void arc_cache_init(void) 870 { 871 unsigned int __maybe_unused cpu = smp_processor_id(); 872 char str[256]; 873 874 printk(arc_cache_mumbojumbo(0, str, sizeof(str))); 875 876 if (IS_ENABLED(CONFIG_ARC_HAS_ICACHE)) { 877 struct cpuinfo_arc_cache *ic = &cpuinfo_arc700[cpu].icache; 878 879 if (!ic->ver) 880 panic("cache support enabled but non-existent cache\n"); 881 882 if (ic->line_len != L1_CACHE_BYTES) 883 panic("ICache line [%d] != kernel Config [%d]", 884 ic->line_len, L1_CACHE_BYTES); 885 886 if (ic->ver != CONFIG_ARC_MMU_VER) 887 panic("Cache ver [%d] doesn't match MMU ver [%d]\n", 888 ic->ver, CONFIG_ARC_MMU_VER); 889 890 /* 891 * In MMU v4 (HS38x) the alising icache config uses IVIL/PTAG 892 * pair to provide vaddr/paddr respectively, just as in MMU v3 893 */ 894 if (is_isa_arcv2() && ic->alias) 895 _cache_line_loop_ic_fn = __cache_line_loop_v3; 896 else 897 _cache_line_loop_ic_fn = __cache_line_loop; 898 } 899 900 if (IS_ENABLED(CONFIG_ARC_HAS_DCACHE)) { 901 struct cpuinfo_arc_cache *dc = &cpuinfo_arc700[cpu].dcache; 902 903 if (!dc->ver) 904 panic("cache support enabled but non-existent cache\n"); 905 906 if (dc->line_len != L1_CACHE_BYTES) 907 panic("DCache line [%d] != kernel Config [%d]", 908 dc->line_len, L1_CACHE_BYTES); 909 910 /* check for D-Cache aliasing on ARCompact: ARCv2 has PIPT */ 911 if (is_isa_arcompact()) { 912 int handled = IS_ENABLED(CONFIG_ARC_CACHE_VIPT_ALIASING); 913 914 if (dc->alias && !handled) 915 panic("Enable CONFIG_ARC_CACHE_VIPT_ALIASING\n"); 916 else if (!dc->alias && handled) 917 panic("Disable CONFIG_ARC_CACHE_VIPT_ALIASING\n"); 918 } 919 } 920 921 if (is_isa_arcv2() && l2_line_sz && !slc_enable) { 922 923 /* IM set : flush before invalidate */ 924 write_aux_reg(ARC_REG_SLC_CTRL, 925 read_aux_reg(ARC_REG_SLC_CTRL) | SLC_CTRL_IM); 926 927 write_aux_reg(ARC_REG_SLC_INVALIDATE, 1); 928 929 /* Important to wait for flush to complete */ 930 while (read_aux_reg(ARC_REG_SLC_CTRL) & SLC_CTRL_BUSY); 931 write_aux_reg(ARC_REG_SLC_CTRL, 932 read_aux_reg(ARC_REG_SLC_CTRL) | SLC_CTRL_DISABLE); 933 } 934 935 if (is_isa_arcv2() && ioc_exists) { 936 /* IO coherency base - 0x8z */ 937 write_aux_reg(ARC_REG_IO_COH_AP0_BASE, 0x80000); 938 /* IO coherency aperture size - 512Mb: 0x8z-0xAz */ 939 write_aux_reg(ARC_REG_IO_COH_AP0_SIZE, 0x11); 940 /* Enable partial writes */ 941 write_aux_reg(ARC_REG_IO_COH_PARTIAL, 1); 942 /* Enable IO coherency */ 943 write_aux_reg(ARC_REG_IO_COH_ENABLE, 1); 944 945 __dma_cache_wback_inv = __dma_cache_wback_inv_ioc; 946 __dma_cache_inv = __dma_cache_inv_ioc; 947 __dma_cache_wback = __dma_cache_wback_ioc; 948 } else if (is_isa_arcv2() && l2_line_sz && slc_enable) { 949 __dma_cache_wback_inv = __dma_cache_wback_inv_slc; 950 __dma_cache_inv = __dma_cache_inv_slc; 951 __dma_cache_wback = __dma_cache_wback_slc; 952 } else { 953 __dma_cache_wback_inv = __dma_cache_wback_inv_l1; 954 __dma_cache_inv = __dma_cache_inv_l1; 955 __dma_cache_wback = __dma_cache_wback_l1; 956 } 957 } 958