1 /* 2 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com) 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 */ 8 9 #include <linux/seq_file.h> 10 #include <linux/fs.h> 11 #include <linux/delay.h> 12 #include <linux/root_dev.h> 13 #include <linux/clk.h> 14 #include <linux/clk-provider.h> 15 #include <linux/clocksource.h> 16 #include <linux/console.h> 17 #include <linux/module.h> 18 #include <linux/cpu.h> 19 #include <linux/of_fdt.h> 20 #include <linux/of.h> 21 #include <linux/cache.h> 22 #include <uapi/linux/mount.h> 23 #include <asm/sections.h> 24 #include <asm/arcregs.h> 25 #include <asm/tlb.h> 26 #include <asm/setup.h> 27 #include <asm/page.h> 28 #include <asm/irq.h> 29 #include <asm/unwind.h> 30 #include <asm/mach_desc.h> 31 #include <asm/smp.h> 32 33 #define FIX_PTR(x) __asm__ __volatile__(";" : "+r"(x)) 34 35 unsigned int intr_to_DE_cnt; 36 37 /* Part of U-boot ABI: see head.S */ 38 int __initdata uboot_tag; 39 char __initdata *uboot_arg; 40 41 const struct machine_desc *machine_desc; 42 43 struct task_struct *_current_task[NR_CPUS]; /* For stack switching */ 44 45 struct cpuinfo_arc cpuinfo_arc700[NR_CPUS]; 46 47 static const struct id_to_str arc_cpu_rel[] = { 48 #ifdef CONFIG_ISA_ARCOMPACT 49 { 0x34, "R4.10"}, 50 { 0x35, "R4.11"}, 51 #else 52 { 0x51, "R2.0" }, 53 { 0x52, "R2.1" }, 54 { 0x53, "R3.0" }, 55 { 0x54, "R3.10a" }, 56 #endif 57 { 0x00, NULL } 58 }; 59 60 static const struct id_to_str arc_cpu_nm[] = { 61 #ifdef CONFIG_ISA_ARCOMPACT 62 { 0x20, "ARC 600" }, 63 { 0x30, "ARC 770" }, /* 750 identified seperately */ 64 #else 65 { 0x40, "ARC EM" }, 66 { 0x50, "ARC HS38" }, 67 { 0x54, "ARC HS48" }, 68 #endif 69 { 0x00, "Unknown" } 70 }; 71 72 static void read_decode_ccm_bcr(struct cpuinfo_arc *cpu) 73 { 74 if (is_isa_arcompact()) { 75 struct bcr_iccm_arcompact iccm; 76 struct bcr_dccm_arcompact dccm; 77 78 READ_BCR(ARC_REG_ICCM_BUILD, iccm); 79 if (iccm.ver) { 80 cpu->iccm.sz = 4096 << iccm.sz; /* 8K to 512K */ 81 cpu->iccm.base_addr = iccm.base << 16; 82 } 83 84 READ_BCR(ARC_REG_DCCM_BUILD, dccm); 85 if (dccm.ver) { 86 unsigned long base; 87 cpu->dccm.sz = 2048 << dccm.sz; /* 2K to 256K */ 88 89 base = read_aux_reg(ARC_REG_DCCM_BASE_BUILD); 90 cpu->dccm.base_addr = base & ~0xF; 91 } 92 } else { 93 struct bcr_iccm_arcv2 iccm; 94 struct bcr_dccm_arcv2 dccm; 95 unsigned long region; 96 97 READ_BCR(ARC_REG_ICCM_BUILD, iccm); 98 if (iccm.ver) { 99 cpu->iccm.sz = 256 << iccm.sz00; /* 512B to 16M */ 100 if (iccm.sz00 == 0xF && iccm.sz01 > 0) 101 cpu->iccm.sz <<= iccm.sz01; 102 103 region = read_aux_reg(ARC_REG_AUX_ICCM); 104 cpu->iccm.base_addr = region & 0xF0000000; 105 } 106 107 READ_BCR(ARC_REG_DCCM_BUILD, dccm); 108 if (dccm.ver) { 109 cpu->dccm.sz = 256 << dccm.sz0; 110 if (dccm.sz0 == 0xF && dccm.sz1 > 0) 111 cpu->dccm.sz <<= dccm.sz1; 112 113 region = read_aux_reg(ARC_REG_AUX_DCCM); 114 cpu->dccm.base_addr = region & 0xF0000000; 115 } 116 } 117 } 118 119 static void read_arc_build_cfg_regs(void) 120 { 121 struct bcr_timer timer; 122 struct bcr_generic bcr; 123 struct cpuinfo_arc *cpu = &cpuinfo_arc700[smp_processor_id()]; 124 const struct id_to_str *tbl; 125 struct bcr_isa_arcv2 isa; 126 struct bcr_actionpoint ap; 127 128 FIX_PTR(cpu); 129 130 READ_BCR(AUX_IDENTITY, cpu->core); 131 132 for (tbl = &arc_cpu_rel[0]; tbl->id != 0; tbl++) { 133 if (cpu->core.family == tbl->id) { 134 cpu->details = tbl->str; 135 break; 136 } 137 } 138 139 for (tbl = &arc_cpu_nm[0]; tbl->id != 0; tbl++) { 140 if ((cpu->core.family & 0xF4) == tbl->id) 141 break; 142 } 143 cpu->name = tbl->str; 144 145 READ_BCR(ARC_REG_TIMERS_BCR, timer); 146 cpu->extn.timer0 = timer.t0; 147 cpu->extn.timer1 = timer.t1; 148 cpu->extn.rtc = timer.rtc; 149 150 cpu->vec_base = read_aux_reg(AUX_INTR_VEC_BASE); 151 152 READ_BCR(ARC_REG_MUL_BCR, cpu->extn_mpy); 153 154 cpu->extn.norm = read_aux_reg(ARC_REG_NORM_BCR) > 1 ? 1 : 0; /* 2,3 */ 155 cpu->extn.barrel = read_aux_reg(ARC_REG_BARREL_BCR) > 1 ? 1 : 0; /* 2,3 */ 156 cpu->extn.swap = read_aux_reg(ARC_REG_SWAP_BCR) ? 1 : 0; /* 1,3 */ 157 cpu->extn.crc = read_aux_reg(ARC_REG_CRC_BCR) ? 1 : 0; 158 cpu->extn.minmax = read_aux_reg(ARC_REG_MIXMAX_BCR) > 1 ? 1 : 0; /* 2 */ 159 cpu->extn.swape = (cpu->core.family >= 0x34) ? 1 : 160 IS_ENABLED(CONFIG_ARC_HAS_SWAPE); 161 162 READ_BCR(ARC_REG_XY_MEM_BCR, cpu->extn_xymem); 163 164 /* Read CCM BCRs for boot reporting even if not enabled in Kconfig */ 165 read_decode_ccm_bcr(cpu); 166 167 read_decode_mmu_bcr(); 168 read_decode_cache_bcr(); 169 170 if (is_isa_arcompact()) { 171 struct bcr_fp_arcompact sp, dp; 172 struct bcr_bpu_arcompact bpu; 173 174 READ_BCR(ARC_REG_FP_BCR, sp); 175 READ_BCR(ARC_REG_DPFP_BCR, dp); 176 cpu->extn.fpu_sp = sp.ver ? 1 : 0; 177 cpu->extn.fpu_dp = dp.ver ? 1 : 0; 178 179 READ_BCR(ARC_REG_BPU_BCR, bpu); 180 cpu->bpu.ver = bpu.ver; 181 cpu->bpu.full = bpu.fam ? 1 : 0; 182 if (bpu.ent) { 183 cpu->bpu.num_cache = 256 << (bpu.ent - 1); 184 cpu->bpu.num_pred = 256 << (bpu.ent - 1); 185 } 186 } else { 187 struct bcr_fp_arcv2 spdp; 188 struct bcr_bpu_arcv2 bpu; 189 190 READ_BCR(ARC_REG_FP_V2_BCR, spdp); 191 cpu->extn.fpu_sp = spdp.sp ? 1 : 0; 192 cpu->extn.fpu_dp = spdp.dp ? 1 : 0; 193 194 READ_BCR(ARC_REG_BPU_BCR, bpu); 195 cpu->bpu.ver = bpu.ver; 196 cpu->bpu.full = bpu.ft; 197 cpu->bpu.num_cache = 256 << bpu.bce; 198 cpu->bpu.num_pred = 2048 << bpu.pte; 199 cpu->bpu.ret_stk = 4 << bpu.rse; 200 201 if (cpu->core.family >= 0x54) { 202 203 struct bcr_uarch_build_arcv2 uarch; 204 205 /* 206 * The first 0x54 core (uarch maj:min 0:1 or 0:2) was 207 * dual issue only (HS4x). But next uarch rev (1:0) 208 * allows it be configured for single issue (HS3x) 209 * Ensure we fiddle with dual issue only on HS4x 210 */ 211 READ_BCR(ARC_REG_MICRO_ARCH_BCR, uarch); 212 213 if (uarch.prod == 4) { 214 unsigned int exec_ctrl; 215 216 /* dual issue hardware always present */ 217 cpu->extn.dual = 1; 218 219 READ_BCR(AUX_EXEC_CTRL, exec_ctrl); 220 221 /* dual issue hardware enabled ? */ 222 cpu->extn.dual_enb = !(exec_ctrl & 1); 223 224 } 225 } 226 } 227 228 READ_BCR(ARC_REG_AP_BCR, ap); 229 if (ap.ver) { 230 cpu->extn.ap_num = 2 << ap.num; 231 cpu->extn.ap_full = !ap.min; 232 } 233 234 READ_BCR(ARC_REG_SMART_BCR, bcr); 235 cpu->extn.smart = bcr.ver ? 1 : 0; 236 237 READ_BCR(ARC_REG_RTT_BCR, bcr); 238 cpu->extn.rtt = bcr.ver ? 1 : 0; 239 240 READ_BCR(ARC_REG_ISA_CFG_BCR, isa); 241 242 /* some hacks for lack of feature BCR info in old ARC700 cores */ 243 if (is_isa_arcompact()) { 244 if (!isa.ver) /* ISA BCR absent, use Kconfig info */ 245 cpu->isa.atomic = IS_ENABLED(CONFIG_ARC_HAS_LLSC); 246 else { 247 /* ARC700_BUILD only has 2 bits of isa info */ 248 struct bcr_generic bcr = *(struct bcr_generic *)&isa; 249 cpu->isa.atomic = bcr.info & 1; 250 } 251 252 cpu->isa.be = IS_ENABLED(CONFIG_CPU_BIG_ENDIAN); 253 254 /* there's no direct way to distinguish 750 vs. 770 */ 255 if (unlikely(cpu->core.family < 0x34 || cpu->mmu.ver < 3)) 256 cpu->name = "ARC750"; 257 } else { 258 cpu->isa = isa; 259 } 260 } 261 262 static char *arc_cpu_mumbojumbo(int cpu_id, char *buf, int len) 263 { 264 struct cpuinfo_arc *cpu = &cpuinfo_arc700[cpu_id]; 265 struct bcr_identity *core = &cpu->core; 266 int n = 0; 267 268 FIX_PTR(cpu); 269 270 n += scnprintf(buf + n, len - n, 271 "\nIDENTITY\t: ARCVER [%#02x] ARCNUM [%#02x] CHIPID [%#4x]\n", 272 core->family, core->cpu_id, core->chip_id); 273 274 n += scnprintf(buf + n, len - n, "processor [%d]\t: %s %s (%s ISA) %s%s%s\n", 275 cpu_id, cpu->name, cpu->details, 276 is_isa_arcompact() ? "ARCompact" : "ARCv2", 277 IS_AVAIL1(cpu->isa.be, "[Big-Endian]"), 278 IS_AVAIL3(cpu->extn.dual, cpu->extn.dual_enb, " Dual-Issue ")); 279 280 n += scnprintf(buf + n, len - n, "Timers\t\t: %s%s%s%s%s%s\nISA Extn\t: ", 281 IS_AVAIL1(cpu->extn.timer0, "Timer0 "), 282 IS_AVAIL1(cpu->extn.timer1, "Timer1 "), 283 IS_AVAIL2(cpu->extn.rtc, "RTC [UP 64-bit] ", CONFIG_ARC_TIMERS_64BIT), 284 IS_AVAIL2(cpu->extn.gfrc, "GFRC [SMP 64-bit] ", CONFIG_ARC_TIMERS_64BIT)); 285 286 n += scnprintf(buf + n, len - n, "%s%s%s%s%s%s", 287 IS_AVAIL2(cpu->isa.atomic, "atomic ", CONFIG_ARC_HAS_LLSC), 288 IS_AVAIL2(cpu->isa.ldd, "ll64 ", CONFIG_ARC_HAS_LL64), 289 IS_AVAIL2(cpu->isa.unalign, "unalign ", CONFIG_ARC_USE_UNALIGNED_MEM_ACCESS)); 290 291 #if defined(__ARC_UNALIGNED__) && !defined(CONFIG_ARC_USE_UNALIGNED_MEM_ACCESS) 292 /* 293 * gcc 7.3.1 (GNU 2018.03) onwards generate unaligned access by default 294 * but -mno-unaligned-access to disable that didn't work until gcc 8.2.1 295 * (GNU 2019.03). So landing here implies the interim period, when 296 * despite Kconfig being off, gcc is generating unaligned accesses which 297 * could bomb later on. So better to disallow such broken builds 298 */ 299 BUILD_BUG_ON_MSG(1, "gcc doesn't support -mno-unaligned-access"); 300 #endif 301 302 n += scnprintf(buf + n, len - n, "\n\t\t: "); 303 304 if (cpu->extn_mpy.ver) { 305 if (cpu->extn_mpy.ver <= 0x2) { /* ARCompact */ 306 n += scnprintf(buf + n, len - n, "mpy "); 307 } else { 308 int opt = 2; /* stock MPY/MPYH */ 309 310 if (cpu->extn_mpy.dsp) /* OPT 7-9 */ 311 opt = cpu->extn_mpy.dsp + 6; 312 313 n += scnprintf(buf + n, len - n, "mpy[opt %d] ", opt); 314 } 315 } 316 317 n += scnprintf(buf + n, len - n, "%s%s%s%s%s%s%s%s\n", 318 IS_AVAIL1(cpu->isa.div_rem, "div_rem "), 319 IS_AVAIL1(cpu->extn.norm, "norm "), 320 IS_AVAIL1(cpu->extn.barrel, "barrel-shift "), 321 IS_AVAIL1(cpu->extn.swap, "swap "), 322 IS_AVAIL1(cpu->extn.minmax, "minmax "), 323 IS_AVAIL1(cpu->extn.crc, "crc "), 324 IS_AVAIL2(cpu->extn.swape, "swape", CONFIG_ARC_HAS_SWAPE)); 325 326 if (cpu->bpu.ver) 327 n += scnprintf(buf + n, len - n, 328 "BPU\t\t: %s%s match, cache:%d, Predict Table:%d Return stk: %d", 329 IS_AVAIL1(cpu->bpu.full, "full"), 330 IS_AVAIL1(!cpu->bpu.full, "partial"), 331 cpu->bpu.num_cache, cpu->bpu.num_pred, cpu->bpu.ret_stk); 332 333 if (is_isa_arcv2()) { 334 struct bcr_lpb lpb; 335 336 READ_BCR(ARC_REG_LPB_BUILD, lpb); 337 if (lpb.ver) { 338 unsigned int ctl; 339 ctl = read_aux_reg(ARC_REG_LPB_CTRL); 340 341 n += scnprintf(buf + n, len - n, " Loop Buffer:%d %s", 342 lpb.entries, 343 IS_DISABLED_RUN(!ctl)); 344 } 345 } 346 347 n += scnprintf(buf + n, len - n, "\n"); 348 return buf; 349 } 350 351 static char *arc_extn_mumbojumbo(int cpu_id, char *buf, int len) 352 { 353 int n = 0; 354 struct cpuinfo_arc *cpu = &cpuinfo_arc700[cpu_id]; 355 356 FIX_PTR(cpu); 357 358 n += scnprintf(buf + n, len - n, "Vector Table\t: %#x\n", cpu->vec_base); 359 360 if (cpu->extn.fpu_sp || cpu->extn.fpu_dp) 361 n += scnprintf(buf + n, len - n, "FPU\t\t: %s%s\n", 362 IS_AVAIL1(cpu->extn.fpu_sp, "SP "), 363 IS_AVAIL1(cpu->extn.fpu_dp, "DP ")); 364 365 if (cpu->extn.ap_num | cpu->extn.smart | cpu->extn.rtt) { 366 n += scnprintf(buf + n, len - n, "DEBUG\t\t: %s%s", 367 IS_AVAIL1(cpu->extn.smart, "smaRT "), 368 IS_AVAIL1(cpu->extn.rtt, "RTT ")); 369 if (cpu->extn.ap_num) { 370 n += scnprintf(buf + n, len - n, "ActionPoint %d/%s", 371 cpu->extn.ap_num, 372 cpu->extn.ap_full ? "full":"min"); 373 } 374 n += scnprintf(buf + n, len - n, "\n"); 375 } 376 377 if (cpu->dccm.sz || cpu->iccm.sz) 378 n += scnprintf(buf + n, len - n, "Extn [CCM]\t: DCCM @ %x, %d KB / ICCM: @ %x, %d KB\n", 379 cpu->dccm.base_addr, TO_KB(cpu->dccm.sz), 380 cpu->iccm.base_addr, TO_KB(cpu->iccm.sz)); 381 382 if (is_isa_arcv2()) { 383 384 /* Error Protection: ECC/Parity */ 385 struct bcr_erp erp; 386 READ_BCR(ARC_REG_ERP_BUILD, erp); 387 388 if (erp.ver) { 389 struct ctl_erp ctl; 390 READ_BCR(ARC_REG_ERP_CTRL, ctl); 391 392 /* inverted bits: 0 means enabled */ 393 n += scnprintf(buf + n, len - n, "Extn [ECC]\t: %s%s%s%s%s%s\n", 394 IS_AVAIL3(erp.ic, !ctl.dpi, "IC "), 395 IS_AVAIL3(erp.dc, !ctl.dpd, "DC "), 396 IS_AVAIL3(erp.mmu, !ctl.mpd, "MMU ")); 397 } 398 } 399 400 n += scnprintf(buf + n, len - n, "OS ABI [v%d]\t: %s\n", 401 EF_ARC_OSABI_CURRENT >> 8, 402 EF_ARC_OSABI_CURRENT == EF_ARC_OSABI_V3 ? 403 "no-legacy-syscalls" : "64-bit data any register aligned"); 404 405 return buf; 406 } 407 408 static void arc_chk_core_config(void) 409 { 410 struct cpuinfo_arc *cpu = &cpuinfo_arc700[smp_processor_id()]; 411 int saved = 0, present = 0; 412 char *opt_nm = NULL; 413 414 if (!cpu->extn.timer0) 415 panic("Timer0 is not present!\n"); 416 417 if (!cpu->extn.timer1) 418 panic("Timer1 is not present!\n"); 419 420 #ifdef CONFIG_ARC_HAS_DCCM 421 /* 422 * DCCM can be arbit placed in hardware. 423 * Make sure it's placement/sz matches what Linux is built with 424 */ 425 if ((unsigned int)__arc_dccm_base != cpu->dccm.base_addr) 426 panic("Linux built with incorrect DCCM Base address\n"); 427 428 if (CONFIG_ARC_DCCM_SZ != cpu->dccm.sz) 429 panic("Linux built with incorrect DCCM Size\n"); 430 #endif 431 432 #ifdef CONFIG_ARC_HAS_ICCM 433 if (CONFIG_ARC_ICCM_SZ != cpu->iccm.sz) 434 panic("Linux built with incorrect ICCM Size\n"); 435 #endif 436 437 /* 438 * FP hardware/software config sanity 439 * -If hardware present, kernel needs to save/restore FPU state 440 * -If not, it will crash trying to save/restore the non-existant regs 441 */ 442 443 if (is_isa_arcompact()) { 444 opt_nm = "CONFIG_ARC_FPU_SAVE_RESTORE"; 445 saved = IS_ENABLED(CONFIG_ARC_FPU_SAVE_RESTORE); 446 447 /* only DPDP checked since SP has no arch visible regs */ 448 present = cpu->extn.fpu_dp; 449 } else { 450 opt_nm = "CONFIG_ARC_HAS_ACCL_REGS"; 451 saved = IS_ENABLED(CONFIG_ARC_HAS_ACCL_REGS); 452 453 /* Accumulator Low:High pair (r58:59) present if DSP MPY or FPU */ 454 present = cpu->extn_mpy.dsp | cpu->extn.fpu_sp | cpu->extn.fpu_dp; 455 } 456 457 if (present && !saved) 458 pr_warn("Enable %s for working apps\n", opt_nm); 459 else if (!present && saved) 460 panic("Disable %s, hardware NOT present\n", opt_nm); 461 } 462 463 /* 464 * Initialize and setup the processor core 465 * This is called by all the CPUs thus should not do special case stuff 466 * such as only for boot CPU etc 467 */ 468 469 void setup_processor(void) 470 { 471 char str[512]; 472 int cpu_id = smp_processor_id(); 473 474 read_arc_build_cfg_regs(); 475 arc_init_IRQ(); 476 477 pr_info("%s", arc_cpu_mumbojumbo(cpu_id, str, sizeof(str))); 478 479 arc_mmu_init(); 480 arc_cache_init(); 481 482 pr_info("%s", arc_extn_mumbojumbo(cpu_id, str, sizeof(str))); 483 pr_info("%s", arc_platform_smp_cpuinfo()); 484 485 arc_chk_core_config(); 486 } 487 488 static inline bool uboot_arg_invalid(unsigned long addr) 489 { 490 /* 491 * Check that it is a untranslated address (although MMU is not enabled 492 * yet, it being a high address ensures this is not by fluke) 493 */ 494 if (addr < PAGE_OFFSET) 495 return true; 496 497 /* Check that address doesn't clobber resident kernel image */ 498 return addr >= (unsigned long)_stext && addr <= (unsigned long)_end; 499 } 500 501 #define IGNORE_ARGS "Ignore U-boot args: " 502 503 /* uboot_tag values for U-boot - kernel ABI revision 0; see head.S */ 504 #define UBOOT_TAG_NONE 0 505 #define UBOOT_TAG_CMDLINE 1 506 #define UBOOT_TAG_DTB 2 507 508 void __init handle_uboot_args(void) 509 { 510 bool use_embedded_dtb = true; 511 bool append_cmdline = false; 512 513 /* check that we know this tag */ 514 if (uboot_tag != UBOOT_TAG_NONE && 515 uboot_tag != UBOOT_TAG_CMDLINE && 516 uboot_tag != UBOOT_TAG_DTB) { 517 pr_warn(IGNORE_ARGS "invalid uboot tag: '%08x'\n", uboot_tag); 518 goto ignore_uboot_args; 519 } 520 521 if (uboot_tag != UBOOT_TAG_NONE && 522 uboot_arg_invalid((unsigned long)uboot_arg)) { 523 pr_warn(IGNORE_ARGS "invalid uboot arg: '%px'\n", uboot_arg); 524 goto ignore_uboot_args; 525 } 526 527 /* see if U-boot passed an external Device Tree blob */ 528 if (uboot_tag == UBOOT_TAG_DTB) { 529 machine_desc = setup_machine_fdt((void *)uboot_arg); 530 531 /* external Device Tree blob is invalid - use embedded one */ 532 use_embedded_dtb = !machine_desc; 533 } 534 535 if (uboot_tag == UBOOT_TAG_CMDLINE) 536 append_cmdline = true; 537 538 ignore_uboot_args: 539 540 if (use_embedded_dtb) { 541 machine_desc = setup_machine_fdt(__dtb_start); 542 if (!machine_desc) 543 panic("Embedded DT invalid\n"); 544 } 545 546 /* 547 * NOTE: @boot_command_line is populated by setup_machine_fdt() so this 548 * append processing can only happen after. 549 */ 550 if (append_cmdline) { 551 /* Ensure a whitespace between the 2 cmdlines */ 552 strlcat(boot_command_line, " ", COMMAND_LINE_SIZE); 553 strlcat(boot_command_line, uboot_arg, COMMAND_LINE_SIZE); 554 } 555 } 556 557 void __init setup_arch(char **cmdline_p) 558 { 559 handle_uboot_args(); 560 561 /* Save unparsed command line copy for /proc/cmdline */ 562 *cmdline_p = boot_command_line; 563 564 /* To force early parsing of things like mem=xxx */ 565 parse_early_param(); 566 567 /* Platform/board specific: e.g. early console registration */ 568 if (machine_desc->init_early) 569 machine_desc->init_early(); 570 571 smp_init_cpus(); 572 573 setup_processor(); 574 setup_arch_memory(); 575 576 /* copy flat DT out of .init and then unflatten it */ 577 unflatten_and_copy_device_tree(); 578 579 /* Can be issue if someone passes cmd line arg "ro" 580 * But that is unlikely so keeping it as it is 581 */ 582 root_mountflags &= ~MS_RDONLY; 583 584 #if defined(CONFIG_VT) && defined(CONFIG_DUMMY_CONSOLE) 585 conswitchp = &dummy_con; 586 #endif 587 588 arc_unwind_init(); 589 } 590 591 /* 592 * Called from start_kernel() - boot CPU only 593 */ 594 void __init time_init(void) 595 { 596 of_clk_init(NULL); 597 timer_probe(); 598 } 599 600 static int __init customize_machine(void) 601 { 602 if (machine_desc->init_machine) 603 machine_desc->init_machine(); 604 605 return 0; 606 } 607 arch_initcall(customize_machine); 608 609 static int __init init_late_machine(void) 610 { 611 if (machine_desc->init_late) 612 machine_desc->init_late(); 613 614 return 0; 615 } 616 late_initcall(init_late_machine); 617 /* 618 * Get CPU information for use by the procfs. 619 */ 620 621 #define cpu_to_ptr(c) ((void *)(0xFFFF0000 | (unsigned int)(c))) 622 #define ptr_to_cpu(p) (~0xFFFF0000UL & (unsigned int)(p)) 623 624 static int show_cpuinfo(struct seq_file *m, void *v) 625 { 626 char *str; 627 int cpu_id = ptr_to_cpu(v); 628 struct device *cpu_dev = get_cpu_device(cpu_id); 629 struct clk *cpu_clk; 630 unsigned long freq = 0; 631 632 if (!cpu_online(cpu_id)) { 633 seq_printf(m, "processor [%d]\t: Offline\n", cpu_id); 634 goto done; 635 } 636 637 str = (char *)__get_free_page(GFP_KERNEL); 638 if (!str) 639 goto done; 640 641 seq_printf(m, arc_cpu_mumbojumbo(cpu_id, str, PAGE_SIZE)); 642 643 cpu_clk = clk_get(cpu_dev, NULL); 644 if (IS_ERR(cpu_clk)) { 645 seq_printf(m, "CPU speed \t: Cannot get clock for processor [%d]\n", 646 cpu_id); 647 } else { 648 freq = clk_get_rate(cpu_clk); 649 } 650 if (freq) 651 seq_printf(m, "CPU speed\t: %lu.%02lu Mhz\n", 652 freq / 1000000, (freq / 10000) % 100); 653 654 seq_printf(m, "Bogo MIPS\t: %lu.%02lu\n", 655 loops_per_jiffy / (500000 / HZ), 656 (loops_per_jiffy / (5000 / HZ)) % 100); 657 658 seq_printf(m, arc_mmu_mumbojumbo(cpu_id, str, PAGE_SIZE)); 659 seq_printf(m, arc_cache_mumbojumbo(cpu_id, str, PAGE_SIZE)); 660 seq_printf(m, arc_extn_mumbojumbo(cpu_id, str, PAGE_SIZE)); 661 seq_printf(m, arc_platform_smp_cpuinfo()); 662 663 free_page((unsigned long)str); 664 done: 665 seq_printf(m, "\n"); 666 667 return 0; 668 } 669 670 static void *c_start(struct seq_file *m, loff_t *pos) 671 { 672 /* 673 * Callback returns cpu-id to iterator for show routine, NULL to stop. 674 * However since NULL is also a valid cpu-id (0), we use a round-about 675 * way to pass it w/o having to kmalloc/free a 2 byte string. 676 * Encode cpu-id as 0xFFcccc, which is decoded by show routine. 677 */ 678 return *pos < nr_cpu_ids ? cpu_to_ptr(*pos) : NULL; 679 } 680 681 static void *c_next(struct seq_file *m, void *v, loff_t *pos) 682 { 683 ++*pos; 684 return c_start(m, pos); 685 } 686 687 static void c_stop(struct seq_file *m, void *v) 688 { 689 } 690 691 const struct seq_operations cpuinfo_op = { 692 .start = c_start, 693 .next = c_next, 694 .stop = c_stop, 695 .show = show_cpuinfo 696 }; 697 698 static DEFINE_PER_CPU(struct cpu, cpu_topology); 699 700 static int __init topology_init(void) 701 { 702 int cpu; 703 704 for_each_present_cpu(cpu) 705 register_cpu(&per_cpu(cpu_topology, cpu), cpu); 706 707 return 0; 708 } 709 710 subsys_initcall(topology_init); 711