1 /* 2 * ARC ARConnect (MultiCore IP) support (formerly known as MCIP) 3 * 4 * Copyright (C) 2013 Synopsys, Inc. (www.synopsys.com) 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11 #include <linux/smp.h> 12 #include <linux/irq.h> 13 #include <linux/spinlock.h> 14 #include <asm/mcip.h> 15 16 static char smp_cpuinfo_buf[128]; 17 static int idu_detected; 18 19 static DEFINE_RAW_SPINLOCK(mcip_lock); 20 21 /* 22 * Any SMP specific init any CPU does when it comes up. 23 * Here we setup the CPU to enable Inter-Processor-Interrupts 24 * Called for each CPU 25 * -Master : init_IRQ() 26 * -Other(s) : start_kernel_secondary() 27 */ 28 void mcip_init_smp(unsigned int cpu) 29 { 30 smp_ipi_irq_setup(cpu, IPI_IRQ); 31 } 32 33 static void mcip_ipi_send(int cpu) 34 { 35 unsigned long flags; 36 int ipi_was_pending; 37 38 /* 39 * NOTE: We must spin here if the other cpu hasn't yet 40 * serviced a previous message. This can burn lots 41 * of time, but we MUST follows this protocol or 42 * ipi messages can be lost!!! 43 * Also, we must release the lock in this loop because 44 * the other side may get to this same loop and not 45 * be able to ack -- thus causing deadlock. 46 */ 47 48 do { 49 raw_spin_lock_irqsave(&mcip_lock, flags); 50 __mcip_cmd(CMD_INTRPT_READ_STATUS, cpu); 51 ipi_was_pending = read_aux_reg(ARC_REG_MCIP_READBACK); 52 if (ipi_was_pending == 0) 53 break; /* break out but keep lock */ 54 raw_spin_unlock_irqrestore(&mcip_lock, flags); 55 } while (1); 56 57 __mcip_cmd(CMD_INTRPT_GENERATE_IRQ, cpu); 58 raw_spin_unlock_irqrestore(&mcip_lock, flags); 59 60 #ifdef CONFIG_ARC_IPI_DBG 61 if (ipi_was_pending) 62 pr_info("IPI ACK delayed from cpu %d\n", cpu); 63 #endif 64 } 65 66 static void mcip_ipi_clear(int irq) 67 { 68 unsigned int cpu, c; 69 unsigned long flags; 70 unsigned int __maybe_unused copy; 71 72 raw_spin_lock_irqsave(&mcip_lock, flags); 73 74 /* Who sent the IPI */ 75 __mcip_cmd(CMD_INTRPT_CHECK_SOURCE, 0); 76 77 copy = cpu = read_aux_reg(ARC_REG_MCIP_READBACK); /* 1,2,4,8... */ 78 79 /* 80 * In rare case, multiple concurrent IPIs sent to same target can 81 * possibly be coalesced by MCIP into 1 asserted IRQ, so @cpus can be 82 * "vectored" (multiple bits sets) as opposed to typical single bit 83 */ 84 do { 85 c = __ffs(cpu); /* 0,1,2,3 */ 86 __mcip_cmd(CMD_INTRPT_GENERATE_ACK, c); 87 cpu &= ~(1U << c); 88 } while (cpu); 89 90 raw_spin_unlock_irqrestore(&mcip_lock, flags); 91 92 #ifdef CONFIG_ARC_IPI_DBG 93 if (c != __ffs(copy)) 94 pr_info("IPIs from %x coalesced to %x\n", 95 copy, raw_smp_processor_id()); 96 #endif 97 } 98 99 volatile int wake_flag; 100 101 static void mcip_wakeup_cpu(int cpu, unsigned long pc) 102 { 103 BUG_ON(cpu == 0); 104 wake_flag = cpu; 105 } 106 107 void arc_platform_smp_wait_to_boot(int cpu) 108 { 109 while (wake_flag != cpu) 110 ; 111 112 wake_flag = 0; 113 __asm__ __volatile__("j @first_lines_of_secondary \n"); 114 } 115 116 struct plat_smp_ops plat_smp_ops = { 117 .info = smp_cpuinfo_buf, 118 .cpu_kick = mcip_wakeup_cpu, 119 .ipi_send = mcip_ipi_send, 120 .ipi_clear = mcip_ipi_clear, 121 }; 122 123 void mcip_init_early_smp(void) 124 { 125 #define IS_AVAIL1(var, str) ((var) ? str : "") 126 127 struct mcip_bcr { 128 #ifdef CONFIG_CPU_BIG_ENDIAN 129 unsigned int pad3:8, 130 idu:1, llm:1, num_cores:6, 131 iocoh:1, grtc:1, dbg:1, pad2:1, 132 msg:1, sem:1, ipi:1, pad:1, 133 ver:8; 134 #else 135 unsigned int ver:8, 136 pad:1, ipi:1, sem:1, msg:1, 137 pad2:1, dbg:1, grtc:1, iocoh:1, 138 num_cores:6, llm:1, idu:1, 139 pad3:8; 140 #endif 141 } mp; 142 143 READ_BCR(ARC_REG_MCIP_BCR, mp); 144 145 sprintf(smp_cpuinfo_buf, 146 "Extn [SMP]\t: ARConnect (v%d): %d cores with %s%s%s%s\n", 147 mp.ver, mp.num_cores, 148 IS_AVAIL1(mp.ipi, "IPI "), 149 IS_AVAIL1(mp.idu, "IDU "), 150 IS_AVAIL1(mp.dbg, "DEBUG "), 151 IS_AVAIL1(mp.grtc, "GRTC")); 152 153 idu_detected = mp.idu; 154 155 if (mp.dbg) { 156 __mcip_cmd_data(CMD_DEBUG_SET_SELECT, 0, 0xf); 157 __mcip_cmd_data(CMD_DEBUG_SET_MASK, 0xf, 0xf); 158 } 159 160 if (IS_ENABLED(CONFIG_ARC_HAS_GRTC) && !mp.grtc) 161 panic("kernel trying to use non-existent GRTC\n"); 162 } 163 164 /*************************************************************************** 165 * ARCv2 Interrupt Distribution Unit (IDU) 166 * 167 * Connects external "COMMON" IRQs to core intc, providing: 168 * -dynamic routing (IRQ affinity) 169 * -load balancing (Round Robin interrupt distribution) 170 * -1:N distribution 171 * 172 * It physically resides in the MCIP hw block 173 */ 174 175 #include <linux/irqchip.h> 176 #include <linux/of.h> 177 #include <linux/of_irq.h> 178 #include "../../drivers/irqchip/irqchip.h" 179 180 /* 181 * Set the DEST for @cmn_irq to @cpu_mask (1 bit per core) 182 */ 183 static void idu_set_dest(unsigned int cmn_irq, unsigned int cpu_mask) 184 { 185 __mcip_cmd_data(CMD_IDU_SET_DEST, cmn_irq, cpu_mask); 186 } 187 188 static void idu_set_mode(unsigned int cmn_irq, unsigned int lvl, 189 unsigned int distr) 190 { 191 union { 192 unsigned int word; 193 struct { 194 unsigned int distr:2, pad:2, lvl:1, pad2:27; 195 }; 196 } data; 197 198 data.distr = distr; 199 data.lvl = lvl; 200 __mcip_cmd_data(CMD_IDU_SET_MODE, cmn_irq, data.word); 201 } 202 203 static void idu_irq_mask(struct irq_data *data) 204 { 205 unsigned long flags; 206 207 raw_spin_lock_irqsave(&mcip_lock, flags); 208 __mcip_cmd_data(CMD_IDU_SET_MASK, data->hwirq, 1); 209 raw_spin_unlock_irqrestore(&mcip_lock, flags); 210 } 211 212 static void idu_irq_unmask(struct irq_data *data) 213 { 214 unsigned long flags; 215 216 raw_spin_lock_irqsave(&mcip_lock, flags); 217 __mcip_cmd_data(CMD_IDU_SET_MASK, data->hwirq, 0); 218 raw_spin_unlock_irqrestore(&mcip_lock, flags); 219 } 220 221 static int 222 idu_irq_set_affinity(struct irq_data *d, const struct cpumask *cpumask, bool f) 223 { 224 return IRQ_SET_MASK_OK; 225 } 226 227 static struct irq_chip idu_irq_chip = { 228 .name = "MCIP IDU Intc", 229 .irq_mask = idu_irq_mask, 230 .irq_unmask = idu_irq_unmask, 231 #ifdef CONFIG_SMP 232 .irq_set_affinity = idu_irq_set_affinity, 233 #endif 234 235 }; 236 237 static int idu_first_irq; 238 239 static void idu_cascade_isr(unsigned int core_irq, struct irq_desc *desc) 240 { 241 struct irq_domain *domain = irq_desc_get_handler_data(desc); 242 unsigned int idu_irq; 243 244 idu_irq = core_irq - idu_first_irq; 245 generic_handle_irq(irq_find_mapping(domain, idu_irq)); 246 } 247 248 static int idu_irq_map(struct irq_domain *d, unsigned int virq, irq_hw_number_t hwirq) 249 { 250 irq_set_chip_and_handler(virq, &idu_irq_chip, handle_level_irq); 251 irq_set_status_flags(virq, IRQ_MOVE_PCNTXT); 252 253 return 0; 254 } 255 256 static int idu_irq_xlate(struct irq_domain *d, struct device_node *n, 257 const u32 *intspec, unsigned int intsize, 258 irq_hw_number_t *out_hwirq, unsigned int *out_type) 259 { 260 irq_hw_number_t hwirq = *out_hwirq = intspec[0]; 261 int distri = intspec[1]; 262 unsigned long flags; 263 264 *out_type = IRQ_TYPE_NONE; 265 266 /* XXX: validate distribution scheme again online cpu mask */ 267 if (distri == 0) { 268 /* 0 - Round Robin to all cpus, otherwise 1 bit per core */ 269 raw_spin_lock_irqsave(&mcip_lock, flags); 270 idu_set_dest(hwirq, BIT(num_online_cpus()) - 1); 271 idu_set_mode(hwirq, IDU_M_TRIG_LEVEL, IDU_M_DISTRI_RR); 272 raw_spin_unlock_irqrestore(&mcip_lock, flags); 273 } else { 274 /* 275 * DEST based distribution for Level Triggered intr can only 276 * have 1 CPU, so generalize it to always contain 1 cpu 277 */ 278 int cpu = ffs(distri); 279 280 if (cpu != fls(distri)) 281 pr_warn("IDU irq %lx distri mode set to cpu %x\n", 282 hwirq, cpu); 283 284 raw_spin_lock_irqsave(&mcip_lock, flags); 285 idu_set_dest(hwirq, cpu); 286 idu_set_mode(hwirq, IDU_M_TRIG_LEVEL, IDU_M_DISTRI_DEST); 287 raw_spin_unlock_irqrestore(&mcip_lock, flags); 288 } 289 290 return 0; 291 } 292 293 static const struct irq_domain_ops idu_irq_ops = { 294 .xlate = idu_irq_xlate, 295 .map = idu_irq_map, 296 }; 297 298 /* 299 * [16, 23]: Statically assigned always private-per-core (Timers, WDT, IPI) 300 * [24, 23+C]: If C > 0 then "C" common IRQs 301 * [24+C, N]: Not statically assigned, private-per-core 302 */ 303 304 305 static int __init 306 idu_of_init(struct device_node *intc, struct device_node *parent) 307 { 308 struct irq_domain *domain; 309 /* Read IDU BCR to confirm nr_irqs */ 310 int nr_irqs = of_irq_count(intc); 311 int i, irq; 312 313 if (!idu_detected) 314 panic("IDU not detected, but DeviceTree using it"); 315 316 pr_info("MCIP: IDU referenced from Devicetree %d irqs\n", nr_irqs); 317 318 domain = irq_domain_add_linear(intc, nr_irqs, &idu_irq_ops, NULL); 319 320 /* Parent interrupts (core-intc) are already mapped */ 321 322 for (i = 0; i < nr_irqs; i++) { 323 /* 324 * Return parent uplink IRQs (towards core intc) 24,25,..... 325 * this step has been done before already 326 * however we need it to get the parent virq and set IDU handler 327 * as first level isr 328 */ 329 irq = irq_of_parse_and_map(intc, i); 330 if (!i) 331 idu_first_irq = irq; 332 333 irq_set_handler_data(irq, domain); 334 irq_set_chained_handler(irq, idu_cascade_isr); 335 } 336 337 __mcip_cmd(CMD_IDU_ENABLE, 0); 338 339 return 0; 340 } 341 IRQCHIP_DECLARE(arcv2_idu_intc, "snps,archs-idu-intc", idu_of_init); 342