1 /* 2 * Copyright (C) 2011-12 Synopsys, Inc. (www.synopsys.com) 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 * 8 */ 9 10 #include <linux/interrupt.h> 11 #include <linux/module.h> 12 #include <linux/of.h> 13 #include <linux/irqdomain.h> 14 #include <asm/sections.h> 15 #include <asm/irq.h> 16 17 /* 18 * Early Hardware specific Interrupt setup 19 * -Called very early (start_kernel -> setup_arch -> setup_processor) 20 * -Platform Independent (must for any ARC700) 21 * -Needed for each CPU (hence not foldable into init_IRQ) 22 * 23 * what it does ? 24 * -setup Vector Table Base Reg - in case Linux not linked at 0x8000_0000 25 * -Disable all IRQs (on CPU side) 26 * -Optionally, setup the High priority Interrupts as Level 2 IRQs 27 */ 28 void __init arc_init_IRQ(void) 29 { 30 int level_mask = 0; 31 32 write_aux_reg(AUX_INTR_VEC_BASE, _int_vec_base_lds); 33 34 /* Disable all IRQs: enable them as devices request */ 35 write_aux_reg(AUX_IENABLE, 0); 36 37 /* setup any high priority Interrupts (Level2 in ARCompact jargon) */ 38 #ifdef CONFIG_ARC_IRQ3_LV2 39 level_mask |= (1 << 3); 40 #endif 41 #ifdef CONFIG_ARC_IRQ5_LV2 42 level_mask |= (1 << 5); 43 #endif 44 #ifdef CONFIG_ARC_IRQ6_LV2 45 level_mask |= (1 << 6); 46 #endif 47 48 if (level_mask) { 49 pr_info("Level-2 interrupts bitset %x\n", level_mask); 50 write_aux_reg(AUX_IRQ_LEV, level_mask); 51 } 52 } 53 54 /* 55 * ARC700 core includes a simple on-chip intc supporting 56 * -per IRQ enable/disable 57 * -2 levels of interrupts (high/low) 58 * -all interrupts being level triggered 59 * 60 * To reduce platform code, we assume all IRQs directly hooked-up into intc. 61 * Platforms with external intc, hence cascaded IRQs, are free to over-ride 62 * below, per IRQ. 63 */ 64 65 static void arc_mask_irq(struct irq_data *data) 66 { 67 arch_mask_irq(data->irq); 68 } 69 70 static void arc_unmask_irq(struct irq_data *data) 71 { 72 arch_unmask_irq(data->irq); 73 } 74 75 static struct irq_chip onchip_intc = { 76 .name = "ARC In-core Intc", 77 .irq_mask = arc_mask_irq, 78 .irq_unmask = arc_unmask_irq, 79 }; 80 81 static int arc_intc_domain_map(struct irq_domain *d, unsigned int irq, 82 irq_hw_number_t hw) 83 { 84 if (irq == TIMER0_IRQ) 85 irq_set_chip_and_handler(irq, &onchip_intc, handle_percpu_irq); 86 else 87 irq_set_chip_and_handler(irq, &onchip_intc, handle_level_irq); 88 89 return 0; 90 } 91 92 static const struct irq_domain_ops arc_intc_domain_ops = { 93 .xlate = irq_domain_xlate_onecell, 94 .map = arc_intc_domain_map, 95 }; 96 97 static struct irq_domain *root_domain; 98 99 void __init init_onchip_IRQ(void) 100 { 101 struct device_node *intc = NULL; 102 103 intc = of_find_compatible_node(NULL, NULL, "snps,arc700-intc"); 104 if(!intc) 105 panic("DeviceTree Missing incore intc\n"); 106 107 root_domain = irq_domain_add_legacy(intc, NR_IRQS, 0, 0, 108 &arc_intc_domain_ops, NULL); 109 110 if (!root_domain) 111 panic("root irq domain not avail\n"); 112 113 /* with this we don't need to export root_domain */ 114 irq_set_default_host(root_domain); 115 } 116 117 /* 118 * Late Interrupt system init called from start_kernel for Boot CPU only 119 * 120 * Since slab must already be initialized, platforms can start doing any 121 * needed request_irq( )s 122 */ 123 void __init init_IRQ(void) 124 { 125 init_onchip_IRQ(); 126 plat_init_IRQ(); 127 } 128 129 /* 130 * "C" Entry point for any ARC ISR, called from low level vector handler 131 * @irq is the vector number read from ICAUSE reg of on-chip intc 132 */ 133 void arch_do_IRQ(unsigned int irq, struct pt_regs *regs) 134 { 135 struct pt_regs *old_regs = set_irq_regs(regs); 136 137 irq_enter(); 138 generic_handle_irq(irq); 139 irq_exit(); 140 set_irq_regs(old_regs); 141 } 142 143 int __init get_hw_config_num_irq(void) 144 { 145 uint32_t val = read_aux_reg(ARC_REG_VECBASE_BCR); 146 147 switch (val & 0x03) { 148 case 0: 149 return 16; 150 case 1: 151 return 32; 152 case 2: 153 return 8; 154 default: 155 return 0; 156 } 157 158 return 0; 159 } 160 161 /* 162 * arch_local_irq_enable - Enable interrupts. 163 * 164 * 1. Explicitly called to re-enable interrupts 165 * 2. Implicitly called from spin_unlock_irq, write_unlock_irq etc 166 * which maybe in hard ISR itself 167 * 168 * Semantics of this function change depending on where it is called from: 169 * 170 * -If called from hard-ISR, it must not invert interrupt priorities 171 * e.g. suppose TIMER is high priority (Level 2) IRQ 172 * Time hard-ISR, timer_interrupt( ) calls spin_unlock_irq several times. 173 * Here local_irq_enable( ) shd not re-enable lower priority interrupts 174 * -If called from soft-ISR, it must re-enable all interrupts 175 * soft ISR are low prioity jobs which can be very slow, thus all IRQs 176 * must be enabled while they run. 177 * Now hardware context wise we may still be in L2 ISR (not done rtie) 178 * still we must re-enable both L1 and L2 IRQs 179 * Another twist is prev scenario with flow being 180 * L1 ISR ==> interrupted by L2 ISR ==> L2 soft ISR 181 * here we must not re-enable Ll as prev Ll Interrupt's h/w context will get 182 * over-written (this is deficiency in ARC700 Interrupt mechanism) 183 */ 184 185 #ifdef CONFIG_ARC_COMPACT_IRQ_LEVELS /* Complex version for 2 IRQ levels */ 186 187 void arch_local_irq_enable(void) 188 { 189 190 unsigned long flags; 191 flags = arch_local_save_flags(); 192 193 /* Allow both L1 and L2 at the onset */ 194 flags |= (STATUS_E1_MASK | STATUS_E2_MASK); 195 196 /* Called from hard ISR (between irq_enter and irq_exit) */ 197 if (in_irq()) { 198 199 /* If in L2 ISR, don't re-enable any further IRQs as this can 200 * cause IRQ priorities to get upside down. e.g. it could allow 201 * L1 be taken while in L2 hard ISR which is wrong not only in 202 * theory, it can also cause the dreaded L1-L2-L1 scenario 203 */ 204 if (flags & STATUS_A2_MASK) 205 flags &= ~(STATUS_E1_MASK | STATUS_E2_MASK); 206 207 /* Even if in L1 ISR, allowe Higher prio L2 IRQs */ 208 else if (flags & STATUS_A1_MASK) 209 flags &= ~(STATUS_E1_MASK); 210 } 211 212 /* called from soft IRQ, ideally we want to re-enable all levels */ 213 214 else if (in_softirq()) { 215 216 /* However if this is case of L1 interrupted by L2, 217 * re-enabling both may cause whaco L1-L2-L1 scenario 218 * because ARC700 allows level 1 to interrupt an active L2 ISR 219 * Thus we disable both 220 * However some code, executing in soft ISR wants some IRQs 221 * to be enabled so we re-enable L2 only 222 * 223 * How do we determine L1 intr by L2 224 * -A2 is set (means in L2 ISR) 225 * -E1 is set in this ISR's pt_regs->status32 which is 226 * saved copy of status32_l2 when l2 ISR happened 227 */ 228 struct pt_regs *pt = get_irq_regs(); 229 if ((flags & STATUS_A2_MASK) && pt && 230 (pt->status32 & STATUS_A1_MASK)) { 231 /*flags &= ~(STATUS_E1_MASK | STATUS_E2_MASK); */ 232 flags &= ~(STATUS_E1_MASK); 233 } 234 } 235 236 arch_local_irq_restore(flags); 237 } 238 239 #else /* ! CONFIG_ARC_COMPACT_IRQ_LEVELS */ 240 241 /* 242 * Simpler version for only 1 level of interrupt 243 * Here we only Worry about Level 1 Bits 244 */ 245 void arch_local_irq_enable(void) 246 { 247 unsigned long flags; 248 249 /* 250 * ARC IDE Drivers tries to re-enable interrupts from hard-isr 251 * context which is simply wrong 252 */ 253 if (in_irq()) { 254 WARN_ONCE(1, "IRQ enabled from hard-isr"); 255 return; 256 } 257 258 flags = arch_local_save_flags(); 259 flags |= (STATUS_E1_MASK | STATUS_E2_MASK); 260 arch_local_irq_restore(flags); 261 } 262 #endif 263 EXPORT_SYMBOL(arch_local_irq_enable); 264