1 /* 2 * Copyright (C) 2011-12 Synopsys, Inc. (www.synopsys.com) 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 * 8 */ 9 10 #include <linux/interrupt.h> 11 #include <linux/module.h> 12 #include <linux/of.h> 13 #include <linux/irqdomain.h> 14 #include <linux/irqchip.h> 15 #include "../../drivers/irqchip/irqchip.h" 16 #include <asm/irq.h> 17 18 /* 19 * Early Hardware specific Interrupt setup 20 * -Platform independent, needed for each CPU (not foldable into init_IRQ) 21 * -Called very early (start_kernel -> setup_arch -> setup_processor) 22 * 23 * what it does ? 24 * -Optionally, setup the High priority Interrupts as Level 2 IRQs 25 */ 26 void arc_init_IRQ(void) 27 { 28 int level_mask = 0; 29 30 /* setup any high priority Interrupts (Level2 in ARCompact jargon) */ 31 level_mask |= IS_ENABLED(CONFIG_ARC_IRQ3_LV2) << 3; 32 level_mask |= IS_ENABLED(CONFIG_ARC_IRQ5_LV2) << 5; 33 level_mask |= IS_ENABLED(CONFIG_ARC_IRQ6_LV2) << 6; 34 35 /* 36 * Write to register, even if no LV2 IRQs configured to reset it 37 * in case bootloader had mucked with it 38 */ 39 write_aux_reg(AUX_IRQ_LEV, level_mask); 40 41 if (level_mask) 42 pr_info("Level-2 interrupts bitset %x\n", level_mask); 43 } 44 45 /* 46 * ARC700 core includes a simple on-chip intc supporting 47 * -per IRQ enable/disable 48 * -2 levels of interrupts (high/low) 49 * -all interrupts being level triggered 50 * 51 * To reduce platform code, we assume all IRQs directly hooked-up into intc. 52 * Platforms with external intc, hence cascaded IRQs, are free to over-ride 53 * below, per IRQ. 54 */ 55 56 static void arc_irq_mask(struct irq_data *data) 57 { 58 unsigned int ienb; 59 60 ienb = read_aux_reg(AUX_IENABLE); 61 ienb &= ~(1 << data->irq); 62 write_aux_reg(AUX_IENABLE, ienb); 63 } 64 65 static void arc_irq_unmask(struct irq_data *data) 66 { 67 unsigned int ienb; 68 69 ienb = read_aux_reg(AUX_IENABLE); 70 ienb |= (1 << data->irq); 71 write_aux_reg(AUX_IENABLE, ienb); 72 } 73 74 static struct irq_chip onchip_intc = { 75 .name = "ARC In-core Intc", 76 .irq_mask = arc_irq_mask, 77 .irq_unmask = arc_irq_unmask, 78 }; 79 80 static int arc_intc_domain_map(struct irq_domain *d, unsigned int irq, 81 irq_hw_number_t hw) 82 { 83 /* 84 * XXX: the IPI IRQ needs to be handled like TIMER too. However ARC core 85 * code doesn't own it (like TIMER0). ISS IDU / ezchip define it 86 * in platform header which can't be included here as it goes 87 * against multi-platform image philisophy 88 */ 89 if (irq == TIMER0_IRQ) 90 irq_set_chip_and_handler(irq, &onchip_intc, handle_percpu_irq); 91 else 92 irq_set_chip_and_handler(irq, &onchip_intc, handle_level_irq); 93 94 return 0; 95 } 96 97 static const struct irq_domain_ops arc_intc_domain_ops = { 98 .xlate = irq_domain_xlate_onecell, 99 .map = arc_intc_domain_map, 100 }; 101 102 static struct irq_domain *root_domain; 103 104 static int __init 105 init_onchip_IRQ(struct device_node *intc, struct device_node *parent) 106 { 107 if (parent) 108 panic("DeviceTree incore intc not a root irq controller\n"); 109 110 root_domain = irq_domain_add_legacy(intc, NR_CPU_IRQS, 0, 0, 111 &arc_intc_domain_ops, NULL); 112 113 if (!root_domain) 114 panic("root irq domain not avail\n"); 115 116 /* with this we don't need to export root_domain */ 117 irq_set_default_host(root_domain); 118 119 return 0; 120 } 121 122 IRQCHIP_DECLARE(arc_intc, "snps,arc700-intc", init_onchip_IRQ); 123 124 /* 125 * arch_local_irq_enable - Enable interrupts. 126 * 127 * 1. Explicitly called to re-enable interrupts 128 * 2. Implicitly called from spin_unlock_irq, write_unlock_irq etc 129 * which maybe in hard ISR itself 130 * 131 * Semantics of this function change depending on where it is called from: 132 * 133 * -If called from hard-ISR, it must not invert interrupt priorities 134 * e.g. suppose TIMER is high priority (Level 2) IRQ 135 * Time hard-ISR, timer_interrupt( ) calls spin_unlock_irq several times. 136 * Here local_irq_enable( ) shd not re-enable lower priority interrupts 137 * -If called from soft-ISR, it must re-enable all interrupts 138 * soft ISR are low prioity jobs which can be very slow, thus all IRQs 139 * must be enabled while they run. 140 * Now hardware context wise we may still be in L2 ISR (not done rtie) 141 * still we must re-enable both L1 and L2 IRQs 142 * Another twist is prev scenario with flow being 143 * L1 ISR ==> interrupted by L2 ISR ==> L2 soft ISR 144 * here we must not re-enable Ll as prev Ll Interrupt's h/w context will get 145 * over-written (this is deficiency in ARC700 Interrupt mechanism) 146 */ 147 148 #ifdef CONFIG_ARC_COMPACT_IRQ_LEVELS /* Complex version for 2 IRQ levels */ 149 150 void arch_local_irq_enable(void) 151 { 152 153 unsigned long flags = arch_local_save_flags(); 154 155 /* Allow both L1 and L2 at the onset */ 156 flags |= (STATUS_E1_MASK | STATUS_E2_MASK); 157 158 /* Called from hard ISR (between irq_enter and irq_exit) */ 159 if (in_irq()) { 160 161 /* If in L2 ISR, don't re-enable any further IRQs as this can 162 * cause IRQ priorities to get upside down. e.g. it could allow 163 * L1 be taken while in L2 hard ISR which is wrong not only in 164 * theory, it can also cause the dreaded L1-L2-L1 scenario 165 */ 166 if (flags & STATUS_A2_MASK) 167 flags &= ~(STATUS_E1_MASK | STATUS_E2_MASK); 168 169 /* Even if in L1 ISR, allowe Higher prio L2 IRQs */ 170 else if (flags & STATUS_A1_MASK) 171 flags &= ~(STATUS_E1_MASK); 172 } 173 174 /* called from soft IRQ, ideally we want to re-enable all levels */ 175 176 else if (in_softirq()) { 177 178 /* However if this is case of L1 interrupted by L2, 179 * re-enabling both may cause whaco L1-L2-L1 scenario 180 * because ARC700 allows level 1 to interrupt an active L2 ISR 181 * Thus we disable both 182 * However some code, executing in soft ISR wants some IRQs 183 * to be enabled so we re-enable L2 only 184 * 185 * How do we determine L1 intr by L2 186 * -A2 is set (means in L2 ISR) 187 * -E1 is set in this ISR's pt_regs->status32 which is 188 * saved copy of status32_l2 when l2 ISR happened 189 */ 190 struct pt_regs *pt = get_irq_regs(); 191 192 if ((flags & STATUS_A2_MASK) && pt && 193 (pt->status32 & STATUS_A1_MASK)) { 194 /*flags &= ~(STATUS_E1_MASK | STATUS_E2_MASK); */ 195 flags &= ~(STATUS_E1_MASK); 196 } 197 } 198 199 arch_local_irq_restore(flags); 200 } 201 202 #else /* ! CONFIG_ARC_COMPACT_IRQ_LEVELS */ 203 204 /* 205 * Simpler version for only 1 level of interrupt 206 * Here we only Worry about Level 1 Bits 207 */ 208 void arch_local_irq_enable(void) 209 { 210 unsigned long flags; 211 212 /* 213 * ARC IDE Drivers tries to re-enable interrupts from hard-isr 214 * context which is simply wrong 215 */ 216 if (in_irq()) { 217 WARN_ONCE(1, "IRQ enabled from hard-isr"); 218 return; 219 } 220 221 flags = arch_local_save_flags(); 222 flags |= (STATUS_E1_MASK | STATUS_E2_MASK); 223 arch_local_irq_restore(flags); 224 } 225 #endif 226 EXPORT_SYMBOL(arch_local_irq_enable); 227