1/* 2 * ARC CPU startup Code 3 * 4 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com) 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 * 10 * Vineetg: Dec 2007 11 * -Check if we are running on Simulator or on real hardware 12 * to skip certain things during boot on simulator 13 */ 14 15#include <asm/asm-offsets.h> 16#include <asm/entry.h> 17#include <linux/linkage.h> 18#include <asm/arcregs.h> 19 20 .cpu A7 21 22 .section .init.text, "ax",@progbits 23 .type stext, @function 24 .globl stext 25stext: 26 ;------------------------------------------------------------------- 27 ; Don't clobber r0-r4 yet. It might have bootloader provided info 28 ;------------------------------------------------------------------- 29 30 sr @_int_vec_base_lds, [AUX_INTR_VEC_BASE] 31 32#ifdef CONFIG_SMP 33 ; Only Boot (Master) proceeds. Others wait in platform dependent way 34 ; IDENTITY Reg [ 3 2 1 0 ] 35 ; (cpu-id) ^^^ => Zero for UP ARC700 36 ; => #Core-ID if SMP (Master 0) 37 ; Note that non-boot CPUs might not land here if halt-on-reset and 38 ; instead breath life from @first_lines_of_secondary, but we still 39 ; need to make sure only boot cpu takes this path. 40 GET_CPU_ID r5 41 cmp r5, 0 42 jnz arc_platform_smp_wait_to_boot 43#endif 44 ; Clear BSS before updating any globals 45 ; XXX: use ZOL here 46 mov r5, __bss_start 47 mov r6, __bss_stop 481: 49 st.ab 0, [r5,4] 50 brlt r5, r6, 1b 51 52#ifdef CONFIG_CMDLINE_UBOOT 53 ; support for bootloader provided cmdline 54 ; If cmdline passed by u-boot, then 55 ; r0 = 1 (because ATAGS parsing, now retired, used to use 0) 56 ; r1 = magic number (board identity) 57 ; r2 = addr of cmdline string (somewhere in memory/flash) 58 59 brne r0, 1, .Lother_bootup_chores ; u-boot didn't pass cmdline 60 breq r2, 0, .Lother_bootup_chores ; or cmdline is NULL 61 62 mov r5, @command_line 631: 64 ldb.ab r6, [r2, 1] 65 breq r6, 0, .Lother_bootup_chores 66 b.d 1b 67 stb.ab r6, [r5, 1] 68#endif 69 70.Lother_bootup_chores: 71 72 ; Identify if running on ISS vs Silicon 73 ; IDENTITY Reg [ 3 2 1 0 ] 74 ; (chip-id) ^^^^^ ==> 0xffff for ISS 75 lr r0, [identity] 76 lsr r3, r0, 16 77 cmp r3, 0xffff 78 mov.z r4, 0 79 mov.nz r4, 1 80 st r4, [@running_on_hw] 81 82 ; setup "current" tsk and optionally cache it in dedicated r25 83 mov r9, @init_task 84 SET_CURR_TASK_ON_CPU r9, r0 ; r9 = tsk, r0 = scratch 85 86 ; setup stack (fp, sp) 87 mov fp, 0 88 89 ; tsk->thread_info is really a PAGE, whose bottom hoists stack 90 GET_TSK_STACK_BASE r9, sp ; r9 = tsk, sp = stack base(output) 91 92 j start_kernel ; "C" entry point 93 94#ifdef CONFIG_SMP 95;---------------------------------------------------------------- 96; First lines of code run by secondary before jumping to 'C' 97;---------------------------------------------------------------- 98 .section .text, "ax",@progbits 99 .type first_lines_of_secondary, @function 100 .globl first_lines_of_secondary 101 102first_lines_of_secondary: 103 104 sr @_int_vec_base_lds, [AUX_INTR_VEC_BASE] 105 106 ; setup per-cpu idle task as "current" on this CPU 107 ld r0, [@secondary_idle_tsk] 108 SET_CURR_TASK_ON_CPU r0, r1 109 110 ; setup stack (fp, sp) 111 mov fp, 0 112 113 ; set it's stack base to tsk->thread_info bottom 114 GET_TSK_STACK_BASE r0, sp 115 116 j start_kernel_secondary 117 118#endif 119