1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com) 4 * 5 * vineetg: May 2011 6 * -Refactored get_new_mmu_context( ) to only handle live-mm. 7 * retiring-mm handled in other hooks 8 * 9 * Vineetg: March 25th, 2008: Bug #92690 10 * -Major rewrite of Core ASID allocation routine get_new_mmu_context 11 * 12 * Amit Bhor, Sameer Dhavale: Codito Technologies 2004 13 */ 14 15 #ifndef _ASM_ARC_MMU_CONTEXT_H 16 #define _ASM_ARC_MMU_CONTEXT_H 17 18 #include <linux/sched/mm.h> 19 20 #include <asm/tlb.h> 21 #include <asm-generic/mm_hooks.h> 22 23 /* ARC ASID Management 24 * 25 * MMU tags TLBs with an 8-bit ASID, avoiding need to flush the TLB on 26 * context-switch. 27 * 28 * ASID is managed per cpu, so task threads across CPUs can have different 29 * ASID. Global ASID management is needed if hardware supports TLB shootdown 30 * and/or shared TLB across cores, which ARC doesn't. 31 * 32 * Each task is assigned unique ASID, with a simple round-robin allocator 33 * tracked in @asid_cpu. When 8-bit value rolls over,a new cycle is started 34 * over from 0, and TLB is flushed 35 * 36 * A new allocation cycle, post rollover, could potentially reassign an ASID 37 * to a different task. Thus the rule is to refresh the ASID in a new cycle. 38 * The 32 bit @asid_cpu (and mm->asid) have 8 bits MMU PID and rest 24 bits 39 * serve as cycle/generation indicator and natural 32 bit unsigned math 40 * automagically increments the generation when lower 8 bits rollover. 41 */ 42 43 #define MM_CTXT_ASID_MASK 0x000000ff /* MMU PID reg :8 bit PID */ 44 #define MM_CTXT_CYCLE_MASK (~MM_CTXT_ASID_MASK) 45 46 #define MM_CTXT_FIRST_CYCLE (MM_CTXT_ASID_MASK + 1) 47 #define MM_CTXT_NO_ASID 0UL 48 49 #define asid_mm(mm, cpu) mm->context.asid[cpu] 50 #define hw_pid(mm, cpu) (asid_mm(mm, cpu) & MM_CTXT_ASID_MASK) 51 52 DECLARE_PER_CPU(unsigned int, asid_cache); 53 #define asid_cpu(cpu) per_cpu(asid_cache, cpu) 54 55 /* 56 * Get a new ASID if task doesn't have a valid one (unalloc or from prev cycle) 57 * Also set the MMU PID register to existing/updated ASID 58 */ 59 static inline void get_new_mmu_context(struct mm_struct *mm) 60 { 61 const unsigned int cpu = smp_processor_id(); 62 unsigned long flags; 63 64 local_irq_save(flags); 65 66 /* 67 * Move to new ASID if it was not from current alloc-cycle/generation. 68 * This is done by ensuring that the generation bits in both mm->ASID 69 * and cpu's ASID counter are exactly same. 70 * 71 * Note: Callers needing new ASID unconditionally, independent of 72 * generation, e.g. local_flush_tlb_mm() for forking parent, 73 * first need to destroy the context, setting it to invalid 74 * value. 75 */ 76 if (!((asid_mm(mm, cpu) ^ asid_cpu(cpu)) & MM_CTXT_CYCLE_MASK)) 77 goto set_hw; 78 79 /* move to new ASID and handle rollover */ 80 if (unlikely(!(++asid_cpu(cpu) & MM_CTXT_ASID_MASK))) { 81 82 local_flush_tlb_all(); 83 84 /* 85 * Above check for rollover of 8 bit ASID in 32 bit container. 86 * If the container itself wrapped around, set it to a non zero 87 * "generation" to distinguish from no context 88 */ 89 if (!asid_cpu(cpu)) 90 asid_cpu(cpu) = MM_CTXT_FIRST_CYCLE; 91 } 92 93 /* Assign new ASID to tsk */ 94 asid_mm(mm, cpu) = asid_cpu(cpu); 95 96 set_hw: 97 mmu_setup_asid(mm, hw_pid(mm, cpu)); 98 99 local_irq_restore(flags); 100 } 101 102 /* 103 * Initialize the context related info for a new mm_struct 104 * instance. 105 */ 106 #define init_new_context init_new_context 107 static inline int 108 init_new_context(struct task_struct *tsk, struct mm_struct *mm) 109 { 110 int i; 111 112 for_each_possible_cpu(i) 113 asid_mm(mm, i) = MM_CTXT_NO_ASID; 114 115 return 0; 116 } 117 118 #define destroy_context destroy_context 119 static inline void destroy_context(struct mm_struct *mm) 120 { 121 unsigned long flags; 122 123 /* Needed to elide CONFIG_DEBUG_PREEMPT warning */ 124 local_irq_save(flags); 125 asid_mm(mm, smp_processor_id()) = MM_CTXT_NO_ASID; 126 local_irq_restore(flags); 127 } 128 129 /* Prepare the MMU for task: setup PID reg with allocated ASID 130 If task doesn't have an ASID (never alloc or stolen, get a new ASID) 131 */ 132 static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next, 133 struct task_struct *tsk) 134 { 135 const int cpu = smp_processor_id(); 136 137 /* 138 * Note that the mm_cpumask is "aggregating" only, we don't clear it 139 * for the switched-out task, unlike some other arches. 140 * It is used to enlist cpus for sending TLB flush IPIs and not sending 141 * it to CPUs where a task once ran-on, could cause stale TLB entry 142 * re-use, specially for a multi-threaded task. 143 * e.g. T1 runs on C1, migrates to C3. T2 running on C2 munmaps. 144 * For a non-aggregating mm_cpumask, IPI not sent C1, and if T1 145 * were to re-migrate to C1, it could access the unmapped region 146 * via any existing stale TLB entries. 147 */ 148 cpumask_set_cpu(cpu, mm_cpumask(next)); 149 150 mmu_setup_pgd(next, next->pgd); 151 152 get_new_mmu_context(next); 153 } 154 155 /* 156 * activate_mm defaults (in asm-generic) to switch_mm and is called at the 157 * time of execve() to get a new ASID Note the subtlety here: 158 * get_new_mmu_context() behaves differently here vs. in switch_mm(). Here 159 * it always returns a new ASID, because mm has an unallocated "initial" 160 * value, while in latter, it moves to a new ASID, only if it was 161 * unallocated 162 */ 163 164 /* it seemed that deactivate_mm( ) is a reasonable place to do book-keeping 165 * for retiring-mm. However destroy_context( ) still needs to do that because 166 * between mm_release( ) = >deactive_mm( ) and 167 * mmput => .. => __mmdrop( ) => destroy_context( ) 168 * there is a good chance that task gets sched-out/in, making its ASID valid 169 * again (this teased me for a whole day). 170 */ 171 172 #include <asm-generic/mmu_context.h> 173 174 #endif /* __ASM_ARC_MMU_CONTEXT_H */ 175