1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com) 4 */ 5 6 #ifndef _ASM_ARC_MMU_H 7 #define _ASM_ARC_MMU_H 8 9 #ifndef __ASSEMBLY__ 10 #include <linux/threads.h> /* NR_CPUS */ 11 #endif 12 13 #if defined(CONFIG_ARC_MMU_V1) 14 #define CONFIG_ARC_MMU_VER 1 15 #elif defined(CONFIG_ARC_MMU_V2) 16 #define CONFIG_ARC_MMU_VER 2 17 #elif defined(CONFIG_ARC_MMU_V3) 18 #define CONFIG_ARC_MMU_VER 3 19 #elif defined(CONFIG_ARC_MMU_V4) 20 #define CONFIG_ARC_MMU_VER 4 21 #endif 22 23 /* MMU Management regs */ 24 #define ARC_REG_MMU_BCR 0x06f 25 #if (CONFIG_ARC_MMU_VER < 4) 26 #define ARC_REG_TLBPD0 0x405 27 #define ARC_REG_TLBPD1 0x406 28 #define ARC_REG_TLBPD1HI 0 /* Dummy: allows code sharing with ARC700 */ 29 #define ARC_REG_TLBINDEX 0x407 30 #define ARC_REG_TLBCOMMAND 0x408 31 #define ARC_REG_PID 0x409 32 #define ARC_REG_SCRATCH_DATA0 0x418 33 #else 34 #define ARC_REG_TLBPD0 0x460 35 #define ARC_REG_TLBPD1 0x461 36 #define ARC_REG_TLBPD1HI 0x463 37 #define ARC_REG_TLBINDEX 0x464 38 #define ARC_REG_TLBCOMMAND 0x465 39 #define ARC_REG_PID 0x468 40 #define ARC_REG_SCRATCH_DATA0 0x46c 41 #endif 42 43 /* Bits in MMU PID register */ 44 #define __TLB_ENABLE (1 << 31) 45 #define __PROG_ENABLE (1 << 30) 46 #define MMU_ENABLE (__TLB_ENABLE | __PROG_ENABLE) 47 48 /* Error code if probe fails */ 49 #define TLB_LKUP_ERR 0x80000000 50 51 #if (CONFIG_ARC_MMU_VER < 4) 52 #define TLB_DUP_ERR (TLB_LKUP_ERR | 0x00000001) 53 #else 54 #define TLB_DUP_ERR (TLB_LKUP_ERR | 0x40000000) 55 #endif 56 57 /* TLB Commands */ 58 #define TLBWrite 0x1 59 #define TLBRead 0x2 60 #define TLBGetIndex 0x3 61 #define TLBProbe 0x4 62 63 #if (CONFIG_ARC_MMU_VER >= 2) 64 #define TLBWriteNI 0x5 /* write JTLB without inv uTLBs */ 65 #define TLBIVUTLB 0x6 /* explicitly inv uTLBs */ 66 #endif 67 68 #if (CONFIG_ARC_MMU_VER >= 4) 69 #define TLBInsertEntry 0x7 70 #define TLBDeleteEntry 0x8 71 #endif 72 73 #ifndef __ASSEMBLY__ 74 75 typedef struct { 76 unsigned long asid[NR_CPUS]; /* 8 bit MMU PID + Generation cycle */ 77 } mm_context_t; 78 79 #ifdef CONFIG_ARC_DBG_TLB_PARANOIA 80 void tlb_paranoid_check(unsigned int mm_asid, unsigned long address); 81 #else 82 #define tlb_paranoid_check(a, b) 83 #endif 84 85 void arc_mmu_init(void); 86 extern char *arc_mmu_mumbojumbo(int cpu_id, char *buf, int len); 87 void read_decode_mmu_bcr(void); 88 89 static inline int is_pae40_enabled(void) 90 { 91 return IS_ENABLED(CONFIG_ARC_HAS_PAE40); 92 } 93 94 extern int pae40_exist_but_not_enab(void); 95 96 #endif /* !__ASSEMBLY__ */ 97 98 #endif 99