1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2004, 2007-2010, 2011-2012, 2019-20 Synopsys, Inc. (www.synopsys.com) 4 * 5 * MMUv3 (arc700) / MMUv4 (archs) are software page walked and software managed. 6 * This file contains the TLB access registers and commands 7 */ 8 9 #ifndef _ASM_ARC_MMU_ARCV2_H 10 #define _ASM_ARC_MMU_ARCV2_H 11 12 #include <soc/arc/aux.h> 13 14 /* 15 * TLB Management regs 16 */ 17 #define ARC_REG_MMU_BCR 0x06f 18 19 #ifdef CONFIG_ARC_MMU_V3 20 #define ARC_REG_TLBPD0 0x405 21 #define ARC_REG_TLBPD1 0x406 22 #define ARC_REG_TLBPD1HI 0 /* Dummy: allows common code */ 23 #define ARC_REG_TLBINDEX 0x407 24 #define ARC_REG_TLBCOMMAND 0x408 25 #define ARC_REG_PID 0x409 26 #define ARC_REG_SCRATCH_DATA0 0x418 27 #else 28 #define ARC_REG_TLBPD0 0x460 29 #define ARC_REG_TLBPD1 0x461 30 #define ARC_REG_TLBPD1HI 0x463 31 #define ARC_REG_TLBINDEX 0x464 32 #define ARC_REG_TLBCOMMAND 0x465 33 #define ARC_REG_PID 0x468 34 #define ARC_REG_SCRATCH_DATA0 0x46c 35 #endif 36 37 /* Bits in MMU PID reg */ 38 #define __TLB_ENABLE (1 << 31) 39 #define __PROG_ENABLE (1 << 30) 40 #define MMU_ENABLE (__TLB_ENABLE | __PROG_ENABLE) 41 42 /* Bits in TLB Index reg */ 43 #define TLB_LKUP_ERR 0x80000000 44 45 #ifdef CONFIG_ARC_MMU_V3 46 #define TLB_DUP_ERR (TLB_LKUP_ERR | 0x00000001) 47 #else 48 #define TLB_DUP_ERR (TLB_LKUP_ERR | 0x40000000) 49 #endif 50 51 /* 52 * TLB Commands 53 */ 54 #define TLBWrite 0x1 55 #define TLBRead 0x2 56 #define TLBGetIndex 0x3 57 #define TLBProbe 0x4 58 #define TLBWriteNI 0x5 /* write JTLB without inv uTLBs */ 59 #define TLBIVUTLB 0x6 /* explicitly inv uTLBs */ 60 61 #ifdef CONFIG_ARC_MMU_V4 62 #define TLBInsertEntry 0x7 63 #define TLBDeleteEntry 0x8 64 #endif 65 66 /* Masks for actual TLB "PD"s */ 67 #define PTE_BITS_IN_PD0 (_PAGE_GLOBAL | _PAGE_PRESENT | _PAGE_HW_SZ) 68 #define PTE_BITS_RWX (_PAGE_EXECUTE | _PAGE_WRITE | _PAGE_READ) 69 70 #define PTE_BITS_NON_RWX_IN_PD1 (PAGE_MASK_PHYS | _PAGE_CACHEABLE) 71 72 #ifndef __ASSEMBLY__ 73 74 struct mm_struct; 75 extern int pae40_exist_but_not_enab(void); 76 77 static inline int is_pae40_enabled(void) 78 { 79 return IS_ENABLED(CONFIG_ARC_HAS_PAE40); 80 } 81 82 static inline void mmu_setup_asid(struct mm_struct *mm, unsigned long asid) 83 { 84 write_aux_reg(ARC_REG_PID, asid | MMU_ENABLE); 85 } 86 87 static inline void mmu_setup_pgd(struct mm_struct *mm, void *pgd) 88 { 89 /* PGD cached in MMU reg to avoid 3 mem lookups: task->mm->pgd */ 90 #ifdef CONFIG_ISA_ARCV2 91 write_aux_reg(ARC_REG_SCRATCH_DATA0, (unsigned int)pgd); 92 #endif 93 } 94 95 #else 96 97 .macro ARC_MMU_REENABLE reg 98 lr \reg, [ARC_REG_PID] 99 or \reg, \reg, MMU_ENABLE 100 sr \reg, [ARC_REG_PID] 101 .endm 102 103 #endif /* !__ASSEMBLY__ */ 104 105 #endif 106