1 /* 2 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com) 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 */ 8 9 #ifndef _ASM_ARC_IO_H 10 #define _ASM_ARC_IO_H 11 12 #include <linux/types.h> 13 #include <asm/byteorder.h> 14 #include <asm/page.h> 15 16 extern void __iomem *ioremap(unsigned long physaddr, unsigned long size); 17 extern void __iomem *ioremap_prot(phys_addr_t offset, unsigned long size, 18 unsigned long flags); 19 extern void iounmap(const void __iomem *addr); 20 21 #define ioremap_nocache(phy, sz) ioremap(phy, sz) 22 #define ioremap_wc(phy, sz) ioremap(phy, sz) 23 24 /* Change struct page to physical address */ 25 #define page_to_phys(page) (page_to_pfn(page) << PAGE_SHIFT) 26 27 #define __raw_readb __raw_readb 28 static inline u8 __raw_readb(const volatile void __iomem *addr) 29 { 30 u8 b; 31 32 __asm__ __volatile__( 33 " ldb%U1 %0, %1 \n" 34 : "=r" (b) 35 : "m" (*(volatile u8 __force *)addr) 36 : "memory"); 37 38 return b; 39 } 40 41 #define __raw_readw __raw_readw 42 static inline u16 __raw_readw(const volatile void __iomem *addr) 43 { 44 u16 s; 45 46 __asm__ __volatile__( 47 " ldw%U1 %0, %1 \n" 48 : "=r" (s) 49 : "m" (*(volatile u16 __force *)addr) 50 : "memory"); 51 52 return s; 53 } 54 55 #define __raw_readl __raw_readl 56 static inline u32 __raw_readl(const volatile void __iomem *addr) 57 { 58 u32 w; 59 60 __asm__ __volatile__( 61 " ld%U1 %0, %1 \n" 62 : "=r" (w) 63 : "m" (*(volatile u32 __force *)addr) 64 : "memory"); 65 66 return w; 67 } 68 69 #define __raw_writeb __raw_writeb 70 static inline void __raw_writeb(u8 b, volatile void __iomem *addr) 71 { 72 __asm__ __volatile__( 73 " stb%U1 %0, %1 \n" 74 : 75 : "r" (b), "m" (*(volatile u8 __force *)addr) 76 : "memory"); 77 } 78 79 #define __raw_writew __raw_writew 80 static inline void __raw_writew(u16 s, volatile void __iomem *addr) 81 { 82 __asm__ __volatile__( 83 " stw%U1 %0, %1 \n" 84 : 85 : "r" (s), "m" (*(volatile u16 __force *)addr) 86 : "memory"); 87 88 } 89 90 #define __raw_writel __raw_writel 91 static inline void __raw_writel(u32 w, volatile void __iomem *addr) 92 { 93 __asm__ __volatile__( 94 " st%U1 %0, %1 \n" 95 : 96 : "r" (w), "m" (*(volatile u32 __force *)addr) 97 : "memory"); 98 99 } 100 101 #ifdef CONFIG_ISA_ARCV2 102 #include <asm/barrier.h> 103 #define __iormb() rmb() 104 #define __iowmb() wmb() 105 #else 106 #define __iormb() do { } while (0) 107 #define __iowmb() do { } while (0) 108 #endif 109 110 /* 111 * MMIO can also get buffered/optimized in micro-arch, so barriers needed 112 * Based on ARM model for the typical use case 113 * 114 * <ST [DMA buffer]> 115 * <writel MMIO "go" reg> 116 * or: 117 * <readl MMIO "status" reg> 118 * <LD [DMA buffer]> 119 * 120 * http://lkml.kernel.org/r/20150622133656.GG1583@arm.com 121 */ 122 #define readb(c) ({ u8 __v = readb_relaxed(c); __iormb(); __v; }) 123 #define readw(c) ({ u16 __v = readw_relaxed(c); __iormb(); __v; }) 124 #define readl(c) ({ u32 __v = readl_relaxed(c); __iormb(); __v; }) 125 126 #define writeb(v,c) ({ __iowmb(); writeb_relaxed(v,c); }) 127 #define writew(v,c) ({ __iowmb(); writew_relaxed(v,c); }) 128 #define writel(v,c) ({ __iowmb(); writel_relaxed(v,c); }) 129 130 /* 131 * Relaxed API for drivers which can handle any ordering themselves 132 */ 133 #define readb_relaxed(c) __raw_readb(c) 134 #define readw_relaxed(c) __raw_readw(c) 135 #define readl_relaxed(c) __raw_readl(c) 136 137 #define writeb_relaxed(v,c) __raw_writeb(v,c) 138 #define writew_relaxed(v,c) __raw_writew(v,c) 139 #define writel_relaxed(v,c) __raw_writel(v,c) 140 141 #include <asm-generic/io.h> 142 143 #endif /* _ASM_ARC_IO_H */ 144