1 /* 2 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com) 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 */ 8 9 #ifndef _ASM_ARC_ARCREGS_H 10 #define _ASM_ARC_ARCREGS_H 11 12 #ifdef __KERNEL__ 13 14 /* status32 Bits Positions */ 15 #define STATUS_H_BIT 0 /* CPU Halted */ 16 #define STATUS_E1_BIT 1 /* Int 1 enable */ 17 #define STATUS_E2_BIT 2 /* Int 2 enable */ 18 #define STATUS_A1_BIT 3 /* Int 1 active */ 19 #define STATUS_A2_BIT 4 /* Int 2 active */ 20 #define STATUS_AE_BIT 5 /* Exception active */ 21 #define STATUS_DE_BIT 6 /* PC is in delay slot */ 22 #define STATUS_U_BIT 7 /* User/Kernel mode */ 23 #define STATUS_L_BIT 12 /* Loop inhibit */ 24 25 /* These masks correspond to the status word(STATUS_32) bits */ 26 #define STATUS_H_MASK (1<<STATUS_H_BIT) 27 #define STATUS_E1_MASK (1<<STATUS_E1_BIT) 28 #define STATUS_E2_MASK (1<<STATUS_E2_BIT) 29 #define STATUS_A1_MASK (1<<STATUS_A1_BIT) 30 #define STATUS_A2_MASK (1<<STATUS_A2_BIT) 31 #define STATUS_AE_MASK (1<<STATUS_AE_BIT) 32 #define STATUS_DE_MASK (1<<STATUS_DE_BIT) 33 #define STATUS_U_MASK (1<<STATUS_U_BIT) 34 #define STATUS_L_MASK (1<<STATUS_L_BIT) 35 36 /* Auxiliary registers */ 37 #define AUX_IDENTITY 4 38 #define AUX_INTR_VEC_BASE 0x25 39 #define AUX_IRQ_LEV 0x200 /* IRQ Priority: L1 or L2 */ 40 #define AUX_IRQ_HINT 0x201 /* For generating Soft Interrupts */ 41 #define AUX_IRQ_LV12 0x43 /* interrupt level register */ 42 43 #define AUX_IENABLE 0x40c 44 #define AUX_ITRIGGER 0x40d 45 #define AUX_IPULSE 0x415 46 47 #ifndef __ASSEMBLY__ 48 49 /* 50 ****************************************************************** 51 * Inline ASM macros to read/write AUX Regs 52 * Essentially invocation of lr/sr insns from "C" 53 */ 54 55 #if 1 56 57 #define read_aux_reg(reg) __builtin_arc_lr(reg) 58 59 /* gcc builtin sr needs reg param to be long immediate */ 60 #define write_aux_reg(reg_immed, val) \ 61 __builtin_arc_sr((unsigned int)val, reg_immed) 62 63 #else 64 65 #define read_aux_reg(reg) \ 66 ({ \ 67 unsigned int __ret; \ 68 __asm__ __volatile__( \ 69 " lr %0, [%1]" \ 70 : "=r"(__ret) \ 71 : "i"(reg)); \ 72 __ret; \ 73 }) 74 75 /* 76 * Aux Reg address is specified as long immediate by caller 77 * e.g. 78 * write_aux_reg(0x69, some_val); 79 * This generates tightest code. 80 */ 81 #define write_aux_reg(reg_imm, val) \ 82 ({ \ 83 __asm__ __volatile__( \ 84 " sr %0, [%1] \n" \ 85 : \ 86 : "ir"(val), "i"(reg_imm)); \ 87 }) 88 89 /* 90 * Aux Reg address is specified in a variable 91 * * e.g. 92 * reg_num = 0x69 93 * write_aux_reg2(reg_num, some_val); 94 * This has to generate glue code to load the reg num from 95 * memory to a reg hence not recommended. 96 */ 97 #define write_aux_reg2(reg_in_var, val) \ 98 ({ \ 99 unsigned int tmp; \ 100 \ 101 __asm__ __volatile__( \ 102 " ld %0, [%2] \n\t" \ 103 " sr %1, [%0] \n\t" \ 104 : "=&r"(tmp) \ 105 : "r"(val), "memory"(®_in_var)); \ 106 }) 107 108 #endif 109 110 #endif /* __ASEMBLY__ */ 111 112 #endif /* __KERNEL__ */ 113 114 #endif /* _ASM_ARC_ARCREGS_H */ 115