1/* 2 * Copyright (C) 2014, 2015 Synopsys, Inc. (www.synopsys.com) 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 */ 8 9/* 10 * Device tree for AXC003 CPU card: 11 * HS38x2 (Dual Core) with IDU intc (VDK version) 12 */ 13 14/ { 15 compatible = "snps,arc"; 16 clock-frequency = <50000000>; 17 #address-cells = <1>; 18 #size-cells = <1>; 19 20 cpu_card { 21 compatible = "simple-bus"; 22 #address-cells = <1>; 23 #size-cells = <1>; 24 25 ranges = <0x00000000 0xf0000000 0x10000000>; 26 27 cpu_intc: archs-intc@cpu { 28 compatible = "snps,archs-intc"; 29 interrupt-controller; 30 #interrupt-cells = <1>; 31 }; 32 33 idu_intc: idu-interrupt-controller { 34 compatible = "snps,archs-idu-intc"; 35 interrupt-controller; 36 interrupt-parent = <&cpu_intc>; 37 38 /* 39 * <hwirq distribution> 40 * distribution: 0=RR; 1=cpu0, 2=cpu1, 4=cpu2, 8=cpu3 41 */ 42 #interrupt-cells = <2>; 43 44 interrupts = <24 25 26 27>; 45 }; 46 47 debug_uart: dw-apb-uart@0x5000 { 48 compatible = "snps,dw-apb-uart"; 49 reg = <0x5000 0x100>; 50 clock-frequency = <2403200>; 51 interrupt-parent = <&idu_intc>; 52 interrupts = <2 0>; 53 baud = <115200>; 54 reg-shift = <2>; 55 reg-io-width = <4>; 56 }; 57 58 }; 59 60 mb_intc: dw-apb-ictl@0xe0012000 { 61 #interrupt-cells = <1>; 62 compatible = "snps,dw-apb-ictl"; 63 reg = < 0xe0012000 0x200 >; 64 interrupt-controller; 65 interrupt-parent = <&idu_intc>; 66 interrupts = < 0 0 >; 67 }; 68 69 memory { 70 #address-cells = <1>; 71 #size-cells = <1>; 72 ranges = <0x00000000 0x80000000 0x40000000>; 73 device_type = "memory"; 74 reg = <0x00000000 0x20000000>; /* 512MiB */ 75 }; 76}; 77