xref: /linux/arch/arc/boot/dts/vdk_axc003_idu.dtsi (revision f759ee57b205223e98fdc97e26cbef305b8048e1)
12924cd18SRuud Derwig/*
22924cd18SRuud Derwig * Copyright (C) 2014, 2015 Synopsys, Inc. (www.synopsys.com)
32924cd18SRuud Derwig *
42924cd18SRuud Derwig * This program is free software; you can redistribute it and/or modify
52924cd18SRuud Derwig * it under the terms of the GNU General Public License version 2 as
62924cd18SRuud Derwig * published by the Free Software Foundation.
72924cd18SRuud Derwig */
82924cd18SRuud Derwig
92924cd18SRuud Derwig/*
102924cd18SRuud Derwig * Device tree for AXC003 CPU card:
112924cd18SRuud Derwig * HS38x2 (Dual Core) with IDU intc (VDK version)
122924cd18SRuud Derwig */
132924cd18SRuud Derwig
142924cd18SRuud Derwig/ {
152924cd18SRuud Derwig	compatible = "snps,arc";
162924cd18SRuud Derwig	clock-frequency = <50000000>;
172924cd18SRuud Derwig	#address-cells = <1>;
182924cd18SRuud Derwig	#size-cells = <1>;
192924cd18SRuud Derwig
202924cd18SRuud Derwig	cpu_card {
212924cd18SRuud Derwig		compatible = "simple-bus";
222924cd18SRuud Derwig		#address-cells = <1>;
232924cd18SRuud Derwig		#size-cells = <1>;
242924cd18SRuud Derwig
252924cd18SRuud Derwig		ranges = <0x00000000 0xf0000000 0x10000000>;
262924cd18SRuud Derwig
272924cd18SRuud Derwig		cpu_intc: archs-intc@cpu {
282924cd18SRuud Derwig			compatible = "snps,archs-intc";
292924cd18SRuud Derwig			interrupt-controller;
302924cd18SRuud Derwig			#interrupt-cells = <1>;
312924cd18SRuud Derwig		};
322924cd18SRuud Derwig
332924cd18SRuud Derwig		idu_intc: idu-interrupt-controller {
342924cd18SRuud Derwig			compatible = "snps,archs-idu-intc";
352924cd18SRuud Derwig			interrupt-controller;
362924cd18SRuud Derwig			interrupt-parent = <&cpu_intc>;
372924cd18SRuud Derwig
382924cd18SRuud Derwig			/*
392924cd18SRuud Derwig			 * <hwirq  distribution>
402924cd18SRuud Derwig			 * distribution: 0=RR; 1=cpu0, 2=cpu1, 4=cpu2, 8=cpu3
412924cd18SRuud Derwig			 */
422924cd18SRuud Derwig			#interrupt-cells = <2>;
432924cd18SRuud Derwig
442924cd18SRuud Derwig			interrupts = <24 25 26 27>;
452924cd18SRuud Derwig		};
462924cd18SRuud Derwig
472924cd18SRuud Derwig		debug_uart: dw-apb-uart@0x5000 {
482924cd18SRuud Derwig			compatible = "snps,dw-apb-uart";
492924cd18SRuud Derwig			reg = <0x5000 0x100>;
502924cd18SRuud Derwig			clock-frequency = <2403200>;
512924cd18SRuud Derwig			interrupt-parent = <&idu_intc>;
522924cd18SRuud Derwig			interrupts = <2 0>;
532924cd18SRuud Derwig			baud = <115200>;
542924cd18SRuud Derwig			reg-shift = <2>;
552924cd18SRuud Derwig			reg-io-width = <4>;
562924cd18SRuud Derwig		};
572924cd18SRuud Derwig
582924cd18SRuud Derwig	};
592924cd18SRuud Derwig
602924cd18SRuud Derwig	mb_intc: dw-apb-ictl@0xe0012000 {
612924cd18SRuud Derwig		#interrupt-cells = <1>;
622924cd18SRuud Derwig		compatible = "snps,dw-apb-ictl";
632924cd18SRuud Derwig		reg = < 0xe0012000 0x200 >;
642924cd18SRuud Derwig		interrupt-controller;
652924cd18SRuud Derwig		interrupt-parent = <&idu_intc>;
662924cd18SRuud Derwig		interrupts = < 0 0 >;
672924cd18SRuud Derwig	};
682924cd18SRuud Derwig
692924cd18SRuud Derwig	memory {
702924cd18SRuud Derwig		#address-cells = <1>;
712924cd18SRuud Derwig		#size-cells = <1>;
722924cd18SRuud Derwig		ranges = <0x00000000 0x80000000 0x40000000>;
732924cd18SRuud Derwig		device_type = "memory";
74*f759ee57SVineet Gupta		reg = <0x80000000 0x20000000>;	/* 512MiB */
752924cd18SRuud Derwig	};
762924cd18SRuud Derwig};
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