xref: /linux/arch/arc/boot/dts/vdk_axc003_idu.dtsi (revision ef4c54c340de47bf167b326f7560c1cc3751d154)
12924cd18SRuud Derwig/*
22924cd18SRuud Derwig * Copyright (C) 2014, 2015 Synopsys, Inc. (www.synopsys.com)
32924cd18SRuud Derwig *
42924cd18SRuud Derwig * This program is free software; you can redistribute it and/or modify
52924cd18SRuud Derwig * it under the terms of the GNU General Public License version 2 as
62924cd18SRuud Derwig * published by the Free Software Foundation.
72924cd18SRuud Derwig */
82924cd18SRuud Derwig
92924cd18SRuud Derwig/*
102924cd18SRuud Derwig * Device tree for AXC003 CPU card:
112924cd18SRuud Derwig * HS38x2 (Dual Core) with IDU intc (VDK version)
122924cd18SRuud Derwig */
132924cd18SRuud Derwig
142e8cd938SVineet Gupta/include/ "skeleton_hs_idu.dtsi"
152e8cd938SVineet Gupta
162924cd18SRuud Derwig/ {
172924cd18SRuud Derwig	compatible = "snps,arc";
182924cd18SRuud Derwig	#address-cells = <1>;
192924cd18SRuud Derwig	#size-cells = <1>;
202924cd18SRuud Derwig
212924cd18SRuud Derwig	cpu_card {
222924cd18SRuud Derwig		compatible = "simple-bus";
232924cd18SRuud Derwig		#address-cells = <1>;
242924cd18SRuud Derwig		#size-cells = <1>;
252924cd18SRuud Derwig
262924cd18SRuud Derwig		ranges = <0x00000000 0xf0000000 0x10000000>;
272924cd18SRuud Derwig
28b3d6aba8SVineet Gupta		core_clk: core_clk {
29b3d6aba8SVineet Gupta			#clock-cells = <0>;
30b3d6aba8SVineet Gupta			compatible = "fixed-clock";
31b3d6aba8SVineet Gupta			clock-frequency = <50000000>;
32b3d6aba8SVineet Gupta		};
33b3d6aba8SVineet Gupta
349ba7648cSVineet Gupta		core_intc: archs-intc@cpu {
352924cd18SRuud Derwig			compatible = "snps,archs-intc";
362924cd18SRuud Derwig			interrupt-controller;
372924cd18SRuud Derwig			#interrupt-cells = <1>;
382924cd18SRuud Derwig		};
392924cd18SRuud Derwig
402924cd18SRuud Derwig		idu_intc: idu-interrupt-controller {
412924cd18SRuud Derwig			compatible = "snps,archs-idu-intc";
422924cd18SRuud Derwig			interrupt-controller;
439ba7648cSVineet Gupta			interrupt-parent = <&core_intc>;
44ec69b269SYuriy Kolerov			#interrupt-cells = <1>;
452924cd18SRuud Derwig		};
462924cd18SRuud Derwig
47*ef4c54c3SAlexey Brodkin		debug_uart: dw-apb-uart@5000 {
482924cd18SRuud Derwig			compatible = "snps,dw-apb-uart";
492924cd18SRuud Derwig			reg = <0x5000 0x100>;
502924cd18SRuud Derwig			clock-frequency = <2403200>;
512924cd18SRuud Derwig			interrupt-parent = <&idu_intc>;
52ec69b269SYuriy Kolerov			interrupts = <2>;
532924cd18SRuud Derwig			baud = <115200>;
542924cd18SRuud Derwig			reg-shift = <2>;
552924cd18SRuud Derwig			reg-io-width = <4>;
562924cd18SRuud Derwig		};
572924cd18SRuud Derwig
582924cd18SRuud Derwig	};
592924cd18SRuud Derwig
60*ef4c54c3SAlexey Brodkin	mb_intc: dw-apb-ictl@e0012000 {
612924cd18SRuud Derwig		#interrupt-cells = <1>;
622924cd18SRuud Derwig		compatible = "snps,dw-apb-ictl";
632924cd18SRuud Derwig		reg = < 0xe0012000 0x200 >;
642924cd18SRuud Derwig		interrupt-controller;
652924cd18SRuud Derwig		interrupt-parent = <&idu_intc>;
66ec69b269SYuriy Kolerov		interrupts = <0>;
672924cd18SRuud Derwig	};
682924cd18SRuud Derwig
692924cd18SRuud Derwig	memory {
702924cd18SRuud Derwig		#address-cells = <1>;
712924cd18SRuud Derwig		#size-cells = <1>;
722924cd18SRuud Derwig		ranges = <0x00000000 0x80000000 0x40000000>;
732924cd18SRuud Derwig		device_type = "memory";
74f759ee57SVineet Gupta		reg = <0x80000000 0x20000000>;	/* 512MiB */
752924cd18SRuud Derwig	};
762924cd18SRuud Derwig};
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