1d2912cb1SThomas Gleixner// SPDX-License-Identifier: GPL-2.0-only 22924cd18SRuud Derwig/* 32924cd18SRuud Derwig * Copyright (C) 2014, 2015 Synopsys, Inc. (www.synopsys.com) 42924cd18SRuud Derwig */ 52924cd18SRuud Derwig 62924cd18SRuud Derwig/* 72924cd18SRuud Derwig * Device tree for AXC003 CPU card: 82924cd18SRuud Derwig * HS38x2 (Dual Core) with IDU intc (VDK version) 92924cd18SRuud Derwig */ 102924cd18SRuud Derwig 112e8cd938SVineet Gupta/include/ "skeleton_hs_idu.dtsi" 122e8cd938SVineet Gupta 132924cd18SRuud Derwig/ { 142924cd18SRuud Derwig compatible = "snps,arc"; 152924cd18SRuud Derwig #address-cells = <1>; 162924cd18SRuud Derwig #size-cells = <1>; 172924cd18SRuud Derwig 182924cd18SRuud Derwig cpu_card { 192924cd18SRuud Derwig compatible = "simple-bus"; 202924cd18SRuud Derwig #address-cells = <1>; 212924cd18SRuud Derwig #size-cells = <1>; 222924cd18SRuud Derwig 232924cd18SRuud Derwig ranges = <0x00000000 0xf0000000 0x10000000>; 242924cd18SRuud Derwig 25b3d6aba8SVineet Gupta core_clk: core_clk { 26b3d6aba8SVineet Gupta #clock-cells = <0>; 27b3d6aba8SVineet Gupta compatible = "fixed-clock"; 28b3d6aba8SVineet Gupta clock-frequency = <50000000>; 29b3d6aba8SVineet Gupta }; 30b3d6aba8SVineet Gupta 319ba7648cSVineet Gupta core_intc: archs-intc@cpu { 322924cd18SRuud Derwig compatible = "snps,archs-intc"; 332924cd18SRuud Derwig interrupt-controller; 342924cd18SRuud Derwig #interrupt-cells = <1>; 352924cd18SRuud Derwig }; 362924cd18SRuud Derwig 372924cd18SRuud Derwig idu_intc: idu-interrupt-controller { 382924cd18SRuud Derwig compatible = "snps,archs-idu-intc"; 392924cd18SRuud Derwig interrupt-controller; 409ba7648cSVineet Gupta interrupt-parent = <&core_intc>; 41ec69b269SYuriy Kolerov #interrupt-cells = <1>; 422924cd18SRuud Derwig }; 432924cd18SRuud Derwig 44ef4c54c3SAlexey Brodkin debug_uart: dw-apb-uart@5000 { 452924cd18SRuud Derwig compatible = "snps,dw-apb-uart"; 462924cd18SRuud Derwig reg = <0x5000 0x100>; 472924cd18SRuud Derwig clock-frequency = <2403200>; 482924cd18SRuud Derwig interrupt-parent = <&idu_intc>; 49ec69b269SYuriy Kolerov interrupts = <2>; 502924cd18SRuud Derwig baud = <115200>; 512924cd18SRuud Derwig reg-shift = <2>; 522924cd18SRuud Derwig reg-io-width = <4>; 532924cd18SRuud Derwig }; 542924cd18SRuud Derwig 552924cd18SRuud Derwig }; 562924cd18SRuud Derwig 57*05b1be68SZhen Lei mb_intc: interrupt-controller@e0012000 { 582924cd18SRuud Derwig #interrupt-cells = <1>; 592924cd18SRuud Derwig compatible = "snps,dw-apb-ictl"; 602924cd18SRuud Derwig reg = < 0xe0012000 0x200 >; 612924cd18SRuud Derwig interrupt-controller; 622924cd18SRuud Derwig interrupt-parent = <&idu_intc>; 63ec69b269SYuriy Kolerov interrupts = <0>; 642924cd18SRuud Derwig }; 652924cd18SRuud Derwig 662924cd18SRuud Derwig memory { 672924cd18SRuud Derwig #address-cells = <1>; 682924cd18SRuud Derwig #size-cells = <1>; 692924cd18SRuud Derwig ranges = <0x00000000 0x80000000 0x40000000>; 702924cd18SRuud Derwig device_type = "memory"; 71f759ee57SVineet Gupta reg = <0x80000000 0x20000000>; /* 512MiB */ 722924cd18SRuud Derwig }; 732924cd18SRuud Derwig}; 74