xref: /linux/arch/arc/boot/dts/vdk_axc003_idu.dtsi (revision b3d6aba8bd92c20b7748ccd82b6fab8ea5081066)
12924cd18SRuud Derwig/*
22924cd18SRuud Derwig * Copyright (C) 2014, 2015 Synopsys, Inc. (www.synopsys.com)
32924cd18SRuud Derwig *
42924cd18SRuud Derwig * This program is free software; you can redistribute it and/or modify
52924cd18SRuud Derwig * it under the terms of the GNU General Public License version 2 as
62924cd18SRuud Derwig * published by the Free Software Foundation.
72924cd18SRuud Derwig */
82924cd18SRuud Derwig
92924cd18SRuud Derwig/*
102924cd18SRuud Derwig * Device tree for AXC003 CPU card:
112924cd18SRuud Derwig * HS38x2 (Dual Core) with IDU intc (VDK version)
122924cd18SRuud Derwig */
132924cd18SRuud Derwig
142e8cd938SVineet Gupta/include/ "skeleton_hs_idu.dtsi"
152e8cd938SVineet Gupta
162924cd18SRuud Derwig/ {
172924cd18SRuud Derwig	compatible = "snps,arc";
182924cd18SRuud Derwig	clock-frequency = <50000000>;
192924cd18SRuud Derwig	#address-cells = <1>;
202924cd18SRuud Derwig	#size-cells = <1>;
212924cd18SRuud Derwig
222924cd18SRuud Derwig	cpu_card {
232924cd18SRuud Derwig		compatible = "simple-bus";
242924cd18SRuud Derwig		#address-cells = <1>;
252924cd18SRuud Derwig		#size-cells = <1>;
262924cd18SRuud Derwig
272924cd18SRuud Derwig		ranges = <0x00000000 0xf0000000 0x10000000>;
282924cd18SRuud Derwig
29*b3d6aba8SVineet Gupta		core_clk: core_clk {
30*b3d6aba8SVineet Gupta			#clock-cells = <0>;
31*b3d6aba8SVineet Gupta			compatible = "fixed-clock";
32*b3d6aba8SVineet Gupta			clock-frequency = <50000000>;
33*b3d6aba8SVineet Gupta		};
34*b3d6aba8SVineet Gupta
359ba7648cSVineet Gupta		core_intc: archs-intc@cpu {
362924cd18SRuud Derwig			compatible = "snps,archs-intc";
372924cd18SRuud Derwig			interrupt-controller;
382924cd18SRuud Derwig			#interrupt-cells = <1>;
392924cd18SRuud Derwig		};
402924cd18SRuud Derwig
412924cd18SRuud Derwig		idu_intc: idu-interrupt-controller {
422924cd18SRuud Derwig			compatible = "snps,archs-idu-intc";
432924cd18SRuud Derwig			interrupt-controller;
449ba7648cSVineet Gupta			interrupt-parent = <&core_intc>;
452924cd18SRuud Derwig
462924cd18SRuud Derwig			/*
472924cd18SRuud Derwig			 * <hwirq  distribution>
482924cd18SRuud Derwig			 * distribution: 0=RR; 1=cpu0, 2=cpu1, 4=cpu2, 8=cpu3
492924cd18SRuud Derwig			 */
502924cd18SRuud Derwig			#interrupt-cells = <2>;
512924cd18SRuud Derwig
522924cd18SRuud Derwig			interrupts = <24 25 26 27>;
532924cd18SRuud Derwig		};
542924cd18SRuud Derwig
552924cd18SRuud Derwig		debug_uart: dw-apb-uart@0x5000 {
562924cd18SRuud Derwig			compatible = "snps,dw-apb-uart";
572924cd18SRuud Derwig			reg = <0x5000 0x100>;
582924cd18SRuud Derwig			clock-frequency = <2403200>;
592924cd18SRuud Derwig			interrupt-parent = <&idu_intc>;
602924cd18SRuud Derwig			interrupts = <2 0>;
612924cd18SRuud Derwig			baud = <115200>;
622924cd18SRuud Derwig			reg-shift = <2>;
632924cd18SRuud Derwig			reg-io-width = <4>;
642924cd18SRuud Derwig		};
652924cd18SRuud Derwig
662924cd18SRuud Derwig	};
672924cd18SRuud Derwig
682924cd18SRuud Derwig	mb_intc: dw-apb-ictl@0xe0012000 {
692924cd18SRuud Derwig		#interrupt-cells = <1>;
702924cd18SRuud Derwig		compatible = "snps,dw-apb-ictl";
712924cd18SRuud Derwig		reg = < 0xe0012000 0x200 >;
722924cd18SRuud Derwig		interrupt-controller;
732924cd18SRuud Derwig		interrupt-parent = <&idu_intc>;
742924cd18SRuud Derwig		interrupts = < 0 0 >;
752924cd18SRuud Derwig	};
762924cd18SRuud Derwig
772924cd18SRuud Derwig	memory {
782924cd18SRuud Derwig		#address-cells = <1>;
792924cd18SRuud Derwig		#size-cells = <1>;
802924cd18SRuud Derwig		ranges = <0x00000000 0x80000000 0x40000000>;
812924cd18SRuud Derwig		device_type = "memory";
82f759ee57SVineet Gupta		reg = <0x80000000 0x20000000>;	/* 512MiB */
832924cd18SRuud Derwig	};
842924cd18SRuud Derwig};
85