1*2924cd18SRuud Derwig/* 2*2924cd18SRuud Derwig * Copyright (C) 2014, 2015 Synopsys, Inc. (www.synopsys.com) 3*2924cd18SRuud Derwig * 4*2924cd18SRuud Derwig * This program is free software; you can redistribute it and/or modify 5*2924cd18SRuud Derwig * it under the terms of the GNU General Public License version 2 as 6*2924cd18SRuud Derwig * published by the Free Software Foundation. 7*2924cd18SRuud Derwig */ 8*2924cd18SRuud Derwig 9*2924cd18SRuud Derwig/* 10*2924cd18SRuud Derwig * Device tree for AXC003 CPU card: 11*2924cd18SRuud Derwig * HS38x2 (Dual Core) with IDU intc (VDK version) 12*2924cd18SRuud Derwig */ 13*2924cd18SRuud Derwig 14*2924cd18SRuud Derwig/ { 15*2924cd18SRuud Derwig compatible = "snps,arc"; 16*2924cd18SRuud Derwig clock-frequency = <50000000>; 17*2924cd18SRuud Derwig #address-cells = <1>; 18*2924cd18SRuud Derwig #size-cells = <1>; 19*2924cd18SRuud Derwig 20*2924cd18SRuud Derwig cpu_card { 21*2924cd18SRuud Derwig compatible = "simple-bus"; 22*2924cd18SRuud Derwig #address-cells = <1>; 23*2924cd18SRuud Derwig #size-cells = <1>; 24*2924cd18SRuud Derwig 25*2924cd18SRuud Derwig ranges = <0x00000000 0xf0000000 0x10000000>; 26*2924cd18SRuud Derwig 27*2924cd18SRuud Derwig cpu_intc: archs-intc@cpu { 28*2924cd18SRuud Derwig compatible = "snps,archs-intc"; 29*2924cd18SRuud Derwig interrupt-controller; 30*2924cd18SRuud Derwig #interrupt-cells = <1>; 31*2924cd18SRuud Derwig }; 32*2924cd18SRuud Derwig 33*2924cd18SRuud Derwig idu_intc: idu-interrupt-controller { 34*2924cd18SRuud Derwig compatible = "snps,archs-idu-intc"; 35*2924cd18SRuud Derwig interrupt-controller; 36*2924cd18SRuud Derwig interrupt-parent = <&cpu_intc>; 37*2924cd18SRuud Derwig 38*2924cd18SRuud Derwig /* 39*2924cd18SRuud Derwig * <hwirq distribution> 40*2924cd18SRuud Derwig * distribution: 0=RR; 1=cpu0, 2=cpu1, 4=cpu2, 8=cpu3 41*2924cd18SRuud Derwig */ 42*2924cd18SRuud Derwig #interrupt-cells = <2>; 43*2924cd18SRuud Derwig 44*2924cd18SRuud Derwig interrupts = <24 25 26 27>; 45*2924cd18SRuud Derwig }; 46*2924cd18SRuud Derwig 47*2924cd18SRuud Derwig debug_uart: dw-apb-uart@0x5000 { 48*2924cd18SRuud Derwig compatible = "snps,dw-apb-uart"; 49*2924cd18SRuud Derwig reg = <0x5000 0x100>; 50*2924cd18SRuud Derwig clock-frequency = <2403200>; 51*2924cd18SRuud Derwig interrupt-parent = <&idu_intc>; 52*2924cd18SRuud Derwig interrupts = <2 0>; 53*2924cd18SRuud Derwig baud = <115200>; 54*2924cd18SRuud Derwig reg-shift = <2>; 55*2924cd18SRuud Derwig reg-io-width = <4>; 56*2924cd18SRuud Derwig }; 57*2924cd18SRuud Derwig 58*2924cd18SRuud Derwig }; 59*2924cd18SRuud Derwig 60*2924cd18SRuud Derwig mb_intc: dw-apb-ictl@0xe0012000 { 61*2924cd18SRuud Derwig #interrupt-cells = <1>; 62*2924cd18SRuud Derwig compatible = "snps,dw-apb-ictl"; 63*2924cd18SRuud Derwig reg = < 0xe0012000 0x200 >; 64*2924cd18SRuud Derwig interrupt-controller; 65*2924cd18SRuud Derwig interrupt-parent = <&idu_intc>; 66*2924cd18SRuud Derwig interrupts = < 0 0 >; 67*2924cd18SRuud Derwig }; 68*2924cd18SRuud Derwig 69*2924cd18SRuud Derwig memory { 70*2924cd18SRuud Derwig #address-cells = <1>; 71*2924cd18SRuud Derwig #size-cells = <1>; 72*2924cd18SRuud Derwig ranges = <0x00000000 0x80000000 0x40000000>; 73*2924cd18SRuud Derwig device_type = "memory"; 74*2924cd18SRuud Derwig reg = <0x00000000 0x20000000>; /* 512MiB */ 75*2924cd18SRuud Derwig }; 76*2924cd18SRuud Derwig}; 77