xref: /linux/arch/arc/boot/dts/skeleton_hs_idu.dtsi (revision 4ed10958ae461168be310b4bbee13f745e4c1547)
12e8cd938SVineet Gupta/*
22e8cd938SVineet Gupta * Copyright (C) 2016 Synopsys, Inc. (www.synopsys.com)
32e8cd938SVineet Gupta *
42e8cd938SVineet Gupta * This program is free software; you can redistribute it and/or modify
52e8cd938SVineet Gupta * it under the terms of the GNU General Public License version 2 as
62e8cd938SVineet Gupta * published by the Free Software Foundation.
72e8cd938SVineet Gupta */
82e8cd938SVineet Gupta
92e8cd938SVineet Gupta/ {
102e8cd938SVineet Gupta	compatible = "snps,arc";
112e8cd938SVineet Gupta	#address-cells = <1>;
122e8cd938SVineet Gupta	#size-cells = <1>;
132e8cd938SVineet Gupta	chosen { };
142e8cd938SVineet Gupta	aliases { };
152e8cd938SVineet Gupta
162e8cd938SVineet Gupta	cpus {
172e8cd938SVineet Gupta		#address-cells = <1>;
182e8cd938SVineet Gupta		#size-cells = <0>;
192e8cd938SVineet Gupta
202e8cd938SVineet Gupta		cpu@0 {
212e8cd938SVineet Gupta			device_type = "cpu";
22*4ed10958SVlad Zakharov			compatible = "snps,archs38";
232e8cd938SVineet Gupta			reg = <0>;
24854c11e2SVlad Zakharov			clocks = <&core_clk>;
252e8cd938SVineet Gupta		};
26*4ed10958SVlad Zakharov		cpu@1 {
27*4ed10958SVlad Zakharov			device_type = "cpu";
28*4ed10958SVlad Zakharov			compatible = "snps,archs38";
29*4ed10958SVlad Zakharov			reg = <1>;
30*4ed10958SVlad Zakharov			clocks = <&core_clk>;
31*4ed10958SVlad Zakharov		};
32*4ed10958SVlad Zakharov		cpu@2 {
33*4ed10958SVlad Zakharov			device_type = "cpu";
34*4ed10958SVlad Zakharov			compatible = "snps,archs38";
35*4ed10958SVlad Zakharov			reg = <2>;
36*4ed10958SVlad Zakharov			clocks = <&core_clk>;
37*4ed10958SVlad Zakharov		};
38*4ed10958SVlad Zakharov		cpu@3 {
39*4ed10958SVlad Zakharov			device_type = "cpu";
40*4ed10958SVlad Zakharov			compatible = "snps,archs38";
41*4ed10958SVlad Zakharov			reg = <3>;
42*4ed10958SVlad Zakharov			clocks = <&core_clk>;
43*4ed10958SVlad Zakharov		};
442e8cd938SVineet Gupta	};
452e8cd938SVineet Gupta
467ec9f34aSVineet Gupta	/* TIMER0 with interrupt for clockevent */
477ec9f34aSVineet Gupta	timer0 {
487ec9f34aSVineet Gupta		compatible = "snps,arc-timer";
497ec9f34aSVineet Gupta		interrupts = <16>;
507ec9f34aSVineet Gupta		interrupt-parent = <&core_intc>;
517ec9f34aSVineet Gupta		clocks = <&core_clk>;
527ec9f34aSVineet Gupta	};
537ec9f34aSVineet Gupta
547ec9f34aSVineet Gupta	/* 64-bit Global Free Running Counter */
557ec9f34aSVineet Gupta	gfrc {
567ec9f34aSVineet Gupta		compatible = "snps,archs-timer-gfrc";
577ec9f34aSVineet Gupta		clocks = <&core_clk>;
587ec9f34aSVineet Gupta	};
597ec9f34aSVineet Gupta
602e8cd938SVineet Gupta	memory {
612e8cd938SVineet Gupta		device_type = "memory";
622e8cd938SVineet Gupta		reg = <0x80000000 0x10000000>;	/* 256M */
632e8cd938SVineet Gupta	};
642e8cd938SVineet Gupta};
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