1/* 2 * Support for peripherals on the AXS10x mainboard 3 * 4 * Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com) 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11/ { 12 axs10x_mb { 13 compatible = "simple-bus"; 14 #address-cells = <1>; 15 #size-cells = <1>; 16 ranges = <0x00000000 0x0 0xe0000000 0x10000000>; 17 interrupt-parent = <&mb_intc>; 18 19 i2sclk: i2sclk@100a0 { 20 compatible = "snps,axs10x-i2s-pll-clock"; 21 reg = <0x100a0 0x10>; 22 clocks = <&i2spll_clk>; 23 #clock-cells = <0>; 24 }; 25 26 clocks { 27 i2spll_clk: i2spll_clk { 28 compatible = "fixed-clock"; 29 clock-frequency = <27000000>; 30 #clock-cells = <0>; 31 }; 32 33 i2cclk: i2cclk { 34 compatible = "fixed-clock"; 35 clock-frequency = <50000000>; 36 #clock-cells = <0>; 37 }; 38 39 apbclk: apbclk { 40 compatible = "fixed-clock"; 41 clock-frequency = <50000000>; 42 #clock-cells = <0>; 43 }; 44 45 mmcclk: mmcclk { 46 compatible = "fixed-clock"; 47 clock-frequency = <50000000>; 48 #clock-cells = <0>; 49 }; 50 51 pguclk: pguclk { 52 #clock-cells = <0>; 53 compatible = "fixed-clock"; 54 clock-frequency = <74250000>; 55 }; 56 }; 57 58 ethernet@0x18000 { 59 #interrupt-cells = <1>; 60 compatible = "snps,dwmac"; 61 reg = < 0x18000 0x2000 >; 62 interrupts = < 4 >; 63 interrupt-names = "macirq"; 64 phy-mode = "rgmii"; 65 snps,pbl = < 32 >; 66 clocks = <&apbclk>; 67 clock-names = "stmmaceth"; 68 max-speed = <100>; 69 }; 70 71 ehci@0x40000 { 72 compatible = "generic-ehci"; 73 reg = < 0x40000 0x100 >; 74 interrupts = < 8 >; 75 }; 76 77 ohci@0x60000 { 78 compatible = "generic-ohci"; 79 reg = < 0x60000 0x100 >; 80 interrupts = < 8 >; 81 }; 82 83 /* 84 * According to DW Mobile Storage databook it is required 85 * to use "Hold Register" if card is enumerated in SDR12 or 86 * SDR25 modes. 87 * 88 * Utilization of "Hold Register" is already implemented via 89 * dw_mci_pltfm_prepare_command() which in its turn gets 90 * used through dw_mci_drv_data->prepare_command call-back. 91 * This call-back is used in Altera Socfpga platform and so 92 * we may reuse it saying that we're compatible with their 93 * "altr,socfpga-dw-mshc". 94 * 95 * Most probably "Hold Register" utilization is platform- 96 * independent requirement which means that single unified 97 * "snps,dw-mshc" should be enough for all users of DW MMC once 98 * dw_mci_pltfm_prepare_command() is used in generic platform 99 * code. 100 */ 101 mmc@0x15000 { 102 compatible = "altr,socfpga-dw-mshc"; 103 reg = < 0x15000 0x400 >; 104 fifo-depth = < 16 >; 105 card-detect-delay = < 200 >; 106 clocks = <&apbclk>, <&mmcclk>; 107 clock-names = "biu", "ciu"; 108 interrupts = < 7 >; 109 bus-width = < 4 >; 110 }; 111 112 uart@0x20000 { 113 compatible = "snps,dw-apb-uart"; 114 reg = <0x20000 0x100>; 115 clock-frequency = <33333333>; 116 interrupts = <17>; 117 baud = <115200>; 118 reg-shift = <2>; 119 reg-io-width = <4>; 120 }; 121 122 uart@0x21000 { 123 compatible = "snps,dw-apb-uart"; 124 reg = <0x21000 0x100>; 125 clock-frequency = <33333333>; 126 interrupts = <18>; 127 baud = <115200>; 128 reg-shift = <2>; 129 reg-io-width = <4>; 130 }; 131 132 /* UART muxed with USB data port (ttyS3) */ 133 uart@0x22000 { 134 compatible = "snps,dw-apb-uart"; 135 reg = <0x22000 0x100>; 136 clock-frequency = <33333333>; 137 interrupts = <19>; 138 baud = <115200>; 139 reg-shift = <2>; 140 reg-io-width = <4>; 141 }; 142 143 i2c@0x1d000 { 144 compatible = "snps,designware-i2c"; 145 reg = <0x1d000 0x100>; 146 clock-frequency = <400000>; 147 clocks = <&i2cclk>; 148 interrupts = <14>; 149 }; 150 151 i2s: i2s@1e000 { 152 compatible = "snps,designware-i2s"; 153 reg = <0x1e000 0x100>; 154 clocks = <&i2sclk 0>; 155 clock-names = "i2sclk"; 156 interrupts = <15>; 157 #sound-dai-cells = <0>; 158 }; 159 160 i2c@0x1f000 { 161 compatible = "snps,designware-i2c"; 162 #address-cells = <1>; 163 #size-cells = <0>; 164 reg = <0x1f000 0x100>; 165 clock-frequency = <400000>; 166 clocks = <&i2cclk>; 167 interrupts = <16>; 168 169 adv7511:adv7511@39{ 170 compatible="adi,adv7511"; 171 reg = <0x39>; 172 interrupts = <23>; 173 adi,input-depth = <8>; 174 adi,input-colorspace = "rgb"; 175 adi,input-clock = "1x"; 176 adi,clock-delay = <0x03>; 177 #sound-dai-cells = <0>; 178 179 ports { 180 #address-cells = <1>; 181 #size-cells = <0>; 182 183 /* RGB/YUV input */ 184 port@0 { 185 reg = <0>; 186 adv7511_input:endpoint { 187 remote-endpoint = <&pgu_output>; 188 }; 189 }; 190 191 /* HDMI output */ 192 port@1 { 193 reg = <1>; 194 adv7511_output: endpoint { 195 remote-endpoint = <&hdmi_connector_in>; 196 }; 197 }; 198 }; 199 }; 200 201 eeprom@0x54{ 202 compatible = "24c01"; 203 reg = <0x54>; 204 pagesize = <0x8>; 205 }; 206 207 eeprom@0x57{ 208 compatible = "24c04"; 209 reg = <0x57>; 210 pagesize = <0x8>; 211 }; 212 }; 213 214 hdmi0: connector { 215 compatible = "hdmi-connector"; 216 type = "a"; 217 port { 218 hdmi_connector_in: endpoint { 219 remote-endpoint = <&adv7511_output>; 220 }; 221 }; 222 }; 223 224 gpio0:gpio@13000 { 225 compatible = "snps,dw-apb-gpio"; 226 reg = <0x13000 0x1000>; 227 #address-cells = <1>; 228 #size-cells = <0>; 229 230 gpio0_banka: gpio-controller@0 { 231 compatible = "snps,dw-apb-gpio-port"; 232 gpio-controller; 233 #gpio-cells = <2>; 234 snps,nr-gpios = <32>; 235 reg = <0>; 236 }; 237 238 gpio0_bankb: gpio-controller@1 { 239 compatible = "snps,dw-apb-gpio-port"; 240 gpio-controller; 241 #gpio-cells = <2>; 242 snps,nr-gpios = <8>; 243 reg = <1>; 244 }; 245 246 gpio0_bankc: gpio-controller@2 { 247 compatible = "snps,dw-apb-gpio-port"; 248 gpio-controller; 249 #gpio-cells = <2>; 250 snps,nr-gpios = <8>; 251 reg = <2>; 252 }; 253 }; 254 255 gpio1:gpio@14000 { 256 compatible = "snps,dw-apb-gpio"; 257 reg = <0x14000 0x1000>; 258 #address-cells = <1>; 259 #size-cells = <0>; 260 261 gpio1_banka: gpio-controller@0 { 262 compatible = "snps,dw-apb-gpio-port"; 263 gpio-controller; 264 #gpio-cells = <2>; 265 snps,nr-gpios = <30>; 266 reg = <0>; 267 }; 268 269 gpio1_bankb: gpio-controller@1 { 270 compatible = "snps,dw-apb-gpio-port"; 271 gpio-controller; 272 #gpio-cells = <2>; 273 snps,nr-gpios = <10>; 274 reg = <1>; 275 }; 276 277 gpio1_bankc: gpio-controller@2 { 278 compatible = "snps,dw-apb-gpio-port"; 279 gpio-controller; 280 #gpio-cells = <2>; 281 snps,nr-gpios = <8>; 282 reg = <2>; 283 }; 284 }; 285 286 pgu@17000 { 287 compatible = "snps,arcpgu"; 288 reg = <0x17000 0x400>; 289 encoder-slave = <&adv7511>; 290 clocks = <&pguclk>; 291 clock-names = "pxlclk"; 292 memory-region = <&frame_buffer>; 293 port { 294 pgu_output: endpoint { 295 remote-endpoint = <&adv7511_input>; 296 }; 297 }; 298 }; 299 300 sound_playback { 301 compatible = "simple-audio-card"; 302 simple-audio-card,name = "AXS10x HDMI Audio"; 303 simple-audio-card,format = "i2s"; 304 simple-audio-card,cpu { 305 sound-dai = <&i2s>; 306 }; 307 simple-audio-card,codec { 308 sound-dai = <&adv7511>; 309 }; 310 }; 311 }; 312}; 313