1/* 2 * Copyright (C) 2014, 2015 Synopsys, Inc. (www.synopsys.com) 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 */ 8 9/* 10 * Device tree for AXC003 CPU card: HS38x2 (Dual Core) with IDU intc 11 */ 12 13/include/ "skeleton_hs_idu.dtsi" 14 15/ { 16 compatible = "snps,arc"; 17 #address-cells = <1>; 18 #size-cells = <1>; 19 20 cpu_card { 21 compatible = "simple-bus"; 22 #address-cells = <1>; 23 #size-cells = <1>; 24 25 ranges = <0x00000000 0xf0000000 0x10000000>; 26 27 core_clk: core_clk { 28 #clock-cells = <0>; 29 compatible = "fixed-clock"; 30 clock-frequency = <100000000>; 31 }; 32 33 core_intc: archs-intc@cpu { 34 compatible = "snps,archs-intc"; 35 interrupt-controller; 36 #interrupt-cells = <1>; 37 }; 38 39 idu_intc: idu-interrupt-controller { 40 compatible = "snps,archs-idu-intc"; 41 interrupt-controller; 42 interrupt-parent = <&core_intc>; 43 #interrupt-cells = <1>; 44 }; 45 46 /* 47 * this GPIO block ORs all interrupts on CPU card (creg,..) 48 * to uplink only 1 IRQ to ARC core intc 49 */ 50 dw-apb-gpio@0x2000 { 51 compatible = "snps,dw-apb-gpio"; 52 reg = < 0x2000 0x80 >; 53 #address-cells = <1>; 54 #size-cells = <0>; 55 56 ictl_intc: gpio-controller@0 { 57 compatible = "snps,dw-apb-gpio-port"; 58 gpio-controller; 59 #gpio-cells = <2>; 60 snps,nr-gpios = <30>; 61 reg = <0>; 62 interrupt-controller; 63 #interrupt-cells = <2>; 64 interrupt-parent = <&idu_intc>; 65 interrupts = <1>; 66 }; 67 }; 68 69 debug_uart: dw-apb-uart@0x5000 { 70 compatible = "snps,dw-apb-uart"; 71 reg = <0x5000 0x100>; 72 clock-frequency = <33333000>; 73 interrupt-parent = <&ictl_intc>; 74 interrupts = <2 4>; 75 baud = <115200>; 76 reg-shift = <2>; 77 reg-io-width = <4>; 78 }; 79 80 arcpct0: pct { 81 compatible = "snps,archs-pct"; 82 #interrupt-cells = <1>; 83 interrupt-parent = <&core_intc>; 84 interrupts = <20>; 85 }; 86 }; 87 88 /* 89 * This INTC is actually connected to DW APB GPIO 90 * which acts as a wire between MB INTC and CPU INTC. 91 * GPIO INTC is configured in platform init code 92 * and here we mimic direct connection from MB INTC to 93 * CPU INTC, thus we set "interrupts = <0 1>" instead of 94 * "interrupts = <12>" 95 * 96 * This intc actually resides on MB, but we move it here to 97 * avoid duplicating the MB dtsi file given that IRQ from 98 * this intc to cpu intc are different for axs101 and axs103 99 */ 100 mb_intc: dw-apb-ictl@0xe0012000 { 101 #interrupt-cells = <1>; 102 compatible = "snps,dw-apb-ictl"; 103 reg = < 0xe0012000 0x200 >; 104 interrupt-controller; 105 interrupt-parent = <&idu_intc>; 106 interrupts = <0>; 107 }; 108 109 memory { 110 #address-cells = <1>; 111 #size-cells = <1>; 112 ranges = <0x00000000 0x80000000 0x40000000>; 113 device_type = "memory"; 114 reg = <0x80000000 0x20000000>; /* 512MiB */ 115 }; 116 117 reserved-memory { 118 #address-cells = <1>; 119 #size-cells = <1>; 120 ranges; 121 /* 122 * Move frame buffer out of IOC aperture (0x8z-0xAz). 123 */ 124 frame_buffer: frame_buffer@be000000 { 125 compatible = "shared-dma-pool"; 126 reg = <0xbe000000 0x2000000>; 127 no-map; 128 }; 129 }; 130}; 131