1/* 2 * Copyright (C) 2014, 2015 Synopsys, Inc. (www.synopsys.com) 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 */ 8 9/* 10 * Device tree for AXC003 CPU card: HS38x2 (Dual Core) with IDU intc 11 */ 12 13/include/ "skeleton_hs_idu.dtsi" 14 15/ { 16 compatible = "snps,arc"; 17 clock-frequency = <90000000>; 18 #address-cells = <1>; 19 #size-cells = <1>; 20 21 cpu_card { 22 compatible = "simple-bus"; 23 #address-cells = <1>; 24 #size-cells = <1>; 25 26 ranges = <0x00000000 0xf0000000 0x10000000>; 27 28 cpu_intc: archs-intc@cpu { 29 compatible = "snps,archs-intc"; 30 interrupt-controller; 31 #interrupt-cells = <1>; 32 }; 33 34 idu_intc: idu-interrupt-controller { 35 compatible = "snps,archs-idu-intc"; 36 interrupt-controller; 37 interrupt-parent = <&cpu_intc>; 38 39 /* 40 * <hwirq distribution> 41 * distribution: 0=RR; 1=cpu0, 2=cpu1, 4=cpu2, 8=cpu3 42 */ 43 #interrupt-cells = <2>; 44 45 /* 46 * upstream irqs to core intc - downstream these are 47 * "COMMON" irq 0,1.. 48 */ 49 interrupts = <24 25>; 50 }; 51 52 /* 53 * this GPIO block ORs all interrupts on CPU card (creg,..) 54 * to uplink only 1 IRQ to ARC core intc 55 */ 56 dw-apb-gpio@0x2000 { 57 compatible = "snps,dw-apb-gpio"; 58 reg = < 0x2000 0x80 >; 59 #address-cells = <1>; 60 #size-cells = <0>; 61 62 ictl_intc: gpio-controller@0 { 63 compatible = "snps,dw-apb-gpio-port"; 64 gpio-controller; 65 #gpio-cells = <2>; 66 snps,nr-gpios = <30>; 67 reg = <0>; 68 interrupt-controller; 69 #interrupt-cells = <2>; 70 interrupt-parent = <&idu_intc>; 71 72 /* 73 * cmn irq 1 -> cpu irq 25 74 * Distribute to cpu0 only 75 */ 76 interrupts = <1 1>; 77 }; 78 }; 79 80 debug_uart: dw-apb-uart@0x5000 { 81 compatible = "snps,dw-apb-uart"; 82 reg = <0x5000 0x100>; 83 clock-frequency = <33333000>; 84 interrupt-parent = <&ictl_intc>; 85 interrupts = <2 4>; 86 baud = <115200>; 87 reg-shift = <2>; 88 reg-io-width = <4>; 89 }; 90 91 arcpct0: pct { 92 compatible = "snps,archs-pct"; 93 #interrupt-cells = <1>; 94 interrupt-parent = <&cpu_intc>; 95 interrupts = <20>; 96 }; 97 }; 98 99 /* 100 * This INTC is actually connected to DW APB GPIO 101 * which acts as a wire between MB INTC and CPU INTC. 102 * GPIO INTC is configured in platform init code 103 * and here we mimic direct connection from MB INTC to 104 * CPU INTC, thus we set "interrupts = <0 1>" instead of 105 * "interrupts = <12>" 106 * 107 * This intc actually resides on MB, but we move it here to 108 * avoid duplicating the MB dtsi file given that IRQ from 109 * this intc to cpu intc are different for axs101 and axs103 110 */ 111 mb_intc: dw-apb-ictl@0xe0012000 { 112 #interrupt-cells = <1>; 113 compatible = "snps,dw-apb-ictl"; 114 reg = < 0xe0012000 0x200 >; 115 interrupt-controller; 116 interrupt-parent = <&idu_intc>; 117 interrupts = <0 1>; /* cmn irq 0 -> cpu irq 24 118 distribute to cpu0 only */ 119 }; 120 121 memory { 122 #address-cells = <1>; 123 #size-cells = <1>; 124 ranges = <0x00000000 0x80000000 0x40000000>; 125 device_type = "memory"; 126 reg = <0x80000000 0x20000000>; /* 512MiB */ 127 }; 128}; 129