15fa2daaaSVineet Gupta/* 25fa2daaaSVineet Gupta * Copyright (C) 2014, 2015 Synopsys, Inc. (www.synopsys.com) 35fa2daaaSVineet Gupta * 45fa2daaaSVineet Gupta * This program is free software; you can redistribute it and/or modify 55fa2daaaSVineet Gupta * it under the terms of the GNU General Public License version 2 as 65fa2daaaSVineet Gupta * published by the Free Software Foundation. 75fa2daaaSVineet Gupta */ 85fa2daaaSVineet Gupta 95fa2daaaSVineet Gupta/* 105fa2daaaSVineet Gupta * Device tree for AXC003 CPU card: HS38x2 (Dual Core) with IDU intc 115fa2daaaSVineet Gupta */ 125fa2daaaSVineet Gupta 132e8cd938SVineet Gupta/include/ "skeleton_hs_idu.dtsi" 142e8cd938SVineet Gupta 155fa2daaaSVineet Gupta/ { 165fa2daaaSVineet Gupta compatible = "snps,arc"; 17f862b315SEugeniy Paltsev #address-cells = <2>; 18f862b315SEugeniy Paltsev #size-cells = <2>; 195fa2daaaSVineet Gupta 205fa2daaaSVineet Gupta cpu_card { 215fa2daaaSVineet Gupta compatible = "simple-bus"; 225fa2daaaSVineet Gupta #address-cells = <1>; 235fa2daaaSVineet Gupta #size-cells = <1>; 245fa2daaaSVineet Gupta 25f862b315SEugeniy Paltsev ranges = <0x00000000 0x0 0xf0000000 0x10000000>; 265fa2daaaSVineet Gupta 27f6a09bacSEugeniy Paltsev input_clk: input-clk { 28b3d6aba8SVineet Gupta #clock-cells = <0>; 29b3d6aba8SVineet Gupta compatible = "fixed-clock"; 30f6a09bacSEugeniy Paltsev clock-frequency = <33333333>; 31f6a09bacSEugeniy Paltsev }; 32f6a09bacSEugeniy Paltsev 33f6a09bacSEugeniy Paltsev core_clk: core-clk@80 { 34f6a09bacSEugeniy Paltsev compatible = "snps,axs10x-arc-pll-clock"; 35f6a09bacSEugeniy Paltsev reg = <0x80 0x10>, <0x100 0x10>; 36f6a09bacSEugeniy Paltsev #clock-cells = <0>; 37f6a09bacSEugeniy Paltsev clocks = <&input_clk>; 38*fbd1cec5SEugeniy Paltsev 39*fbd1cec5SEugeniy Paltsev /* 40*fbd1cec5SEugeniy Paltsev * Set initial core pll output frequency to 100MHz. 41*fbd1cec5SEugeniy Paltsev * It will be applied at the core pll driver probing 42*fbd1cec5SEugeniy Paltsev * on early boot. 43*fbd1cec5SEugeniy Paltsev */ 44*fbd1cec5SEugeniy Paltsev assigned-clocks = <&core_clk>; 45*fbd1cec5SEugeniy Paltsev assigned-clock-rates = <100000000>; 46b3d6aba8SVineet Gupta }; 47b3d6aba8SVineet Gupta 489ba7648cSVineet Gupta core_intc: archs-intc@cpu { 495fa2daaaSVineet Gupta compatible = "snps,archs-intc"; 505fa2daaaSVineet Gupta interrupt-controller; 515fa2daaaSVineet Gupta #interrupt-cells = <1>; 525fa2daaaSVineet Gupta }; 535fa2daaaSVineet Gupta 545fa2daaaSVineet Gupta idu_intc: idu-interrupt-controller { 555fa2daaaSVineet Gupta compatible = "snps,archs-idu-intc"; 565fa2daaaSVineet Gupta interrupt-controller; 579ba7648cSVineet Gupta interrupt-parent = <&core_intc>; 58ec69b269SYuriy Kolerov #interrupt-cells = <1>; 595fa2daaaSVineet Gupta }; 605fa2daaaSVineet Gupta 615fa2daaaSVineet Gupta /* 625fa2daaaSVineet Gupta * this GPIO block ORs all interrupts on CPU card (creg,..) 635fa2daaaSVineet Gupta * to uplink only 1 IRQ to ARC core intc 645fa2daaaSVineet Gupta */ 655fa2daaaSVineet Gupta dw-apb-gpio@0x2000 { 665fa2daaaSVineet Gupta compatible = "snps,dw-apb-gpio"; 675fa2daaaSVineet Gupta reg = < 0x2000 0x80 >; 685fa2daaaSVineet Gupta #address-cells = <1>; 695fa2daaaSVineet Gupta #size-cells = <0>; 705fa2daaaSVineet Gupta 715fa2daaaSVineet Gupta ictl_intc: gpio-controller@0 { 725fa2daaaSVineet Gupta compatible = "snps,dw-apb-gpio-port"; 735fa2daaaSVineet Gupta gpio-controller; 745fa2daaaSVineet Gupta #gpio-cells = <2>; 755fa2daaaSVineet Gupta snps,nr-gpios = <30>; 765fa2daaaSVineet Gupta reg = <0>; 775fa2daaaSVineet Gupta interrupt-controller; 785fa2daaaSVineet Gupta #interrupt-cells = <2>; 795fa2daaaSVineet Gupta interrupt-parent = <&idu_intc>; 80ec69b269SYuriy Kolerov interrupts = <1>; 815fa2daaaSVineet Gupta }; 825fa2daaaSVineet Gupta }; 835fa2daaaSVineet Gupta 845fa2daaaSVineet Gupta debug_uart: dw-apb-uart@0x5000 { 855fa2daaaSVineet Gupta compatible = "snps,dw-apb-uart"; 865fa2daaaSVineet Gupta reg = <0x5000 0x100>; 875fa2daaaSVineet Gupta clock-frequency = <33333000>; 885fa2daaaSVineet Gupta interrupt-parent = <&ictl_intc>; 895fa2daaaSVineet Gupta interrupts = <2 4>; 905fa2daaaSVineet Gupta baud = <115200>; 915fa2daaaSVineet Gupta reg-shift = <2>; 925fa2daaaSVineet Gupta reg-io-width = <4>; 935fa2daaaSVineet Gupta }; 945fa2daaaSVineet Gupta 955fa2daaaSVineet Gupta arcpct0: pct { 965fa2daaaSVineet Gupta compatible = "snps,archs-pct"; 975fa2daaaSVineet Gupta #interrupt-cells = <1>; 989ba7648cSVineet Gupta interrupt-parent = <&core_intc>; 995fa2daaaSVineet Gupta interrupts = <20>; 1005fa2daaaSVineet Gupta }; 1015fa2daaaSVineet Gupta }; 1025fa2daaaSVineet Gupta 1035fa2daaaSVineet Gupta /* 1045fa2daaaSVineet Gupta * This INTC is actually connected to DW APB GPIO 1055fa2daaaSVineet Gupta * which acts as a wire between MB INTC and CPU INTC. 1065fa2daaaSVineet Gupta * GPIO INTC is configured in platform init code 1075fa2daaaSVineet Gupta * and here we mimic direct connection from MB INTC to 1085fa2daaaSVineet Gupta * CPU INTC, thus we set "interrupts = <0 1>" instead of 1095fa2daaaSVineet Gupta * "interrupts = <12>" 1105fa2daaaSVineet Gupta * 1115fa2daaaSVineet Gupta * This intc actually resides on MB, but we move it here to 1125fa2daaaSVineet Gupta * avoid duplicating the MB dtsi file given that IRQ from 1135fa2daaaSVineet Gupta * this intc to cpu intc are different for axs101 and axs103 1145fa2daaaSVineet Gupta */ 1155fa2daaaSVineet Gupta mb_intc: dw-apb-ictl@0xe0012000 { 1165fa2daaaSVineet Gupta #interrupt-cells = <1>; 1175fa2daaaSVineet Gupta compatible = "snps,dw-apb-ictl"; 118f862b315SEugeniy Paltsev reg = < 0x0 0xe0012000 0x0 0x200 >; 1195fa2daaaSVineet Gupta interrupt-controller; 1205fa2daaaSVineet Gupta interrupt-parent = <&idu_intc>; 121ec69b269SYuriy Kolerov interrupts = <0>; 1225fa2daaaSVineet Gupta }; 1235fa2daaaSVineet Gupta 1245fa2daaaSVineet Gupta memory { 1255fa2daaaSVineet Gupta device_type = "memory"; 1269ed68785SEugeniy Paltsev /* CONFIG_LINUX_RAM_BASE needs to match low mem start */ 127f862b315SEugeniy Paltsev reg = <0x0 0x80000000 0x0 0x20000000 /* 512 MiB low mem */ 128f862b315SEugeniy Paltsev 0x1 0xc0000000 0x0 0x40000000>; /* 1 GiB highmem */ 1295fa2daaaSVineet Gupta }; 130cb2ad5e5SAlexey Brodkin 131cb2ad5e5SAlexey Brodkin reserved-memory { 132f862b315SEugeniy Paltsev #address-cells = <2>; 133f862b315SEugeniy Paltsev #size-cells = <2>; 134cb2ad5e5SAlexey Brodkin ranges; 135cb2ad5e5SAlexey Brodkin /* 136cb2ad5e5SAlexey Brodkin * Move frame buffer out of IOC aperture (0x8z-0xAz). 137cb2ad5e5SAlexey Brodkin */ 138cb2ad5e5SAlexey Brodkin frame_buffer: frame_buffer@be000000 { 139cb2ad5e5SAlexey Brodkin compatible = "shared-dma-pool"; 140f862b315SEugeniy Paltsev reg = <0x0 0xbe000000 0x0 0x2000000>; 141cb2ad5e5SAlexey Brodkin no-map; 142cb2ad5e5SAlexey Brodkin }; 143cb2ad5e5SAlexey Brodkin }; 1445fa2daaaSVineet Gupta}; 145