1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Abilis Systems TB10X SOC device tree 4 * 5 * Copyright (C) Abilis Systems 2013 6 * 7 * Author: Christian Ruppert <christian.ruppert@abilis.com> 8 */ 9 10 11/ { 12 compatible = "abilis,arc-tb10x"; 13 #address-cells = <1>; 14 #size-cells = <1>; 15 16 cpus { 17 #address-cells = <1>; 18 #size-cells = <0>; 19 cpu@0 { 20 device_type = "cpu"; 21 compatible = "snps,arc770d"; 22 reg = <0>; 23 }; 24 }; 25 26 /* TIMER0 with interrupt for clockevent */ 27 timer0 { 28 compatible = "snps,arc-timer"; 29 interrupts = <3>; 30 interrupt-parent = <&intc>; 31 clocks = <&cpu_clk>; 32 }; 33 34 /* TIMER1 for free running clocksource */ 35 timer1 { 36 compatible = "snps,arc-timer"; 37 clocks = <&cpu_clk>; 38 }; 39 40 soc100 { 41 #address-cells = <1>; 42 #size-cells = <1>; 43 device_type = "soc"; 44 ranges = <0xfe000000 0xfe000000 0x02000000 45 0x000f0000 0x000f0000 0x00010000>; 46 compatible = "abilis,tb10x", "simple-bus"; 47 48 pll0: oscillator { 49 compatible = "fixed-clock"; 50 #clock-cells = <0>; 51 clock-output-names = "pll0"; 52 }; 53 cpu_clk: clkdiv_cpu { 54 compatible = "fixed-factor-clock"; 55 #clock-cells = <0>; 56 clocks = <&pll0>; 57 clock-output-names = "cpu_clk"; 58 }; 59 ahb_clk: clkdiv_ahb { 60 compatible = "fixed-factor-clock"; 61 #clock-cells = <0>; 62 clocks = <&pll0>; 63 clock-output-names = "ahb_clk"; 64 }; 65 66 iomux: iomux@ff10601c { 67 compatible = "abilis,tb10x-iomux"; 68 #gpio-range-cells = <3>; 69 reg = <0xff10601c 0x4>; 70 }; 71 72 intc: interrupt-controller { 73 compatible = "snps,arc700-intc"; 74 interrupt-controller; 75 #interrupt-cells = <1>; 76 }; 77 tb10x_ictl: pic@fe002000 { 78 compatible = "abilis,tb10x-ictl"; 79 reg = <0xfe002000 0x20>; 80 interrupt-controller; 81 #interrupt-cells = <2>; 82 interrupt-parent = <&intc>; 83 interrupts = <5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 84 20 21 22 23 24 25 26 27 28 29 30 31>; 85 }; 86 87 uart@ff100000 { 88 compatible = "snps,dw-apb-uart"; 89 reg = <0xff100000 0x100>; 90 clock-frequency = <166666666>; 91 interrupts = <25 8>; 92 reg-shift = <2>; 93 reg-io-width = <4>; 94 interrupt-parent = <&tb10x_ictl>; 95 }; 96 ethernet@fe100000 { 97 compatible = "snps,dwmac-3.70a","snps,dwmac"; 98 reg = <0xfe100000 0x1058>; 99 interrupt-parent = <&tb10x_ictl>; 100 interrupts = <6 8>; 101 interrupt-names = "macirq"; 102 clocks = <&ahb_clk>; 103 clock-names = "stmmaceth"; 104 }; 105 dma@fe000000 { 106 compatible = "snps,dma-spear1340"; 107 reg = <0xfe000000 0x400>; 108 interrupt-parent = <&tb10x_ictl>; 109 interrupts = <14 8>; 110 dma-channels = <6>; 111 dma-requests = <0>; 112 dma-masters = <1>; 113 #dma-cells = <3>; 114 chan_allocation_order = <0>; 115 chan_priority = <1>; 116 block_size = <0x7ff>; 117 data-width = <4>; 118 clocks = <&ahb_clk>; 119 clock-names = "hclk"; 120 multi-block = <1 1 1 1 1 1>; 121 }; 122 123 i2c0: i2c@ff120000 { 124 #address-cells = <1>; 125 #size-cells = <0>; 126 compatible = "snps,designware-i2c"; 127 reg = <0xff120000 0x1000>; 128 interrupt-parent = <&tb10x_ictl>; 129 interrupts = <12 8>; 130 clocks = <&ahb_clk>; 131 }; 132 i2c1: i2c@ff121000 { 133 #address-cells = <1>; 134 #size-cells = <0>; 135 compatible = "snps,designware-i2c"; 136 reg = <0xff121000 0x1000>; 137 interrupt-parent = <&tb10x_ictl>; 138 interrupts = <12 8>; 139 clocks = <&ahb_clk>; 140 }; 141 i2c2: i2c@ff122000 { 142 #address-cells = <1>; 143 #size-cells = <0>; 144 compatible = "snps,designware-i2c"; 145 reg = <0xff122000 0x1000>; 146 interrupt-parent = <&tb10x_ictl>; 147 interrupts = <12 8>; 148 clocks = <&ahb_clk>; 149 }; 150 i2c3: i2c@ff123000 { 151 #address-cells = <1>; 152 #size-cells = <0>; 153 compatible = "snps,designware-i2c"; 154 reg = <0xff123000 0x1000>; 155 interrupt-parent = <&tb10x_ictl>; 156 interrupts = <12 8>; 157 clocks = <&ahb_clk>; 158 }; 159 i2c4: i2c@ff124000 { 160 #address-cells = <1>; 161 #size-cells = <0>; 162 compatible = "snps,designware-i2c"; 163 reg = <0xff124000 0x1000>; 164 interrupt-parent = <&tb10x_ictl>; 165 interrupts = <12 8>; 166 clocks = <&ahb_clk>; 167 }; 168 169 spi0: spi@fe010000 { 170 #address-cells = <1>; 171 #size-cells = <0>; 172 cell-index = <0>; 173 compatible = "abilis,tb100-spi"; 174 num-cs = <1>; 175 reg = <0xfe010000 0x20>; 176 interrupt-parent = <&tb10x_ictl>; 177 interrupts = <26 8>; 178 clocks = <&ahb_clk>; 179 }; 180 spi1: spi@fe011000 { 181 #address-cells = <1>; 182 #size-cells = <0>; 183 cell-index = <1>; 184 compatible = "abilis,tb100-spi"; 185 num-cs = <2>; 186 reg = <0xfe011000 0x20>; 187 interrupt-parent = <&tb10x_ictl>; 188 interrupts = <10 8>; 189 clocks = <&ahb_clk>; 190 }; 191 192 tb10x_tsm: tb10x-tsm@ff316000 { 193 compatible = "abilis,tb100-tsm"; 194 reg = <0xff316000 0x400>; 195 interrupt-parent = <&tb10x_ictl>; 196 interrupts = <17 8>; 197 output-clkdiv = <4>; 198 global-packet-delay = <0x21>; 199 port-packet-delay = <0>; 200 }; 201 tb10x_stream_proc: tb10x-stream-proc { 202 compatible = "abilis,tb100-streamproc"; 203 reg = <0xfff00000 0x200>, 204 <0x000f0000 0x10000>, 205 <0xfff00200 0x105>, 206 <0xff10600c 0x1>, 207 <0xfe001018 0x1>; 208 reg-names = "mbox", 209 "sp_iccm", 210 "mbox_irq", 211 "cpuctrl", 212 "a6it_int_force"; 213 interrupt-parent = <&tb10x_ictl>; 214 interrupts = <20 2>, <19 2>; 215 interrupt-names = "cmd_irq", "event_irq"; 216 }; 217 tb10x_mdsc0: tb10x-mdscr@ff300000 { 218 compatible = "abilis,tb100-mdscr"; 219 reg = <0xff300000 0x7000>; 220 tb100-mdscr-manage-tsin; 221 }; 222 tb10x_mscr0: tb10x-mdscr@ff307000 { 223 compatible = "abilis,tb100-mdscr"; 224 reg = <0xff307000 0x7000>; 225 }; 226 tb10x_scr0: tb10x-mdscr@ff30e000 { 227 compatible = "abilis,tb100-mdscr"; 228 reg = <0xff30e000 0x4000>; 229 tb100-mdscr-manage-tsin; 230 }; 231 tb10x_scr1: tb10x-mdscr@ff312000 { 232 compatible = "abilis,tb100-mdscr"; 233 reg = <0xff312000 0x4000>; 234 tb100-mdscr-manage-tsin; 235 }; 236 tb10x_wfb: tb10x-wfb@ff319000 { 237 compatible = "abilis,tb100-wfb"; 238 reg = <0xff319000 0x1000>; 239 interrupt-parent = <&tb10x_ictl>; 240 interrupts = <16 8>; 241 }; 242 }; 243}; 244