1# 2# Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com) 3# 4# This program is free software; you can redistribute it and/or modify 5# it under the terms of the GNU General Public License version 2 as 6# published by the Free Software Foundation. 7# 8 9config ARC 10 def_bool y 11 select ARC_TIMERS 12 select ARCH_HAS_SYNC_DMA_FOR_CPU 13 select ARCH_HAS_SYNC_DMA_FOR_DEVICE 14 select ARCH_HAS_SG_CHAIN 15 select ARCH_SUPPORTS_ATOMIC_RMW if ARC_HAS_LLSC 16 select BUILDTIME_EXTABLE_SORT 17 select CLONE_BACKWARDS 18 select COMMON_CLK 19 select DMA_NONCOHERENT_OPS 20 select DMA_NONCOHERENT_MMAP 21 select GENERIC_ATOMIC64 if !ISA_ARCV2 || !(ARC_HAS_LL64 && ARC_HAS_LLSC) 22 select GENERIC_CLOCKEVENTS 23 select GENERIC_FIND_FIRST_BIT 24 # for now, we don't need GENERIC_IRQ_PROBE, CONFIG_GENERIC_IRQ_CHIP 25 select GENERIC_IRQ_SHOW 26 select GENERIC_PCI_IOMAP 27 select GENERIC_PENDING_IRQ if SMP 28 select GENERIC_SMP_IDLE_THREAD 29 select HAVE_ARCH_KGDB 30 select HAVE_ARCH_TRACEHOOK 31 select HAVE_FUTEX_CMPXCHG if FUTEX 32 select HAVE_IOREMAP_PROT 33 select HAVE_KPROBES 34 select HAVE_KRETPROBES 35 select HAVE_MEMBLOCK 36 select HAVE_MOD_ARCH_SPECIFIC 37 select HAVE_OPROFILE 38 select HAVE_PERF_EVENTS 39 select HANDLE_DOMAIN_IRQ 40 select IRQ_DOMAIN 41 select MODULES_USE_ELF_RELA 42 select NO_BOOTMEM 43 select OF 44 select OF_EARLY_FLATTREE 45 select OF_RESERVED_MEM 46 select PERF_USE_VMALLOC if ARC_CACHE_VIPT_ALIASING 47 select HAVE_DEBUG_STACKOVERFLOW 48 select HAVE_GENERIC_DMA_COHERENT 49 select HAVE_KERNEL_GZIP 50 select HAVE_KERNEL_LZMA 51 select ARCH_HAS_PTE_SPECIAL 52 53config ARCH_HAS_CACHE_LINE_SIZE 54 def_bool y 55 56config MIGHT_HAVE_PCI 57 bool 58 59config TRACE_IRQFLAGS_SUPPORT 60 def_bool y 61 62config LOCKDEP_SUPPORT 63 def_bool y 64 65config SCHED_OMIT_FRAME_POINTER 66 def_bool y 67 68config GENERIC_CSUM 69 def_bool y 70 71config RWSEM_GENERIC_SPINLOCK 72 def_bool y 73 74config ARCH_DISCONTIGMEM_ENABLE 75 def_bool n 76 77config ARCH_FLATMEM_ENABLE 78 def_bool y 79 80config MMU 81 def_bool y 82 83config NO_IOPORT_MAP 84 def_bool y 85 86config GENERIC_CALIBRATE_DELAY 87 def_bool y 88 89config GENERIC_HWEIGHT 90 def_bool y 91 92config STACKTRACE_SUPPORT 93 def_bool y 94 select STACKTRACE 95 96config HAVE_ARCH_TRANSPARENT_HUGEPAGE 97 def_bool y 98 depends on ARC_MMU_V4 99 100source "init/Kconfig" 101source "kernel/Kconfig.freezer" 102 103menu "ARC Architecture Configuration" 104 105menu "ARC Platform/SoC/Board" 106 107source "arch/arc/plat-tb10x/Kconfig" 108source "arch/arc/plat-axs10x/Kconfig" 109#New platform adds here 110source "arch/arc/plat-eznps/Kconfig" 111source "arch/arc/plat-hsdk/Kconfig" 112 113endmenu 114 115choice 116 prompt "ARC Instruction Set" 117 default ISA_ARCOMPACT 118 119config ISA_ARCOMPACT 120 bool "ARCompact ISA" 121 select CPU_NO_EFFICIENT_FFS 122 help 123 The original ARC ISA of ARC600/700 cores 124 125config ISA_ARCV2 126 bool "ARC ISA v2" 127 select ARC_TIMERS_64BIT 128 help 129 ISA for the Next Generation ARC-HS cores 130 131endchoice 132 133menu "ARC CPU Configuration" 134 135choice 136 prompt "ARC Core" 137 default ARC_CPU_770 if ISA_ARCOMPACT 138 default ARC_CPU_HS if ISA_ARCV2 139 140if ISA_ARCOMPACT 141 142config ARC_CPU_750D 143 bool "ARC750D" 144 select ARC_CANT_LLSC 145 help 146 Support for ARC750 core 147 148config ARC_CPU_770 149 bool "ARC770" 150 select ARC_HAS_SWAPE 151 help 152 Support for ARC770 core introduced with Rel 4.10 (Summer 2011) 153 This core has a bunch of cool new features: 154 -MMU-v3: Variable Page Sz (4k, 8k, 16k), bigger J-TLB (128x4) 155 Shared Address Spaces (for sharing TLB entires in MMU) 156 -Caches: New Prog Model, Region Flush 157 -Insns: endian swap, load-locked/store-conditional, time-stamp-ctr 158 159endif #ISA_ARCOMPACT 160 161config ARC_CPU_HS 162 bool "ARC-HS" 163 depends on ISA_ARCV2 164 help 165 Support for ARC HS38x Cores based on ARCv2 ISA 166 The notable features are: 167 - SMP configurations of upto 4 core with coherency 168 - Optional L2 Cache and IO-Coherency 169 - Revised Interrupt Architecture (multiple priorites, reg banks, 170 auto stack switch, auto regfile save/restore) 171 - MMUv4 (PIPT dcache, Huge Pages) 172 - Instructions for 173 * 64bit load/store: LDD, STD 174 * Hardware assisted divide/remainder: DIV, REM 175 * Function prologue/epilogue: ENTER_S, LEAVE_S 176 * IRQ enable/disable: CLRI, SETI 177 * pop count: FFS, FLS 178 * SETcc, BMSKN, XBFU... 179 180endchoice 181 182config CPU_BIG_ENDIAN 183 bool "Enable Big Endian Mode" 184 default n 185 help 186 Build kernel for Big Endian Mode of ARC CPU 187 188config SMP 189 bool "Symmetric Multi-Processing" 190 default n 191 select ARC_MCIP if ISA_ARCV2 192 help 193 This enables support for systems with more than one CPU. 194 195if SMP 196 197config NR_CPUS 198 int "Maximum number of CPUs (2-4096)" 199 range 2 4096 200 default "4" 201 202config ARC_SMP_HALT_ON_RESET 203 bool "Enable Halt-on-reset boot mode" 204 default y if ARC_UBOOT_SUPPORT 205 help 206 In SMP configuration cores can be configured as Halt-on-reset 207 or they could all start at same time. For Halt-on-reset, non 208 masters are parked until Master kicks them so they can start of 209 at designated entry point. For other case, all jump to common 210 entry point and spin wait for Master's signal. 211 212endif #SMP 213 214config ARC_MCIP 215 bool "ARConnect Multicore IP (MCIP) Support " 216 depends on ISA_ARCV2 217 default y if SMP 218 help 219 This IP block enables SMP in ARC-HS38 cores. 220 It provides for cross-core interrupts, multi-core debug 221 hardware semaphores, shared memory,.... 222 223menuconfig ARC_CACHE 224 bool "Enable Cache Support" 225 default y 226 227if ARC_CACHE 228 229config ARC_CACHE_LINE_SHIFT 230 int "Cache Line Length (as power of 2)" 231 range 5 7 232 default "6" 233 help 234 Starting with ARC700 4.9, Cache line length is configurable, 235 This option specifies "N", with Line-len = 2 power N 236 So line lengths of 32, 64, 128 are specified by 5,6,7, respectively 237 Linux only supports same line lengths for I and D caches. 238 239config ARC_HAS_ICACHE 240 bool "Use Instruction Cache" 241 default y 242 243config ARC_HAS_DCACHE 244 bool "Use Data Cache" 245 default y 246 247config ARC_CACHE_PAGES 248 bool "Per Page Cache Control" 249 default y 250 depends on ARC_HAS_ICACHE || ARC_HAS_DCACHE 251 help 252 This can be used to over-ride the global I/D Cache Enable on a 253 per-page basis (but only for pages accessed via MMU such as 254 Kernel Virtual address or User Virtual Address) 255 TLB entries have a per-page Cache Enable Bit. 256 Note that Global I/D ENABLE + Per Page DISABLE works but corollary 257 Global DISABLE + Per Page ENABLE won't work 258 259config ARC_CACHE_VIPT_ALIASING 260 bool "Support VIPT Aliasing D$" 261 depends on ARC_HAS_DCACHE && ISA_ARCOMPACT 262 default n 263 264endif #ARC_CACHE 265 266config ARC_HAS_ICCM 267 bool "Use ICCM" 268 help 269 Single Cycle RAMS to store Fast Path Code 270 default n 271 272config ARC_ICCM_SZ 273 int "ICCM Size in KB" 274 default "64" 275 depends on ARC_HAS_ICCM 276 277config ARC_HAS_DCCM 278 bool "Use DCCM" 279 help 280 Single Cycle RAMS to store Fast Path Data 281 default n 282 283config ARC_DCCM_SZ 284 int "DCCM Size in KB" 285 default "64" 286 depends on ARC_HAS_DCCM 287 288config ARC_DCCM_BASE 289 hex "DCCM map address" 290 default "0xA0000000" 291 depends on ARC_HAS_DCCM 292 293choice 294 prompt "MMU Version" 295 default ARC_MMU_V3 if ARC_CPU_770 296 default ARC_MMU_V2 if ARC_CPU_750D 297 default ARC_MMU_V4 if ARC_CPU_HS 298 299if ISA_ARCOMPACT 300 301config ARC_MMU_V1 302 bool "MMU v1" 303 help 304 Orig ARC700 MMU 305 306config ARC_MMU_V2 307 bool "MMU v2" 308 help 309 Fixed the deficiency of v1 - possible thrashing in memcpy scenario 310 when 2 D-TLB and 1 I-TLB entries index into same 2way set. 311 312config ARC_MMU_V3 313 bool "MMU v3" 314 depends on ARC_CPU_770 315 help 316 Introduced with ARC700 4.10: New Features 317 Variable Page size (1k-16k), var JTLB size 128 x (2 or 4) 318 Shared Address Spaces (SASID) 319 320endif 321 322config ARC_MMU_V4 323 bool "MMU v4" 324 depends on ISA_ARCV2 325 326endchoice 327 328 329choice 330 prompt "MMU Page Size" 331 default ARC_PAGE_SIZE_8K 332 333config ARC_PAGE_SIZE_8K 334 bool "8KB" 335 help 336 Choose between 8k vs 16k 337 338config ARC_PAGE_SIZE_16K 339 bool "16KB" 340 depends on ARC_MMU_V3 || ARC_MMU_V4 341 342config ARC_PAGE_SIZE_4K 343 bool "4KB" 344 depends on ARC_MMU_V3 || ARC_MMU_V4 345 346endchoice 347 348choice 349 prompt "MMU Super Page Size" 350 depends on ISA_ARCV2 && TRANSPARENT_HUGEPAGE 351 default ARC_HUGEPAGE_2M 352 353config ARC_HUGEPAGE_2M 354 bool "2MB" 355 356config ARC_HUGEPAGE_16M 357 bool "16MB" 358 359endchoice 360 361config NODES_SHIFT 362 int "Maximum NUMA Nodes (as a power of 2)" 363 default "0" if !DISCONTIGMEM 364 default "1" if DISCONTIGMEM 365 depends on NEED_MULTIPLE_NODES 366 ---help--- 367 Accessing memory beyond 1GB (with or w/o PAE) requires 2 memory 368 zones. 369 370if ISA_ARCOMPACT 371 372config ARC_COMPACT_IRQ_LEVELS 373 bool "Setup Timer IRQ as high Priority" 374 default n 375 # if SMP, LV2 enabled ONLY if ARC implementation has LV2 re-entrancy 376 depends on !SMP 377 378config ARC_FPU_SAVE_RESTORE 379 bool "Enable FPU state persistence across context switch" 380 default n 381 help 382 Double Precision Floating Point unit had dedicated regs which 383 need to be saved/restored across context-switch. 384 Note that ARC FPU is overly simplistic, unlike say x86, which has 385 hardware pieces to allow software to conditionally save/restore, 386 based on actual usage of FPU by a task. Thus our implemn does 387 this for all tasks in system. 388 389endif #ISA_ARCOMPACT 390 391config ARC_CANT_LLSC 392 def_bool n 393 394config ARC_HAS_LLSC 395 bool "Insn: LLOCK/SCOND (efficient atomic ops)" 396 default y 397 depends on !ARC_CANT_LLSC 398 399config ARC_HAS_SWAPE 400 bool "Insn: SWAPE (endian-swap)" 401 default y 402 403if ISA_ARCV2 404 405config ARC_HAS_LL64 406 bool "Insn: 64bit LDD/STD" 407 help 408 Enable gcc to generate 64-bit load/store instructions 409 ISA mandates even/odd registers to allow encoding of two 410 dest operands with 2 possible source operands. 411 default y 412 413config ARC_HAS_DIV_REM 414 bool "Insn: div, divu, rem, remu" 415 default y 416 417config ARC_HAS_ACCL_REGS 418 bool "Reg Pair ACCL:ACCH (FPU and/or MPY > 6)" 419 default y 420 help 421 Depending on the configuration, CPU can contain accumulator reg-pair 422 (also referred to as r58:r59). These can also be used by gcc as GPR so 423 kernel needs to save/restore per process 424 425endif # ISA_ARCV2 426 427endmenu # "ARC CPU Configuration" 428 429config LINUX_LINK_BASE 430 hex "Kernel link address" 431 default "0x80000000" 432 help 433 ARC700 divides the 32 bit phy address space into two equal halves 434 -Lower 2G (0 - 0x7FFF_FFFF ) is user virtual, translated by MMU 435 -Upper 2G (0x8000_0000 onwards) is untranslated, for kernel 436 Typically Linux kernel is linked at the start of untransalted addr, 437 hence the default value of 0x8zs. 438 However some customers have peripherals mapped at this addr, so 439 Linux needs to be scooted a bit. 440 If you don't know what the above means, leave this setting alone. 441 This needs to match memory start address specified in Device Tree 442 443config LINUX_RAM_BASE 444 hex "RAM base address" 445 default LINUX_LINK_BASE 446 help 447 By default Linux is linked at base of RAM. However in some special 448 cases (such as HSDK), Linux can't be linked at start of DDR, hence 449 this option. 450 451config HIGHMEM 452 bool "High Memory Support" 453 select ARCH_DISCONTIGMEM_ENABLE 454 help 455 With ARC 2G:2G address split, only upper 2G is directly addressable by 456 kernel. Enable this to potentially allow access to rest of 2G and PAE 457 in future 458 459config ARC_HAS_PAE40 460 bool "Support for the 40-bit Physical Address Extension" 461 default n 462 depends on ISA_ARCV2 463 select HIGHMEM 464 select PHYS_ADDR_T_64BIT 465 help 466 Enable access to physical memory beyond 4G, only supported on 467 ARC cores with 40 bit Physical Addressing support 468 469config ARC_KVADDR_SIZE 470 int "Kernel Virtual Address Space size (MB)" 471 range 0 512 472 default "256" 473 help 474 The kernel address space is carved out of 256MB of translated address 475 space for catering to vmalloc, modules, pkmap, fixmap. This however may 476 not suffice vmalloc requirements of a 4K CPU EZChip system. So allow 477 this to be stretched to 512 MB (by extending into the reserved 478 kernel-user gutter) 479 480config ARC_CURR_IN_REG 481 bool "Dedicate Register r25 for current_task pointer" 482 default y 483 help 484 This reserved Register R25 to point to Current Task in 485 kernel mode. This saves memory access for each such access 486 487 488config ARC_EMUL_UNALIGNED 489 bool "Emulate unaligned memory access (userspace only)" 490 select SYSCTL_ARCH_UNALIGN_NO_WARN 491 select SYSCTL_ARCH_UNALIGN_ALLOW 492 depends on ISA_ARCOMPACT 493 help 494 This enables misaligned 16 & 32 bit memory access from user space. 495 Use ONLY-IF-ABS-NECESSARY as it will be very slow and also can hide 496 potential bugs in code 497 498config HZ 499 int "Timer Frequency" 500 default 100 501 502config ARC_METAWARE_HLINK 503 bool "Support for Metaware debugger assisted Host access" 504 default n 505 help 506 This options allows a Linux userland apps to directly access 507 host file system (open/creat/read/write etc) with help from 508 Metaware Debugger. This can come in handy for Linux-host communication 509 when there is no real usable peripheral such as EMAC. 510 511menuconfig ARC_DBG 512 bool "ARC debugging" 513 default y 514 515if ARC_DBG 516 517config ARC_DW2_UNWIND 518 bool "Enable DWARF specific kernel stack unwind" 519 default y 520 select KALLSYMS 521 help 522 Compiles the kernel with DWARF unwind information and can be used 523 to get stack backtraces. 524 525 If you say Y here the resulting kernel image will be slightly larger 526 but not slower, and it will give very useful debugging information. 527 If you don't debug the kernel, you can say N, but we may not be able 528 to solve problems without frame unwind information 529 530config ARC_DBG_TLB_PARANOIA 531 bool "Paranoia Checks in Low Level TLB Handlers" 532 default n 533 534endif 535 536config ARC_UBOOT_SUPPORT 537 bool "Support uboot arg Handling" 538 default n 539 help 540 ARC Linux by default checks for uboot provided args as pointers to 541 external cmdline or DTB. This however breaks in absence of uboot, 542 when booting from Metaware debugger directly, as the registers are 543 not zeroed out on reset by mdb and/or ARCv2 based cores. The bogus 544 registers look like uboot args to kernel which then chokes. 545 So only enable the uboot arg checking/processing if users are sure 546 of uboot being in play. 547 548config ARC_BUILTIN_DTB_NAME 549 string "Built in DTB" 550 help 551 Set the name of the DTB to embed in the vmlinux binary 552 Leaving it blank selects the minimal "skeleton" dtb 553 554source "kernel/Kconfig.preempt" 555 556menu "Executable file formats" 557source "fs/Kconfig.binfmt" 558endmenu 559 560endmenu # "ARC Architecture Configuration" 561 562source "mm/Kconfig" 563 564config FORCE_MAX_ZONEORDER 565 int "Maximum zone order" 566 default "12" if ARC_HUGEPAGE_16M 567 default "11" 568 569source "net/Kconfig" 570source "drivers/Kconfig" 571 572menu "Bus Support" 573 574config PCI 575 bool "PCI support" if MIGHT_HAVE_PCI 576 help 577 PCI is the name of a bus system, i.e., the way the CPU talks to 578 the other stuff inside your box. Find out if your board/platform 579 has PCI. 580 581 Note: PCIe support for Synopsys Device will be available only 582 when HAPS DX is configured with PCIe RC bitmap. If you have PCI, 583 say Y, otherwise N. 584 585config PCI_SYSCALL 586 def_bool PCI 587 588source "drivers/pci/Kconfig" 589 590endmenu 591 592source "fs/Kconfig" 593source "arch/arc/Kconfig.debug" 594source "security/Kconfig" 595source "crypto/Kconfig" 596source "lib/Kconfig" 597source "kernel/power/Kconfig" 598