1# 2# Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com) 3# 4# This program is free software; you can redistribute it and/or modify 5# it under the terms of the GNU General Public License version 2 as 6# published by the Free Software Foundation. 7# 8 9config ARC 10 def_bool y 11 select ARCH_SUPPORTS_ATOMIC_RMW if ARC_HAS_LLSC 12 select BUILDTIME_EXTABLE_SORT 13 select CLKSRC_OF 14 select CLONE_BACKWARDS 15 select COMMON_CLK 16 select GENERIC_ATOMIC64 if !ISA_ARCV2 || !(ARC_HAS_LL64 && ARC_HAS_LLSC) 17 select GENERIC_CLOCKEVENTS 18 select GENERIC_FIND_FIRST_BIT 19 # for now, we don't need GENERIC_IRQ_PROBE, CONFIG_GENERIC_IRQ_CHIP 20 select GENERIC_IRQ_SHOW 21 select GENERIC_PCI_IOMAP 22 select GENERIC_PENDING_IRQ if SMP 23 select GENERIC_SMP_IDLE_THREAD 24 select HAVE_ARCH_KGDB 25 select HAVE_ARCH_TRACEHOOK 26 select HAVE_FUTEX_CMPXCHG 27 select HAVE_IOREMAP_PROT 28 select HAVE_KPROBES 29 select HAVE_KRETPROBES 30 select HAVE_MEMBLOCK 31 select HAVE_MOD_ARCH_SPECIFIC if ARC_DW2_UNWIND 32 select HAVE_OPROFILE 33 select HAVE_PERF_EVENTS 34 select HANDLE_DOMAIN_IRQ 35 select IRQ_DOMAIN 36 select MODULES_USE_ELF_RELA 37 select NO_BOOTMEM 38 select OF 39 select OF_EARLY_FLATTREE 40 select OF_RESERVED_MEM 41 select PERF_USE_VMALLOC 42 select HAVE_DEBUG_STACKOVERFLOW 43 select HAVE_GENERIC_DMA_COHERENT 44 select HAVE_KERNEL_GZIP 45 select HAVE_KERNEL_LZMA 46 47config MIGHT_HAVE_PCI 48 bool 49 50config TRACE_IRQFLAGS_SUPPORT 51 def_bool y 52 53config LOCKDEP_SUPPORT 54 def_bool y 55 56config SCHED_OMIT_FRAME_POINTER 57 def_bool y 58 59config GENERIC_CSUM 60 def_bool y 61 62config RWSEM_GENERIC_SPINLOCK 63 def_bool y 64 65config ARCH_DISCONTIGMEM_ENABLE 66 def_bool n 67 68config ARCH_FLATMEM_ENABLE 69 def_bool y 70 71config MMU 72 def_bool y 73 74config NO_IOPORT_MAP 75 def_bool y 76 77config GENERIC_CALIBRATE_DELAY 78 def_bool y 79 80config GENERIC_HWEIGHT 81 def_bool y 82 83config STACKTRACE_SUPPORT 84 def_bool y 85 select STACKTRACE 86 87config HAVE_ARCH_TRANSPARENT_HUGEPAGE 88 def_bool y 89 depends on ARC_MMU_V4 90 91source "init/Kconfig" 92source "kernel/Kconfig.freezer" 93 94menu "ARC Architecture Configuration" 95 96menu "ARC Platform/SoC/Board" 97 98source "arch/arc/plat-sim/Kconfig" 99source "arch/arc/plat-tb10x/Kconfig" 100source "arch/arc/plat-axs10x/Kconfig" 101#New platform adds here 102source "arch/arc/plat-eznps/Kconfig" 103 104endmenu 105 106choice 107 prompt "ARC Instruction Set" 108 default ISA_ARCOMPACT 109 110config ISA_ARCOMPACT 111 bool "ARCompact ISA" 112 select CPU_NO_EFFICIENT_FFS 113 help 114 The original ARC ISA of ARC600/700 cores 115 116config ISA_ARCV2 117 bool "ARC ISA v2" 118 help 119 ISA for the Next Generation ARC-HS cores 120 121endchoice 122 123menu "ARC CPU Configuration" 124 125choice 126 prompt "ARC Core" 127 default ARC_CPU_770 if ISA_ARCOMPACT 128 default ARC_CPU_HS if ISA_ARCV2 129 130if ISA_ARCOMPACT 131 132config ARC_CPU_750D 133 bool "ARC750D" 134 select ARC_CANT_LLSC 135 help 136 Support for ARC750 core 137 138config ARC_CPU_770 139 bool "ARC770" 140 select ARC_HAS_SWAPE 141 help 142 Support for ARC770 core introduced with Rel 4.10 (Summer 2011) 143 This core has a bunch of cool new features: 144 -MMU-v3: Variable Page Sz (4k, 8k, 16k), bigger J-TLB (128x4) 145 Shared Address Spaces (for sharing TLB entires in MMU) 146 -Caches: New Prog Model, Region Flush 147 -Insns: endian swap, load-locked/store-conditional, time-stamp-ctr 148 149endif #ISA_ARCOMPACT 150 151config ARC_CPU_HS 152 bool "ARC-HS" 153 depends on ISA_ARCV2 154 help 155 Support for ARC HS38x Cores based on ARCv2 ISA 156 The notable features are: 157 - SMP configurations of upto 4 core with coherency 158 - Optional L2 Cache and IO-Coherency 159 - Revised Interrupt Architecture (multiple priorites, reg banks, 160 auto stack switch, auto regfile save/restore) 161 - MMUv4 (PIPT dcache, Huge Pages) 162 - Instructions for 163 * 64bit load/store: LDD, STD 164 * Hardware assisted divide/remainder: DIV, REM 165 * Function prologue/epilogue: ENTER_S, LEAVE_S 166 * IRQ enable/disable: CLRI, SETI 167 * pop count: FFS, FLS 168 * SETcc, BMSKN, XBFU... 169 170endchoice 171 172config CPU_BIG_ENDIAN 173 bool "Enable Big Endian Mode" 174 default n 175 help 176 Build kernel for Big Endian Mode of ARC CPU 177 178config SMP 179 bool "Symmetric Multi-Processing" 180 default n 181 select ARC_HAS_COH_CACHES if ISA_ARCV2 182 select ARC_MCIP if ISA_ARCV2 183 help 184 This enables support for systems with more than one CPU. 185 186if SMP 187 188config ARC_HAS_COH_CACHES 189 def_bool n 190 191config NR_CPUS 192 int "Maximum number of CPUs (2-4096)" 193 range 2 4096 194 default "4" 195 196config ARC_SMP_HALT_ON_RESET 197 bool "Enable Halt-on-reset boot mode" 198 default y if ARC_UBOOT_SUPPORT 199 help 200 In SMP configuration cores can be configured as Halt-on-reset 201 or they could all start at same time. For Halt-on-reset, non 202 masters are parked until Master kicks them so they can start of 203 at designated entry point. For other case, all jump to common 204 entry point and spin wait for Master's signal. 205 206endif #SMP 207 208config ARC_MCIP 209 bool "ARConnect Multicore IP (MCIP) Support " 210 depends on ISA_ARCV2 211 default y if SMP 212 help 213 This IP block enables SMP in ARC-HS38 cores. 214 It provides for cross-core interrupts, multi-core debug 215 hardware semaphores, shared memory,.... 216 217menuconfig ARC_CACHE 218 bool "Enable Cache Support" 219 default y 220 # if SMP, cache enabled ONLY if ARC implementation has cache coherency 221 depends on !SMP || ARC_HAS_COH_CACHES 222 223if ARC_CACHE 224 225config ARC_CACHE_LINE_SHIFT 226 int "Cache Line Length (as power of 2)" 227 range 5 7 228 default "6" 229 help 230 Starting with ARC700 4.9, Cache line length is configurable, 231 This option specifies "N", with Line-len = 2 power N 232 So line lengths of 32, 64, 128 are specified by 5,6,7, respectively 233 Linux only supports same line lengths for I and D caches. 234 235config ARC_HAS_ICACHE 236 bool "Use Instruction Cache" 237 default y 238 239config ARC_HAS_DCACHE 240 bool "Use Data Cache" 241 default y 242 243config ARC_CACHE_PAGES 244 bool "Per Page Cache Control" 245 default y 246 depends on ARC_HAS_ICACHE || ARC_HAS_DCACHE 247 help 248 This can be used to over-ride the global I/D Cache Enable on a 249 per-page basis (but only for pages accessed via MMU such as 250 Kernel Virtual address or User Virtual Address) 251 TLB entries have a per-page Cache Enable Bit. 252 Note that Global I/D ENABLE + Per Page DISABLE works but corollary 253 Global DISABLE + Per Page ENABLE won't work 254 255config ARC_CACHE_VIPT_ALIASING 256 bool "Support VIPT Aliasing D$" 257 depends on ARC_HAS_DCACHE && ISA_ARCOMPACT 258 default n 259 260endif #ARC_CACHE 261 262config ARC_HAS_ICCM 263 bool "Use ICCM" 264 help 265 Single Cycle RAMS to store Fast Path Code 266 default n 267 268config ARC_ICCM_SZ 269 int "ICCM Size in KB" 270 default "64" 271 depends on ARC_HAS_ICCM 272 273config ARC_HAS_DCCM 274 bool "Use DCCM" 275 help 276 Single Cycle RAMS to store Fast Path Data 277 default n 278 279config ARC_DCCM_SZ 280 int "DCCM Size in KB" 281 default "64" 282 depends on ARC_HAS_DCCM 283 284config ARC_DCCM_BASE 285 hex "DCCM map address" 286 default "0xA0000000" 287 depends on ARC_HAS_DCCM 288 289choice 290 prompt "MMU Version" 291 default ARC_MMU_V3 if ARC_CPU_770 292 default ARC_MMU_V2 if ARC_CPU_750D 293 default ARC_MMU_V4 if ARC_CPU_HS 294 295if ISA_ARCOMPACT 296 297config ARC_MMU_V1 298 bool "MMU v1" 299 help 300 Orig ARC700 MMU 301 302config ARC_MMU_V2 303 bool "MMU v2" 304 help 305 Fixed the deficiency of v1 - possible thrashing in memcpy sceanrio 306 when 2 D-TLB and 1 I-TLB entries index into same 2way set. 307 308config ARC_MMU_V3 309 bool "MMU v3" 310 depends on ARC_CPU_770 311 help 312 Introduced with ARC700 4.10: New Features 313 Variable Page size (1k-16k), var JTLB size 128 x (2 or 4) 314 Shared Address Spaces (SASID) 315 316endif 317 318config ARC_MMU_V4 319 bool "MMU v4" 320 depends on ISA_ARCV2 321 322endchoice 323 324 325choice 326 prompt "MMU Page Size" 327 default ARC_PAGE_SIZE_8K 328 329config ARC_PAGE_SIZE_8K 330 bool "8KB" 331 help 332 Choose between 8k vs 16k 333 334config ARC_PAGE_SIZE_16K 335 bool "16KB" 336 depends on ARC_MMU_V3 || ARC_MMU_V4 337 338config ARC_PAGE_SIZE_4K 339 bool "4KB" 340 depends on ARC_MMU_V3 || ARC_MMU_V4 341 342endchoice 343 344choice 345 prompt "MMU Super Page Size" 346 depends on ISA_ARCV2 && TRANSPARENT_HUGEPAGE 347 default ARC_HUGEPAGE_2M 348 349config ARC_HUGEPAGE_2M 350 bool "2MB" 351 352config ARC_HUGEPAGE_16M 353 bool "16MB" 354 355endchoice 356 357config NODES_SHIFT 358 int "Maximum NUMA Nodes (as a power of 2)" 359 default "0" if !DISCONTIGMEM 360 default "1" if DISCONTIGMEM 361 depends on NEED_MULTIPLE_NODES 362 ---help--- 363 Accessing memory beyond 1GB (with or w/o PAE) requires 2 memory 364 zones. 365 366if ISA_ARCOMPACT 367 368config ARC_COMPACT_IRQ_LEVELS 369 bool "Setup Timer IRQ as high Priority" 370 default n 371 # if SMP, LV2 enabled ONLY if ARC implementation has LV2 re-entrancy 372 depends on !SMP 373 374config ARC_FPU_SAVE_RESTORE 375 bool "Enable FPU state persistence across context switch" 376 default n 377 help 378 Double Precision Floating Point unit had dedictaed regs which 379 need to be saved/restored across context-switch. 380 Note that ARC FPU is overly simplistic, unlike say x86, which has 381 hardware pieces to allow software to conditionally save/restore, 382 based on actual usage of FPU by a task. Thus our implemn does 383 this for all tasks in system. 384 385endif #ISA_ARCOMPACT 386 387config ARC_CANT_LLSC 388 def_bool n 389 390config ARC_HAS_LLSC 391 bool "Insn: LLOCK/SCOND (efficient atomic ops)" 392 default y 393 depends on !ARC_CANT_LLSC 394 395config ARC_HAS_SWAPE 396 bool "Insn: SWAPE (endian-swap)" 397 default y 398 399if ISA_ARCV2 400 401config ARC_HAS_LL64 402 bool "Insn: 64bit LDD/STD" 403 help 404 Enable gcc to generate 64-bit load/store instructions 405 ISA mandates even/odd registers to allow encoding of two 406 dest operands with 2 possible source operands. 407 default y 408 409config ARC_HAS_DIV_REM 410 bool "Insn: div, divu, rem, remu" 411 default y 412 413config ARC_TIMERS_64BIT 414 bool "64-bit r/o cycle counters RTC (up) and GFRC (smp)" 415 default y 416 417config ARC_NUMBER_OF_INTERRUPTS 418 int "Number of interrupts" 419 range 8 240 420 default 32 421 help 422 This defines the number of interrupts on the ARCv2HS core. 423 It affects the size of vector table. 424 The initial 8 IRQs are fixed (Timer, ICI etc) and although configurable 425 in hardware, it keep things simple for Linux to assume they are always 426 present. 427 428endif # ISA_ARCV2 429 430endmenu # "ARC CPU Configuration" 431 432config LINUX_LINK_BASE 433 hex "Linux Link Address" 434 default "0x80000000" 435 help 436 ARC700 divides the 32 bit phy address space into two equal halves 437 -Lower 2G (0 - 0x7FFF_FFFF ) is user virtual, translated by MMU 438 -Upper 2G (0x8000_0000 onwards) is untranslated, for kernel 439 Typically Linux kernel is linked at the start of untransalted addr, 440 hence the default value of 0x8zs. 441 However some customers have peripherals mapped at this addr, so 442 Linux needs to be scooted a bit. 443 If you don't know what the above means, leave this setting alone. 444 This needs to match memory start address specified in Device Tree 445 446config HIGHMEM 447 bool "High Memory Support" 448 select ARCH_DISCONTIGMEM_ENABLE 449 help 450 With ARC 2G:2G address split, only upper 2G is directly addressable by 451 kernel. Enable this to potentially allow access to rest of 2G and PAE 452 in future 453 454config ARC_HAS_PAE40 455 bool "Support for the 40-bit Physical Address Extension" 456 default n 457 depends on ISA_ARCV2 458 help 459 Enable access to physical memory beyond 4G, only supported on 460 ARC cores with 40 bit Physical Addressing support 461 462config ARCH_PHYS_ADDR_T_64BIT 463 def_bool ARC_HAS_PAE40 464 465config ARCH_DMA_ADDR_T_64BIT 466 bool 467 468config ARC_PLAT_NEEDS_PHYS_TO_DMA 469 bool 470 471config ARC_KVADDR_SIZE 472 int "Kernel Virtaul Address Space size (MB)" 473 range 0 512 474 default "256" 475 help 476 The kernel address space is carved out of 256MB of translated address 477 space for catering to vmalloc, modules, pkmap, fixmap. This however may 478 not suffice vmalloc requirements of a 4K CPU EZChip system. So allow 479 this to be stretched to 512 MB (by extending into the reserved 480 kernel-user gutter) 481 482config ARC_CURR_IN_REG 483 bool "Dedicate Register r25 for current_task pointer" 484 default y 485 help 486 This reserved Register R25 to point to Current Task in 487 kernel mode. This saves memory access for each such access 488 489 490config ARC_EMUL_UNALIGNED 491 bool "Emulate unaligned memory access (userspace only)" 492 default N 493 select SYSCTL_ARCH_UNALIGN_NO_WARN 494 select SYSCTL_ARCH_UNALIGN_ALLOW 495 depends on ISA_ARCOMPACT 496 help 497 This enables misaligned 16 & 32 bit memory access from user space. 498 Use ONLY-IF-ABS-NECESSARY as it will be very slow and also can hide 499 potential bugs in code 500 501config HZ 502 int "Timer Frequency" 503 default 100 504 505config ARC_METAWARE_HLINK 506 bool "Support for Metaware debugger assisted Host access" 507 default n 508 help 509 This options allows a Linux userland apps to directly access 510 host file system (open/creat/read/write etc) with help from 511 Metaware Debugger. This can come in handy for Linux-host communication 512 when there is no real usable peripheral such as EMAC. 513 514menuconfig ARC_DBG 515 bool "ARC debugging" 516 default y 517 518if ARC_DBG 519 520config ARC_DW2_UNWIND 521 bool "Enable DWARF specific kernel stack unwind" 522 default y 523 select KALLSYMS 524 help 525 Compiles the kernel with DWARF unwind information and can be used 526 to get stack backtraces. 527 528 If you say Y here the resulting kernel image will be slightly larger 529 but not slower, and it will give very useful debugging information. 530 If you don't debug the kernel, you can say N, but we may not be able 531 to solve problems without frame unwind information 532 533config ARC_DBG_TLB_PARANOIA 534 bool "Paranoia Checks in Low Level TLB Handlers" 535 default n 536 537endif 538 539config ARC_UBOOT_SUPPORT 540 bool "Support uboot arg Handling" 541 default n 542 help 543 ARC Linux by default checks for uboot provided args as pointers to 544 external cmdline or DTB. This however breaks in absence of uboot, 545 when booting from Metaware debugger directly, as the registers are 546 not zeroed out on reset by mdb and/or ARCv2 based cores. The bogus 547 registers look like uboot args to kernel which then chokes. 548 So only enable the uboot arg checking/processing if users are sure 549 of uboot being in play. 550 551config ARC_BUILTIN_DTB_NAME 552 string "Built in DTB" 553 help 554 Set the name of the DTB to embed in the vmlinux binary 555 Leaving it blank selects the minimal "skeleton" dtb 556 557source "kernel/Kconfig.preempt" 558 559menu "Executable file formats" 560source "fs/Kconfig.binfmt" 561endmenu 562 563endmenu # "ARC Architecture Configuration" 564 565source "mm/Kconfig" 566 567config FORCE_MAX_ZONEORDER 568 int "Maximum zone order" 569 default "12" if ARC_HUGEPAGE_16M 570 default "11" 571 572source "net/Kconfig" 573source "drivers/Kconfig" 574 575menu "Bus Support" 576 577config PCI 578 bool "PCI support" if MIGHT_HAVE_PCI 579 help 580 PCI is the name of a bus system, i.e., the way the CPU talks to 581 the other stuff inside your box. Find out if your board/platform 582 has PCI. 583 584 Note: PCIe support for Synopsys Device will be available only 585 when HAPS DX is configured with PCIe RC bitmap. If you have PCI, 586 say Y, otherwise N. 587 588config PCI_SYSCALL 589 def_bool PCI 590 591source "drivers/pci/Kconfig" 592 593endmenu 594 595source "fs/Kconfig" 596source "arch/arc/Kconfig.debug" 597source "security/Kconfig" 598source "crypto/Kconfig" 599source "lib/Kconfig" 600source "kernel/power/Kconfig" 601