1# SPDX-License-Identifier: GPL-2.0-only 2# 3# Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com) 4# 5 6config ARC 7 def_bool y 8 select ARC_TIMERS 9 select ARCH_HAS_DMA_PREP_COHERENT 10 select ARCH_HAS_PTE_SPECIAL 11 select ARCH_HAS_SETUP_DMA_OPS 12 select ARCH_HAS_SYNC_DMA_FOR_CPU 13 select ARCH_HAS_SYNC_DMA_FOR_DEVICE 14 select ARCH_SUPPORTS_ATOMIC_RMW if ARC_HAS_LLSC 15 select ARCH_32BIT_OFF_T 16 select BUILDTIME_EXTABLE_SORT 17 select CLONE_BACKWARDS 18 select COMMON_CLK 19 select DMA_DIRECT_REMAP 20 select GENERIC_ATOMIC64 if !ISA_ARCV2 || !(ARC_HAS_LL64 && ARC_HAS_LLSC) 21 select GENERIC_CLOCKEVENTS 22 select GENERIC_FIND_FIRST_BIT 23 # for now, we don't need GENERIC_IRQ_PROBE, CONFIG_GENERIC_IRQ_CHIP 24 select GENERIC_IRQ_SHOW 25 select GENERIC_PCI_IOMAP 26 select GENERIC_PENDING_IRQ if SMP 27 select GENERIC_SCHED_CLOCK 28 select GENERIC_SMP_IDLE_THREAD 29 select HAVE_ARCH_KGDB 30 select HAVE_ARCH_TRACEHOOK 31 select HAVE_COPY_THREAD_TLS 32 select HAVE_DEBUG_STACKOVERFLOW 33 select HAVE_DEBUG_KMEMLEAK 34 select HAVE_FUTEX_CMPXCHG if FUTEX 35 select HAVE_IOREMAP_PROT 36 select HAVE_KERNEL_GZIP 37 select HAVE_KERNEL_LZMA 38 select HAVE_KPROBES 39 select HAVE_KRETPROBES 40 select HAVE_MOD_ARCH_SPECIFIC 41 select HAVE_OPROFILE 42 select HAVE_PERF_EVENTS 43 select HANDLE_DOMAIN_IRQ 44 select IRQ_DOMAIN 45 select MODULES_USE_ELF_RELA 46 select OF 47 select OF_EARLY_FLATTREE 48 select PCI_SYSCALL if PCI 49 select PERF_USE_VMALLOC if ARC_CACHE_VIPT_ALIASING 50 select HAVE_ARCH_JUMP_LABEL if ISA_ARCV2 && !CPU_ENDIAN_BE32 51 52config ARCH_HAS_CACHE_LINE_SIZE 53 def_bool y 54 55config TRACE_IRQFLAGS_SUPPORT 56 def_bool y 57 58config LOCKDEP_SUPPORT 59 def_bool y 60 61config SCHED_OMIT_FRAME_POINTER 62 def_bool y 63 64config GENERIC_CSUM 65 def_bool y 66 67config ARCH_DISCONTIGMEM_ENABLE 68 def_bool n 69 70config ARCH_FLATMEM_ENABLE 71 def_bool y 72 73config MMU 74 def_bool y 75 76config NO_IOPORT_MAP 77 def_bool y 78 79config GENERIC_CALIBRATE_DELAY 80 def_bool y 81 82config GENERIC_HWEIGHT 83 def_bool y 84 85config STACKTRACE_SUPPORT 86 def_bool y 87 select STACKTRACE 88 89config HAVE_ARCH_TRANSPARENT_HUGEPAGE 90 def_bool y 91 depends on ARC_MMU_V4 92 93menu "ARC Architecture Configuration" 94 95menu "ARC Platform/SoC/Board" 96 97source "arch/arc/plat-tb10x/Kconfig" 98source "arch/arc/plat-axs10x/Kconfig" 99#New platform adds here 100source "arch/arc/plat-eznps/Kconfig" 101source "arch/arc/plat-hsdk/Kconfig" 102 103endmenu 104 105choice 106 prompt "ARC Instruction Set" 107 default ISA_ARCV2 108 109config ISA_ARCOMPACT 110 bool "ARCompact ISA" 111 select CPU_NO_EFFICIENT_FFS 112 help 113 The original ARC ISA of ARC600/700 cores 114 115config ISA_ARCV2 116 bool "ARC ISA v2" 117 select ARC_TIMERS_64BIT 118 help 119 ISA for the Next Generation ARC-HS cores 120 121endchoice 122 123menu "ARC CPU Configuration" 124 125choice 126 prompt "ARC Core" 127 default ARC_CPU_770 if ISA_ARCOMPACT 128 default ARC_CPU_HS if ISA_ARCV2 129 130if ISA_ARCOMPACT 131 132config ARC_CPU_750D 133 bool "ARC750D" 134 select ARC_CANT_LLSC 135 help 136 Support for ARC750 core 137 138config ARC_CPU_770 139 bool "ARC770" 140 select ARC_HAS_SWAPE 141 help 142 Support for ARC770 core introduced with Rel 4.10 (Summer 2011) 143 This core has a bunch of cool new features: 144 -MMU-v3: Variable Page Sz (4k, 8k, 16k), bigger J-TLB (128x4) 145 Shared Address Spaces (for sharing TLB entries in MMU) 146 -Caches: New Prog Model, Region Flush 147 -Insns: endian swap, load-locked/store-conditional, time-stamp-ctr 148 149endif #ISA_ARCOMPACT 150 151config ARC_CPU_HS 152 bool "ARC-HS" 153 depends on ISA_ARCV2 154 help 155 Support for ARC HS38x Cores based on ARCv2 ISA 156 The notable features are: 157 - SMP configurations of upto 4 core with coherency 158 - Optional L2 Cache and IO-Coherency 159 - Revised Interrupt Architecture (multiple priorites, reg banks, 160 auto stack switch, auto regfile save/restore) 161 - MMUv4 (PIPT dcache, Huge Pages) 162 - Instructions for 163 * 64bit load/store: LDD, STD 164 * Hardware assisted divide/remainder: DIV, REM 165 * Function prologue/epilogue: ENTER_S, LEAVE_S 166 * IRQ enable/disable: CLRI, SETI 167 * pop count: FFS, FLS 168 * SETcc, BMSKN, XBFU... 169 170endchoice 171 172config CPU_BIG_ENDIAN 173 bool "Enable Big Endian Mode" 174 help 175 Build kernel for Big Endian Mode of ARC CPU 176 177config SMP 178 bool "Symmetric Multi-Processing" 179 select ARC_MCIP if ISA_ARCV2 180 help 181 This enables support for systems with more than one CPU. 182 183if SMP 184 185config NR_CPUS 186 int "Maximum number of CPUs (2-4096)" 187 range 2 4096 188 default "4" 189 190config ARC_SMP_HALT_ON_RESET 191 bool "Enable Halt-on-reset boot mode" 192 help 193 In SMP configuration cores can be configured as Halt-on-reset 194 or they could all start at same time. For Halt-on-reset, non 195 masters are parked until Master kicks them so they can start of 196 at designated entry point. For other case, all jump to common 197 entry point and spin wait for Master's signal. 198 199endif #SMP 200 201config ARC_MCIP 202 bool "ARConnect Multicore IP (MCIP) Support " 203 depends on ISA_ARCV2 204 default y if SMP 205 help 206 This IP block enables SMP in ARC-HS38 cores. 207 It provides for cross-core interrupts, multi-core debug 208 hardware semaphores, shared memory,.... 209 210menuconfig ARC_CACHE 211 bool "Enable Cache Support" 212 default y 213 214if ARC_CACHE 215 216config ARC_CACHE_LINE_SHIFT 217 int "Cache Line Length (as power of 2)" 218 range 5 7 219 default "6" 220 help 221 Starting with ARC700 4.9, Cache line length is configurable, 222 This option specifies "N", with Line-len = 2 power N 223 So line lengths of 32, 64, 128 are specified by 5,6,7, respectively 224 Linux only supports same line lengths for I and D caches. 225 226config ARC_HAS_ICACHE 227 bool "Use Instruction Cache" 228 default y 229 230config ARC_HAS_DCACHE 231 bool "Use Data Cache" 232 default y 233 234config ARC_CACHE_PAGES 235 bool "Per Page Cache Control" 236 default y 237 depends on ARC_HAS_ICACHE || ARC_HAS_DCACHE 238 help 239 This can be used to over-ride the global I/D Cache Enable on a 240 per-page basis (but only for pages accessed via MMU such as 241 Kernel Virtual address or User Virtual Address) 242 TLB entries have a per-page Cache Enable Bit. 243 Note that Global I/D ENABLE + Per Page DISABLE works but corollary 244 Global DISABLE + Per Page ENABLE won't work 245 246config ARC_CACHE_VIPT_ALIASING 247 bool "Support VIPT Aliasing D$" 248 depends on ARC_HAS_DCACHE && ISA_ARCOMPACT 249 250endif #ARC_CACHE 251 252config ARC_HAS_ICCM 253 bool "Use ICCM" 254 help 255 Single Cycle RAMS to store Fast Path Code 256 257config ARC_ICCM_SZ 258 int "ICCM Size in KB" 259 default "64" 260 depends on ARC_HAS_ICCM 261 262config ARC_HAS_DCCM 263 bool "Use DCCM" 264 help 265 Single Cycle RAMS to store Fast Path Data 266 267config ARC_DCCM_SZ 268 int "DCCM Size in KB" 269 default "64" 270 depends on ARC_HAS_DCCM 271 272config ARC_DCCM_BASE 273 hex "DCCM map address" 274 default "0xA0000000" 275 depends on ARC_HAS_DCCM 276 277choice 278 prompt "MMU Version" 279 default ARC_MMU_V3 if ARC_CPU_770 280 default ARC_MMU_V2 if ARC_CPU_750D 281 default ARC_MMU_V4 if ARC_CPU_HS 282 283if ISA_ARCOMPACT 284 285config ARC_MMU_V1 286 bool "MMU v1" 287 help 288 Orig ARC700 MMU 289 290config ARC_MMU_V2 291 bool "MMU v2" 292 help 293 Fixed the deficiency of v1 - possible thrashing in memcpy scenario 294 when 2 D-TLB and 1 I-TLB entries index into same 2way set. 295 296config ARC_MMU_V3 297 bool "MMU v3" 298 depends on ARC_CPU_770 299 help 300 Introduced with ARC700 4.10: New Features 301 Variable Page size (1k-16k), var JTLB size 128 x (2 or 4) 302 Shared Address Spaces (SASID) 303 304endif 305 306config ARC_MMU_V4 307 bool "MMU v4" 308 depends on ISA_ARCV2 309 310endchoice 311 312 313choice 314 prompt "MMU Page Size" 315 default ARC_PAGE_SIZE_8K 316 317config ARC_PAGE_SIZE_8K 318 bool "8KB" 319 help 320 Choose between 8k vs 16k 321 322config ARC_PAGE_SIZE_16K 323 bool "16KB" 324 depends on ARC_MMU_V3 || ARC_MMU_V4 325 326config ARC_PAGE_SIZE_4K 327 bool "4KB" 328 depends on ARC_MMU_V3 || ARC_MMU_V4 329 330endchoice 331 332choice 333 prompt "MMU Super Page Size" 334 depends on ISA_ARCV2 && TRANSPARENT_HUGEPAGE 335 default ARC_HUGEPAGE_2M 336 337config ARC_HUGEPAGE_2M 338 bool "2MB" 339 340config ARC_HUGEPAGE_16M 341 bool "16MB" 342 343endchoice 344 345config NODES_SHIFT 346 int "Maximum NUMA Nodes (as a power of 2)" 347 default "0" if !DISCONTIGMEM 348 default "1" if DISCONTIGMEM 349 depends on NEED_MULTIPLE_NODES 350 ---help--- 351 Accessing memory beyond 1GB (with or w/o PAE) requires 2 memory 352 zones. 353 354if ISA_ARCOMPACT 355 356config ARC_COMPACT_IRQ_LEVELS 357 bool "Setup Timer IRQ as high Priority" 358 # if SMP, LV2 enabled ONLY if ARC implementation has LV2 re-entrancy 359 depends on !SMP 360 361config ARC_FPU_SAVE_RESTORE 362 bool "Enable FPU state persistence across context switch" 363 help 364 Double Precision Floating Point unit had dedicated regs which 365 need to be saved/restored across context-switch. 366 Note that ARC FPU is overly simplistic, unlike say x86, which has 367 hardware pieces to allow software to conditionally save/restore, 368 based on actual usage of FPU by a task. Thus our implemn does 369 this for all tasks in system. 370 371endif #ISA_ARCOMPACT 372 373config ARC_CANT_LLSC 374 def_bool n 375 376config ARC_HAS_LLSC 377 bool "Insn: LLOCK/SCOND (efficient atomic ops)" 378 default y 379 depends on !ARC_CANT_LLSC 380 381config ARC_HAS_SWAPE 382 bool "Insn: SWAPE (endian-swap)" 383 default y 384 385if ISA_ARCV2 386 387config ARC_USE_UNALIGNED_MEM_ACCESS 388 bool "Enable unaligned access in HW" 389 default y 390 select HAVE_EFFICIENT_UNALIGNED_ACCESS 391 help 392 The ARC HS architecture supports unaligned memory access 393 which is disabled by default. Enable unaligned access in 394 hardware and use software to use it 395 396config ARC_HAS_LL64 397 bool "Insn: 64bit LDD/STD" 398 help 399 Enable gcc to generate 64-bit load/store instructions 400 ISA mandates even/odd registers to allow encoding of two 401 dest operands with 2 possible source operands. 402 default y 403 404config ARC_HAS_DIV_REM 405 bool "Insn: div, divu, rem, remu" 406 default y 407 408config ARC_HAS_ACCL_REGS 409 bool "Reg Pair ACCL:ACCH (FPU and/or MPY > 6)" 410 default y 411 help 412 Depending on the configuration, CPU can contain accumulator reg-pair 413 (also referred to as r58:r59). These can also be used by gcc as GPR so 414 kernel needs to save/restore per process 415 416config ARC_IRQ_NO_AUTOSAVE 417 bool "Disable hardware autosave regfile on interrupts" 418 default n 419 help 420 On HS cores, taken interrupt auto saves the regfile on stack. 421 This is programmable and can be optionally disabled in which case 422 software INTERRUPT_PROLOGUE/EPILGUE do the needed work 423 424endif # ISA_ARCV2 425 426endmenu # "ARC CPU Configuration" 427 428config LINUX_LINK_BASE 429 hex "Kernel link address" 430 default "0x80000000" 431 help 432 ARC700 divides the 32 bit phy address space into two equal halves 433 -Lower 2G (0 - 0x7FFF_FFFF ) is user virtual, translated by MMU 434 -Upper 2G (0x8000_0000 onwards) is untranslated, for kernel 435 Typically Linux kernel is linked at the start of untransalted addr, 436 hence the default value of 0x8zs. 437 However some customers have peripherals mapped at this addr, so 438 Linux needs to be scooted a bit. 439 If you don't know what the above means, leave this setting alone. 440 This needs to match memory start address specified in Device Tree 441 442config LINUX_RAM_BASE 443 hex "RAM base address" 444 default LINUX_LINK_BASE 445 help 446 By default Linux is linked at base of RAM. However in some special 447 cases (such as HSDK), Linux can't be linked at start of DDR, hence 448 this option. 449 450config HIGHMEM 451 bool "High Memory Support" 452 select ARCH_DISCONTIGMEM_ENABLE 453 help 454 With ARC 2G:2G address split, only upper 2G is directly addressable by 455 kernel. Enable this to potentially allow access to rest of 2G and PAE 456 in future 457 458config ARC_HAS_PAE40 459 bool "Support for the 40-bit Physical Address Extension" 460 depends on ISA_ARCV2 461 select HIGHMEM 462 select PHYS_ADDR_T_64BIT 463 help 464 Enable access to physical memory beyond 4G, only supported on 465 ARC cores with 40 bit Physical Addressing support 466 467config ARC_KVADDR_SIZE 468 int "Kernel Virtual Address Space size (MB)" 469 range 0 512 470 default "256" 471 help 472 The kernel address space is carved out of 256MB of translated address 473 space for catering to vmalloc, modules, pkmap, fixmap. This however may 474 not suffice vmalloc requirements of a 4K CPU EZChip system. So allow 475 this to be stretched to 512 MB (by extending into the reserved 476 kernel-user gutter) 477 478config ARC_CURR_IN_REG 479 bool "Dedicate Register r25 for current_task pointer" 480 default y 481 help 482 This reserved Register R25 to point to Current Task in 483 kernel mode. This saves memory access for each such access 484 485 486config ARC_EMUL_UNALIGNED 487 bool "Emulate unaligned memory access (userspace only)" 488 select SYSCTL_ARCH_UNALIGN_NO_WARN 489 select SYSCTL_ARCH_UNALIGN_ALLOW 490 depends on ISA_ARCOMPACT 491 help 492 This enables misaligned 16 & 32 bit memory access from user space. 493 Use ONLY-IF-ABS-NECESSARY as it will be very slow and also can hide 494 potential bugs in code 495 496config HZ 497 int "Timer Frequency" 498 default 100 499 500config ARC_METAWARE_HLINK 501 bool "Support for Metaware debugger assisted Host access" 502 help 503 This options allows a Linux userland apps to directly access 504 host file system (open/creat/read/write etc) with help from 505 Metaware Debugger. This can come in handy for Linux-host communication 506 when there is no real usable peripheral such as EMAC. 507 508menuconfig ARC_DBG 509 bool "ARC debugging" 510 default y 511 512if ARC_DBG 513 514config ARC_DW2_UNWIND 515 bool "Enable DWARF specific kernel stack unwind" 516 default y 517 select KALLSYMS 518 help 519 Compiles the kernel with DWARF unwind information and can be used 520 to get stack backtraces. 521 522 If you say Y here the resulting kernel image will be slightly larger 523 but not slower, and it will give very useful debugging information. 524 If you don't debug the kernel, you can say N, but we may not be able 525 to solve problems without frame unwind information 526 527config ARC_DBG_TLB_PARANOIA 528 bool "Paranoia Checks in Low Level TLB Handlers" 529 530config ARC_DBG_JUMP_LABEL 531 bool "Paranoid checks in Static Keys (jump labels) code" 532 depends on JUMP_LABEL 533 default y if STATIC_KEYS_SELFTEST 534 help 535 Enable paranoid checks and self-test of both ARC-specific and generic 536 part of static keys (jump labels) related code. 537endif 538 539config ARC_BUILTIN_DTB_NAME 540 string "Built in DTB" 541 help 542 Set the name of the DTB to embed in the vmlinux binary 543 Leaving it blank selects the minimal "skeleton" dtb 544 545endmenu # "ARC Architecture Configuration" 546 547config FORCE_MAX_ZONEORDER 548 int "Maximum zone order" 549 default "12" if ARC_HUGEPAGE_16M 550 default "11" 551 552source "kernel/power/Kconfig" 553