xref: /linux/arch/arc/Kconfig (revision bbcd53c960713507ae764bf81970651b5577b95a)
1# SPDX-License-Identifier: GPL-2.0-only
2#
3# Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
4#
5
6config ARC
7	def_bool y
8	select ARC_TIMERS
9	select ARCH_HAS_CACHE_LINE_SIZE
10	select ARCH_HAS_DEBUG_VM_PGTABLE
11	select ARCH_HAS_DMA_PREP_COHERENT
12	select ARCH_HAS_PTE_SPECIAL
13	select ARCH_HAS_SETUP_DMA_OPS
14	select ARCH_HAS_SYNC_DMA_FOR_CPU
15	select ARCH_HAS_SYNC_DMA_FOR_DEVICE
16	select ARCH_SUPPORTS_ATOMIC_RMW if ARC_HAS_LLSC
17	select ARCH_32BIT_OFF_T
18	select BUILDTIME_TABLE_SORT
19	select CLONE_BACKWARDS
20	select COMMON_CLK
21	select DMA_DIRECT_REMAP
22	select GENERIC_ATOMIC64 if !ISA_ARCV2 || !(ARC_HAS_LL64 && ARC_HAS_LLSC)
23	select GENERIC_FIND_FIRST_BIT
24	# for now, we don't need GENERIC_IRQ_PROBE, CONFIG_GENERIC_IRQ_CHIP
25	select GENERIC_IRQ_SHOW
26	select GENERIC_PCI_IOMAP
27	select GENERIC_PENDING_IRQ if SMP
28	select GENERIC_SCHED_CLOCK
29	select GENERIC_SMP_IDLE_THREAD
30	select HAVE_ARCH_KGDB
31	select HAVE_ARCH_TRACEHOOK
32	select HAVE_ARCH_TRANSPARENT_HUGEPAGE if ARC_MMU_V4
33	select HAVE_DEBUG_STACKOVERFLOW
34	select HAVE_DEBUG_KMEMLEAK
35	select HAVE_FUTEX_CMPXCHG if FUTEX
36	select HAVE_IOREMAP_PROT
37	select HAVE_KERNEL_GZIP
38	select HAVE_KERNEL_LZMA
39	select HAVE_KPROBES
40	select HAVE_KRETPROBES
41	select HAVE_MOD_ARCH_SPECIFIC
42	select HAVE_PERF_EVENTS
43	select HANDLE_DOMAIN_IRQ
44	select IRQ_DOMAIN
45	select MODULES_USE_ELF_RELA
46	select OF
47	select OF_EARLY_FLATTREE
48	select PCI_SYSCALL if PCI
49	select PERF_USE_VMALLOC if ARC_CACHE_VIPT_ALIASING
50	select HAVE_ARCH_JUMP_LABEL if ISA_ARCV2 && !CPU_ENDIAN_BE32
51	select SET_FS
52
53config TRACE_IRQFLAGS_SUPPORT
54	def_bool y
55
56config LOCKDEP_SUPPORT
57	def_bool y
58
59config SCHED_OMIT_FRAME_POINTER
60	def_bool y
61
62config GENERIC_CSUM
63	def_bool y
64
65config ARCH_DISCONTIGMEM_ENABLE
66	def_bool n
67	depends on BROKEN
68
69config ARCH_FLATMEM_ENABLE
70	def_bool y
71
72config MMU
73	def_bool y
74
75config NO_IOPORT_MAP
76	def_bool y
77
78config GENERIC_CALIBRATE_DELAY
79	def_bool y
80
81config GENERIC_HWEIGHT
82	def_bool y
83
84config STACKTRACE_SUPPORT
85	def_bool y
86	select STACKTRACE
87
88menu "ARC Architecture Configuration"
89
90menu "ARC Platform/SoC/Board"
91
92source "arch/arc/plat-tb10x/Kconfig"
93source "arch/arc/plat-axs10x/Kconfig"
94source "arch/arc/plat-hsdk/Kconfig"
95
96endmenu
97
98choice
99	prompt "ARC Instruction Set"
100	default ISA_ARCV2
101
102config ISA_ARCOMPACT
103	bool "ARCompact ISA"
104	select CPU_NO_EFFICIENT_FFS
105	help
106	  The original ARC ISA of ARC600/700 cores
107
108config ISA_ARCV2
109	bool "ARC ISA v2"
110	select ARC_TIMERS_64BIT
111	help
112	  ISA for the Next Generation ARC-HS cores
113
114endchoice
115
116menu "ARC CPU Configuration"
117
118choice
119	prompt "ARC Core"
120	default ARC_CPU_770 if ISA_ARCOMPACT
121	default ARC_CPU_HS if ISA_ARCV2
122
123if ISA_ARCOMPACT
124
125config ARC_CPU_750D
126	bool "ARC750D"
127	select ARC_CANT_LLSC
128	help
129	  Support for ARC750 core
130
131config ARC_CPU_770
132	bool "ARC770"
133	select ARC_HAS_SWAPE
134	help
135	  Support for ARC770 core introduced with Rel 4.10 (Summer 2011)
136	  This core has a bunch of cool new features:
137	  -MMU-v3: Variable Page Sz (4k, 8k, 16k), bigger J-TLB (128x4)
138	           Shared Address Spaces (for sharing TLB entries in MMU)
139	  -Caches: New Prog Model, Region Flush
140	  -Insns: endian swap, load-locked/store-conditional, time-stamp-ctr
141
142endif #ISA_ARCOMPACT
143
144config ARC_CPU_HS
145	bool "ARC-HS"
146	depends on ISA_ARCV2
147	help
148	  Support for ARC HS38x Cores based on ARCv2 ISA
149	  The notable features are:
150	    - SMP configurations of up to 4 cores with coherency
151	    - Optional L2 Cache and IO-Coherency
152	    - Revised Interrupt Architecture (multiple priorites, reg banks,
153	        auto stack switch, auto regfile save/restore)
154	    - MMUv4 (PIPT dcache, Huge Pages)
155	    - Instructions for
156		* 64bit load/store: LDD, STD
157		* Hardware assisted divide/remainder: DIV, REM
158		* Function prologue/epilogue: ENTER_S, LEAVE_S
159		* IRQ enable/disable: CLRI, SETI
160		* pop count: FFS, FLS
161		* SETcc, BMSKN, XBFU...
162
163endchoice
164
165config ARC_TUNE_MCPU
166	string "Override default -mcpu compiler flag"
167	default ""
168	help
169	  Override default -mcpu=xxx compiler flag (which is set depending on
170	  the ISA version) with the specified value.
171	  NOTE: If specified flag isn't supported by current compiler the
172	  ISA default value will be used as a fallback.
173
174config CPU_BIG_ENDIAN
175	bool "Enable Big Endian Mode"
176	help
177	  Build kernel for Big Endian Mode of ARC CPU
178
179config SMP
180	bool "Symmetric Multi-Processing"
181	select ARC_MCIP if ISA_ARCV2
182	help
183	  This enables support for systems with more than one CPU.
184
185if SMP
186
187config NR_CPUS
188	int "Maximum number of CPUs (2-4096)"
189	range 2 4096
190	default "4"
191
192config ARC_SMP_HALT_ON_RESET
193	bool "Enable Halt-on-reset boot mode"
194	help
195	  In SMP configuration cores can be configured as Halt-on-reset
196	  or they could all start at same time. For Halt-on-reset, non
197	  masters are parked until Master kicks them so they can start off
198	  at designated entry point. For other case, all jump to common
199	  entry point and spin wait for Master's signal.
200
201endif #SMP
202
203config ARC_MCIP
204	bool "ARConnect Multicore IP (MCIP) Support "
205	depends on ISA_ARCV2
206	default y if SMP
207	help
208	  This IP block enables SMP in ARC-HS38 cores.
209	  It provides for cross-core interrupts, multi-core debug
210	  hardware semaphores, shared memory,....
211
212menuconfig ARC_CACHE
213	bool "Enable Cache Support"
214	default y
215
216if ARC_CACHE
217
218config ARC_CACHE_LINE_SHIFT
219	int "Cache Line Length (as power of 2)"
220	range 5 7
221	default "6"
222	help
223	  Starting with ARC700 4.9, Cache line length is configurable,
224	  This option specifies "N", with Line-len = 2 power N
225	  So line lengths of 32, 64, 128 are specified by 5,6,7, respectively
226	  Linux only supports same line lengths for I and D caches.
227
228config ARC_HAS_ICACHE
229	bool "Use Instruction Cache"
230	default y
231
232config ARC_HAS_DCACHE
233	bool "Use Data Cache"
234	default y
235
236config ARC_CACHE_PAGES
237	bool "Per Page Cache Control"
238	default y
239	depends on ARC_HAS_ICACHE || ARC_HAS_DCACHE
240	help
241	  This can be used to over-ride the global I/D Cache Enable on a
242	  per-page basis (but only for pages accessed via MMU such as
243	  Kernel Virtual address or User Virtual Address)
244	  TLB entries have a per-page Cache Enable Bit.
245	  Note that Global I/D ENABLE + Per Page DISABLE works but corollary
246	  Global DISABLE + Per Page ENABLE won't work
247
248config ARC_CACHE_VIPT_ALIASING
249	bool "Support VIPT Aliasing D$"
250	depends on ARC_HAS_DCACHE && ISA_ARCOMPACT
251
252endif #ARC_CACHE
253
254config ARC_HAS_ICCM
255	bool "Use ICCM"
256	help
257	  Single Cycle RAMS to store Fast Path Code
258
259config ARC_ICCM_SZ
260	int "ICCM Size in KB"
261	default "64"
262	depends on ARC_HAS_ICCM
263
264config ARC_HAS_DCCM
265	bool "Use DCCM"
266	help
267	  Single Cycle RAMS to store Fast Path Data
268
269config ARC_DCCM_SZ
270	int "DCCM Size in KB"
271	default "64"
272	depends on ARC_HAS_DCCM
273
274config ARC_DCCM_BASE
275	hex "DCCM map address"
276	default "0xA0000000"
277	depends on ARC_HAS_DCCM
278
279choice
280	prompt "MMU Version"
281	default ARC_MMU_V3 if ARC_CPU_770
282	default ARC_MMU_V2 if ARC_CPU_750D
283	default ARC_MMU_V4 if ARC_CPU_HS
284
285if ISA_ARCOMPACT
286
287config ARC_MMU_V1
288	bool "MMU v1"
289	help
290	  Orig ARC700 MMU
291
292config ARC_MMU_V2
293	bool "MMU v2"
294	help
295	  Fixed the deficiency of v1 - possible thrashing in memcpy scenario
296	  when 2 D-TLB and 1 I-TLB entries index into same 2way set.
297
298config ARC_MMU_V3
299	bool "MMU v3"
300	depends on ARC_CPU_770
301	help
302	  Introduced with ARC700 4.10: New Features
303	  Variable Page size (1k-16k), var JTLB size 128 x (2 or 4)
304	  Shared Address Spaces (SASID)
305
306endif
307
308config ARC_MMU_V4
309	bool "MMU v4"
310	depends on ISA_ARCV2
311
312endchoice
313
314
315choice
316	prompt "MMU Page Size"
317	default ARC_PAGE_SIZE_8K
318
319config ARC_PAGE_SIZE_8K
320	bool "8KB"
321	help
322	  Choose between 8k vs 16k
323
324config ARC_PAGE_SIZE_16K
325	bool "16KB"
326	depends on ARC_MMU_V3 || ARC_MMU_V4
327
328config ARC_PAGE_SIZE_4K
329	bool "4KB"
330	depends on ARC_MMU_V3 || ARC_MMU_V4
331
332endchoice
333
334choice
335	prompt "MMU Super Page Size"
336	depends on ISA_ARCV2 && TRANSPARENT_HUGEPAGE
337	default ARC_HUGEPAGE_2M
338
339config ARC_HUGEPAGE_2M
340	bool "2MB"
341
342config ARC_HUGEPAGE_16M
343	bool "16MB"
344
345endchoice
346
347config NODES_SHIFT
348	int "Maximum NUMA Nodes (as a power of 2)"
349	default "0" if !DISCONTIGMEM
350	default "1" if DISCONTIGMEM
351	depends on NEED_MULTIPLE_NODES
352	help
353	  Accessing memory beyond 1GB (with or w/o PAE) requires 2 memory
354	  zones.
355
356config ARC_COMPACT_IRQ_LEVELS
357	depends on ISA_ARCOMPACT
358	bool "Setup Timer IRQ as high Priority"
359	# if SMP, LV2 enabled ONLY if ARC implementation has LV2 re-entrancy
360	depends on !SMP
361
362config ARC_FPU_SAVE_RESTORE
363	bool "Enable FPU state persistence across context switch"
364	help
365	  ARCompact FPU has internal registers to assist with Double precision
366	  Floating Point operations. There are control and stauts registers
367	  for floating point exceptions and rounding modes. These are
368	  preserved across task context switch when enabled.
369
370config ARC_CANT_LLSC
371	def_bool n
372
373config ARC_HAS_LLSC
374	bool "Insn: LLOCK/SCOND (efficient atomic ops)"
375	default y
376	depends on !ARC_CANT_LLSC
377
378config ARC_HAS_SWAPE
379	bool "Insn: SWAPE (endian-swap)"
380	default y
381
382if ISA_ARCV2
383
384config ARC_USE_UNALIGNED_MEM_ACCESS
385	bool "Enable unaligned access in HW"
386	default y
387	select HAVE_EFFICIENT_UNALIGNED_ACCESS
388	help
389	  The ARC HS architecture supports unaligned memory access
390	  which is disabled by default. Enable unaligned access in
391	  hardware and use software to use it
392
393config ARC_HAS_LL64
394	bool "Insn: 64bit LDD/STD"
395	help
396	  Enable gcc to generate 64-bit load/store instructions
397	  ISA mandates even/odd registers to allow encoding of two
398	  dest operands with 2 possible source operands.
399	default y
400
401config ARC_HAS_DIV_REM
402	bool "Insn: div, divu, rem, remu"
403	default y
404
405config ARC_HAS_ACCL_REGS
406	bool "Reg Pair ACCL:ACCH (FPU and/or MPY > 6 and/or DSP)"
407	default y
408	help
409	  Depending on the configuration, CPU can contain accumulator reg-pair
410	  (also referred to as r58:r59). These can also be used by gcc as GPR so
411	  kernel needs to save/restore per process
412
413config ARC_DSP_HANDLED
414	def_bool n
415
416config ARC_DSP_SAVE_RESTORE_REGS
417	def_bool n
418
419choice
420	prompt "DSP support"
421	default ARC_DSP_NONE
422	help
423	  Depending on the configuration, CPU can contain DSP registers
424	  (ACC0_GLO, ACC0_GHI, DSP_BFLY0, DSP_CTRL, DSP_FFT_CTRL).
425	  Bellow is options describing how to handle these registers in
426	  interrupt entry / exit and in context switch.
427
428config ARC_DSP_NONE
429	bool "No DSP extension presence in HW"
430	help
431	  No DSP extension presence in HW
432
433config ARC_DSP_KERNEL
434	bool "DSP extension in HW, no support for userspace"
435	select ARC_HAS_ACCL_REGS
436	select ARC_DSP_HANDLED
437	help
438	  DSP extension presence in HW, no support for DSP-enabled userspace
439	  applications. We don't save / restore DSP registers and only do
440	  some minimal preparations so userspace won't be able to break kernel
441
442config ARC_DSP_USERSPACE
443	bool "Support DSP for userspace apps"
444	select ARC_HAS_ACCL_REGS
445	select ARC_DSP_HANDLED
446	select ARC_DSP_SAVE_RESTORE_REGS
447	help
448	  DSP extension presence in HW, support save / restore DSP registers to
449	  run DSP-enabled userspace applications
450
451config ARC_DSP_AGU_USERSPACE
452	bool "Support DSP with AGU for userspace apps"
453	select ARC_HAS_ACCL_REGS
454	select ARC_DSP_HANDLED
455	select ARC_DSP_SAVE_RESTORE_REGS
456	help
457	  DSP and AGU extensions presence in HW, support save / restore DSP
458	  and AGU registers to run DSP-enabled userspace applications
459endchoice
460
461config ARC_IRQ_NO_AUTOSAVE
462	bool "Disable hardware autosave regfile on interrupts"
463	default n
464	help
465	  On HS cores, taken interrupt auto saves the regfile on stack.
466	  This is programmable and can be optionally disabled in which case
467	  software INTERRUPT_PROLOGUE/EPILGUE do the needed work
468
469config ARC_LPB_DISABLE
470	bool "Disable loop buffer (LPB)"
471	help
472	  On HS cores, loop buffer (LPB) is programmable in runtime and can
473	  be optionally disabled.
474
475endif # ISA_ARCV2
476
477endmenu   # "ARC CPU Configuration"
478
479config LINUX_LINK_BASE
480	hex "Kernel link address"
481	default "0x80000000"
482	help
483	  ARC700 divides the 32 bit phy address space into two equal halves
484	  -Lower 2G (0 - 0x7FFF_FFFF ) is user virtual, translated by MMU
485	  -Upper 2G (0x8000_0000 onwards) is untranslated, for kernel
486	  Typically Linux kernel is linked at the start of untransalted addr,
487	  hence the default value of 0x8zs.
488	  However some customers have peripherals mapped at this addr, so
489	  Linux needs to be scooted a bit.
490	  If you don't know what the above means, leave this setting alone.
491	  This needs to match memory start address specified in Device Tree
492
493config LINUX_RAM_BASE
494	hex "RAM base address"
495	default LINUX_LINK_BASE
496	help
497	  By default Linux is linked at base of RAM. However in some special
498	  cases (such as HSDK), Linux can't be linked at start of DDR, hence
499	  this option.
500
501config HIGHMEM
502	bool "High Memory Support"
503	select HAVE_ARCH_PFN_VALID
504	select KMAP_LOCAL
505	help
506	  With ARC 2G:2G address split, only upper 2G is directly addressable by
507	  kernel. Enable this to potentially allow access to rest of 2G and PAE
508	  in future
509
510config ARC_HAS_PAE40
511	bool "Support for the 40-bit Physical Address Extension"
512	depends on ISA_ARCV2
513	select HIGHMEM
514	select PHYS_ADDR_T_64BIT
515	help
516	  Enable access to physical memory beyond 4G, only supported on
517	  ARC cores with 40 bit Physical Addressing support
518
519config ARC_KVADDR_SIZE
520	int "Kernel Virtual Address Space size (MB)"
521	range 0 512
522	default "256"
523	help
524	  The kernel address space is carved out of 256MB of translated address
525	  space for catering to vmalloc, modules, pkmap, fixmap. This however may
526	  not suffice vmalloc requirements of a 4K CPU EZChip system. So allow
527	  this to be stretched to 512 MB (by extending into the reserved
528	  kernel-user gutter)
529
530config ARC_CURR_IN_REG
531	bool "Dedicate Register r25 for current_task pointer"
532	default y
533	help
534	  This reserved Register R25 to point to Current Task in
535	  kernel mode. This saves memory access for each such access
536
537
538config ARC_EMUL_UNALIGNED
539	bool "Emulate unaligned memory access (userspace only)"
540	select SYSCTL_ARCH_UNALIGN_NO_WARN
541	select SYSCTL_ARCH_UNALIGN_ALLOW
542	depends on ISA_ARCOMPACT
543	help
544	  This enables misaligned 16 & 32 bit memory access from user space.
545	  Use ONLY-IF-ABS-NECESSARY as it will be very slow and also can hide
546	  potential bugs in code
547
548config HZ
549	int "Timer Frequency"
550	default 100
551
552config ARC_METAWARE_HLINK
553	bool "Support for Metaware debugger assisted Host access"
554	help
555	  This options allows a Linux userland apps to directly access
556	  host file system (open/creat/read/write etc) with help from
557	  Metaware Debugger. This can come in handy for Linux-host communication
558	  when there is no real usable peripheral such as EMAC.
559
560menuconfig ARC_DBG
561	bool "ARC debugging"
562	default y
563
564if ARC_DBG
565
566config ARC_DW2_UNWIND
567	bool "Enable DWARF specific kernel stack unwind"
568	default y
569	select KALLSYMS
570	help
571	  Compiles the kernel with DWARF unwind information and can be used
572	  to get stack backtraces.
573
574	  If you say Y here the resulting kernel image will be slightly larger
575	  but not slower, and it will give very useful debugging information.
576	  If you don't debug the kernel, you can say N, but we may not be able
577	  to solve problems without frame unwind information
578
579config ARC_DBG_TLB_PARANOIA
580	bool "Paranoia Checks in Low Level TLB Handlers"
581
582config ARC_DBG_JUMP_LABEL
583	bool "Paranoid checks in Static Keys (jump labels) code"
584	depends on JUMP_LABEL
585	default y if STATIC_KEYS_SELFTEST
586	help
587	  Enable paranoid checks and self-test of both ARC-specific and generic
588	  part of static keys (jump labels) related code.
589endif
590
591config ARC_BUILTIN_DTB_NAME
592	string "Built in DTB"
593	help
594	  Set the name of the DTB to embed in the vmlinux binary
595	  Leaving it blank selects the minimal "skeleton" dtb
596
597endmenu	 # "ARC Architecture Configuration"
598
599config FORCE_MAX_ZONEORDER
600	int "Maximum zone order"
601	default "12" if ARC_HUGEPAGE_16M
602	default "11"
603
604source "kernel/power/Kconfig"
605