1# 2# Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com) 3# 4# This program is free software; you can redistribute it and/or modify 5# it under the terms of the GNU General Public License version 2 as 6# published by the Free Software Foundation. 7# 8 9config ARC 10 def_bool y 11 select ARC_TIMERS 12 select ARCH_HAS_DMA_COHERENT_TO_PFN 13 select ARCH_HAS_PTE_SPECIAL 14 select ARCH_HAS_SETUP_DMA_OPS 15 select ARCH_HAS_SYNC_DMA_FOR_CPU 16 select ARCH_HAS_SYNC_DMA_FOR_DEVICE 17 select ARCH_SUPPORTS_ATOMIC_RMW if ARC_HAS_LLSC 18 select ARCH_32BIT_OFF_T 19 select BUILDTIME_EXTABLE_SORT 20 select CLONE_BACKWARDS 21 select COMMON_CLK 22 select GENERIC_ATOMIC64 if !ISA_ARCV2 || !(ARC_HAS_LL64 && ARC_HAS_LLSC) 23 select GENERIC_CLOCKEVENTS 24 select GENERIC_FIND_FIRST_BIT 25 # for now, we don't need GENERIC_IRQ_PROBE, CONFIG_GENERIC_IRQ_CHIP 26 select GENERIC_IRQ_SHOW 27 select GENERIC_PCI_IOMAP 28 select GENERIC_PENDING_IRQ if SMP 29 select GENERIC_SCHED_CLOCK 30 select GENERIC_SMP_IDLE_THREAD 31 select HAVE_ARCH_KGDB 32 select HAVE_ARCH_TRACEHOOK 33 select HAVE_DEBUG_STACKOVERFLOW 34 select HAVE_FUTEX_CMPXCHG if FUTEX 35 select HAVE_IOREMAP_PROT 36 select HAVE_KERNEL_GZIP 37 select HAVE_KERNEL_LZMA 38 select HAVE_KPROBES 39 select HAVE_KRETPROBES 40 select HAVE_MOD_ARCH_SPECIFIC 41 select HAVE_OPROFILE 42 select HAVE_PERF_EVENTS 43 select HANDLE_DOMAIN_IRQ 44 select IRQ_DOMAIN 45 select MODULES_USE_ELF_RELA 46 select OF 47 select OF_EARLY_FLATTREE 48 select PCI_SYSCALL if PCI 49 select PERF_USE_VMALLOC if ARC_CACHE_VIPT_ALIASING 50 51config ARCH_HAS_CACHE_LINE_SIZE 52 def_bool y 53 54config TRACE_IRQFLAGS_SUPPORT 55 def_bool y 56 57config LOCKDEP_SUPPORT 58 def_bool y 59 60config SCHED_OMIT_FRAME_POINTER 61 def_bool y 62 63config GENERIC_CSUM 64 def_bool y 65 66config RWSEM_GENERIC_SPINLOCK 67 def_bool y 68 69config ARCH_DISCONTIGMEM_ENABLE 70 def_bool n 71 72config ARCH_FLATMEM_ENABLE 73 def_bool y 74 75config MMU 76 def_bool y 77 78config NO_IOPORT_MAP 79 def_bool y 80 81config GENERIC_CALIBRATE_DELAY 82 def_bool y 83 84config GENERIC_HWEIGHT 85 def_bool y 86 87config STACKTRACE_SUPPORT 88 def_bool y 89 select STACKTRACE 90 91config HAVE_ARCH_TRANSPARENT_HUGEPAGE 92 def_bool y 93 depends on ARC_MMU_V4 94 95menu "ARC Architecture Configuration" 96 97menu "ARC Platform/SoC/Board" 98 99source "arch/arc/plat-tb10x/Kconfig" 100source "arch/arc/plat-axs10x/Kconfig" 101#New platform adds here 102source "arch/arc/plat-eznps/Kconfig" 103source "arch/arc/plat-hsdk/Kconfig" 104 105endmenu 106 107choice 108 prompt "ARC Instruction Set" 109 default ISA_ARCV2 110 111config ISA_ARCOMPACT 112 bool "ARCompact ISA" 113 select CPU_NO_EFFICIENT_FFS 114 help 115 The original ARC ISA of ARC600/700 cores 116 117config ISA_ARCV2 118 bool "ARC ISA v2" 119 select ARC_TIMERS_64BIT 120 help 121 ISA for the Next Generation ARC-HS cores 122 123endchoice 124 125menu "ARC CPU Configuration" 126 127choice 128 prompt "ARC Core" 129 default ARC_CPU_770 if ISA_ARCOMPACT 130 default ARC_CPU_HS if ISA_ARCV2 131 132if ISA_ARCOMPACT 133 134config ARC_CPU_750D 135 bool "ARC750D" 136 select ARC_CANT_LLSC 137 help 138 Support for ARC750 core 139 140config ARC_CPU_770 141 bool "ARC770" 142 select ARC_HAS_SWAPE 143 help 144 Support for ARC770 core introduced with Rel 4.10 (Summer 2011) 145 This core has a bunch of cool new features: 146 -MMU-v3: Variable Page Sz (4k, 8k, 16k), bigger J-TLB (128x4) 147 Shared Address Spaces (for sharing TLB entries in MMU) 148 -Caches: New Prog Model, Region Flush 149 -Insns: endian swap, load-locked/store-conditional, time-stamp-ctr 150 151endif #ISA_ARCOMPACT 152 153config ARC_CPU_HS 154 bool "ARC-HS" 155 depends on ISA_ARCV2 156 help 157 Support for ARC HS38x Cores based on ARCv2 ISA 158 The notable features are: 159 - SMP configurations of upto 4 core with coherency 160 - Optional L2 Cache and IO-Coherency 161 - Revised Interrupt Architecture (multiple priorites, reg banks, 162 auto stack switch, auto regfile save/restore) 163 - MMUv4 (PIPT dcache, Huge Pages) 164 - Instructions for 165 * 64bit load/store: LDD, STD 166 * Hardware assisted divide/remainder: DIV, REM 167 * Function prologue/epilogue: ENTER_S, LEAVE_S 168 * IRQ enable/disable: CLRI, SETI 169 * pop count: FFS, FLS 170 * SETcc, BMSKN, XBFU... 171 172endchoice 173 174config CPU_BIG_ENDIAN 175 bool "Enable Big Endian Mode" 176 help 177 Build kernel for Big Endian Mode of ARC CPU 178 179config SMP 180 bool "Symmetric Multi-Processing" 181 select ARC_MCIP if ISA_ARCV2 182 help 183 This enables support for systems with more than one CPU. 184 185if SMP 186 187config NR_CPUS 188 int "Maximum number of CPUs (2-4096)" 189 range 2 4096 190 default "4" 191 192config ARC_SMP_HALT_ON_RESET 193 bool "Enable Halt-on-reset boot mode" 194 help 195 In SMP configuration cores can be configured as Halt-on-reset 196 or they could all start at same time. For Halt-on-reset, non 197 masters are parked until Master kicks them so they can start of 198 at designated entry point. For other case, all jump to common 199 entry point and spin wait for Master's signal. 200 201endif #SMP 202 203config ARC_MCIP 204 bool "ARConnect Multicore IP (MCIP) Support " 205 depends on ISA_ARCV2 206 default y if SMP 207 help 208 This IP block enables SMP in ARC-HS38 cores. 209 It provides for cross-core interrupts, multi-core debug 210 hardware semaphores, shared memory,.... 211 212menuconfig ARC_CACHE 213 bool "Enable Cache Support" 214 default y 215 216if ARC_CACHE 217 218config ARC_CACHE_LINE_SHIFT 219 int "Cache Line Length (as power of 2)" 220 range 5 7 221 default "6" 222 help 223 Starting with ARC700 4.9, Cache line length is configurable, 224 This option specifies "N", with Line-len = 2 power N 225 So line lengths of 32, 64, 128 are specified by 5,6,7, respectively 226 Linux only supports same line lengths for I and D caches. 227 228config ARC_HAS_ICACHE 229 bool "Use Instruction Cache" 230 default y 231 232config ARC_HAS_DCACHE 233 bool "Use Data Cache" 234 default y 235 236config ARC_CACHE_PAGES 237 bool "Per Page Cache Control" 238 default y 239 depends on ARC_HAS_ICACHE || ARC_HAS_DCACHE 240 help 241 This can be used to over-ride the global I/D Cache Enable on a 242 per-page basis (but only for pages accessed via MMU such as 243 Kernel Virtual address or User Virtual Address) 244 TLB entries have a per-page Cache Enable Bit. 245 Note that Global I/D ENABLE + Per Page DISABLE works but corollary 246 Global DISABLE + Per Page ENABLE won't work 247 248config ARC_CACHE_VIPT_ALIASING 249 bool "Support VIPT Aliasing D$" 250 depends on ARC_HAS_DCACHE && ISA_ARCOMPACT 251 252endif #ARC_CACHE 253 254config ARC_HAS_ICCM 255 bool "Use ICCM" 256 help 257 Single Cycle RAMS to store Fast Path Code 258 259config ARC_ICCM_SZ 260 int "ICCM Size in KB" 261 default "64" 262 depends on ARC_HAS_ICCM 263 264config ARC_HAS_DCCM 265 bool "Use DCCM" 266 help 267 Single Cycle RAMS to store Fast Path Data 268 269config ARC_DCCM_SZ 270 int "DCCM Size in KB" 271 default "64" 272 depends on ARC_HAS_DCCM 273 274config ARC_DCCM_BASE 275 hex "DCCM map address" 276 default "0xA0000000" 277 depends on ARC_HAS_DCCM 278 279choice 280 prompt "MMU Version" 281 default ARC_MMU_V3 if ARC_CPU_770 282 default ARC_MMU_V2 if ARC_CPU_750D 283 default ARC_MMU_V4 if ARC_CPU_HS 284 285if ISA_ARCOMPACT 286 287config ARC_MMU_V1 288 bool "MMU v1" 289 help 290 Orig ARC700 MMU 291 292config ARC_MMU_V2 293 bool "MMU v2" 294 help 295 Fixed the deficiency of v1 - possible thrashing in memcpy scenario 296 when 2 D-TLB and 1 I-TLB entries index into same 2way set. 297 298config ARC_MMU_V3 299 bool "MMU v3" 300 depends on ARC_CPU_770 301 help 302 Introduced with ARC700 4.10: New Features 303 Variable Page size (1k-16k), var JTLB size 128 x (2 or 4) 304 Shared Address Spaces (SASID) 305 306endif 307 308config ARC_MMU_V4 309 bool "MMU v4" 310 depends on ISA_ARCV2 311 312endchoice 313 314 315choice 316 prompt "MMU Page Size" 317 default ARC_PAGE_SIZE_8K 318 319config ARC_PAGE_SIZE_8K 320 bool "8KB" 321 help 322 Choose between 8k vs 16k 323 324config ARC_PAGE_SIZE_16K 325 bool "16KB" 326 depends on ARC_MMU_V3 || ARC_MMU_V4 327 328config ARC_PAGE_SIZE_4K 329 bool "4KB" 330 depends on ARC_MMU_V3 || ARC_MMU_V4 331 332endchoice 333 334choice 335 prompt "MMU Super Page Size" 336 depends on ISA_ARCV2 && TRANSPARENT_HUGEPAGE 337 default ARC_HUGEPAGE_2M 338 339config ARC_HUGEPAGE_2M 340 bool "2MB" 341 342config ARC_HUGEPAGE_16M 343 bool "16MB" 344 345endchoice 346 347config NODES_SHIFT 348 int "Maximum NUMA Nodes (as a power of 2)" 349 default "0" if !DISCONTIGMEM 350 default "1" if DISCONTIGMEM 351 depends on NEED_MULTIPLE_NODES 352 ---help--- 353 Accessing memory beyond 1GB (with or w/o PAE) requires 2 memory 354 zones. 355 356if ISA_ARCOMPACT 357 358config ARC_COMPACT_IRQ_LEVELS 359 bool "Setup Timer IRQ as high Priority" 360 # if SMP, LV2 enabled ONLY if ARC implementation has LV2 re-entrancy 361 depends on !SMP 362 363config ARC_FPU_SAVE_RESTORE 364 bool "Enable FPU state persistence across context switch" 365 help 366 Double Precision Floating Point unit had dedicated regs which 367 need to be saved/restored across context-switch. 368 Note that ARC FPU is overly simplistic, unlike say x86, which has 369 hardware pieces to allow software to conditionally save/restore, 370 based on actual usage of FPU by a task. Thus our implemn does 371 this for all tasks in system. 372 373endif #ISA_ARCOMPACT 374 375config ARC_CANT_LLSC 376 def_bool n 377 378config ARC_HAS_LLSC 379 bool "Insn: LLOCK/SCOND (efficient atomic ops)" 380 default y 381 depends on !ARC_CANT_LLSC 382 383config ARC_HAS_SWAPE 384 bool "Insn: SWAPE (endian-swap)" 385 default y 386 387if ISA_ARCV2 388 389config ARC_USE_UNALIGNED_MEM_ACCESS 390 bool "Enable unaligned access in HW" 391 default y 392 select HAVE_EFFICIENT_UNALIGNED_ACCESS 393 help 394 The ARC HS architecture supports unaligned memory access 395 which is disabled by default. Enable unaligned access in 396 hardware and use software to use it 397 398config ARC_HAS_LL64 399 bool "Insn: 64bit LDD/STD" 400 help 401 Enable gcc to generate 64-bit load/store instructions 402 ISA mandates even/odd registers to allow encoding of two 403 dest operands with 2 possible source operands. 404 default y 405 406config ARC_HAS_DIV_REM 407 bool "Insn: div, divu, rem, remu" 408 default y 409 410config ARC_HAS_ACCL_REGS 411 bool "Reg Pair ACCL:ACCH (FPU and/or MPY > 6)" 412 default y 413 help 414 Depending on the configuration, CPU can contain accumulator reg-pair 415 (also referred to as r58:r59). These can also be used by gcc as GPR so 416 kernel needs to save/restore per process 417 418config ARC_IRQ_NO_AUTOSAVE 419 bool "Disable hardware autosave regfile on interrupts" 420 default n 421 help 422 On HS cores, taken interrupt auto saves the regfile on stack. 423 This is programmable and can be optionally disabled in which case 424 software INTERRUPT_PROLOGUE/EPILGUE do the needed work 425 426endif # ISA_ARCV2 427 428endmenu # "ARC CPU Configuration" 429 430config LINUX_LINK_BASE 431 hex "Kernel link address" 432 default "0x80000000" 433 help 434 ARC700 divides the 32 bit phy address space into two equal halves 435 -Lower 2G (0 - 0x7FFF_FFFF ) is user virtual, translated by MMU 436 -Upper 2G (0x8000_0000 onwards) is untranslated, for kernel 437 Typically Linux kernel is linked at the start of untransalted addr, 438 hence the default value of 0x8zs. 439 However some customers have peripherals mapped at this addr, so 440 Linux needs to be scooted a bit. 441 If you don't know what the above means, leave this setting alone. 442 This needs to match memory start address specified in Device Tree 443 444config LINUX_RAM_BASE 445 hex "RAM base address" 446 default LINUX_LINK_BASE 447 help 448 By default Linux is linked at base of RAM. However in some special 449 cases (such as HSDK), Linux can't be linked at start of DDR, hence 450 this option. 451 452config HIGHMEM 453 bool "High Memory Support" 454 select ARCH_DISCONTIGMEM_ENABLE 455 help 456 With ARC 2G:2G address split, only upper 2G is directly addressable by 457 kernel. Enable this to potentially allow access to rest of 2G and PAE 458 in future 459 460config ARC_HAS_PAE40 461 bool "Support for the 40-bit Physical Address Extension" 462 depends on ISA_ARCV2 463 select HIGHMEM 464 select PHYS_ADDR_T_64BIT 465 help 466 Enable access to physical memory beyond 4G, only supported on 467 ARC cores with 40 bit Physical Addressing support 468 469config ARC_KVADDR_SIZE 470 int "Kernel Virtual Address Space size (MB)" 471 range 0 512 472 default "256" 473 help 474 The kernel address space is carved out of 256MB of translated address 475 space for catering to vmalloc, modules, pkmap, fixmap. This however may 476 not suffice vmalloc requirements of a 4K CPU EZChip system. So allow 477 this to be stretched to 512 MB (by extending into the reserved 478 kernel-user gutter) 479 480config ARC_CURR_IN_REG 481 bool "Dedicate Register r25 for current_task pointer" 482 default y 483 help 484 This reserved Register R25 to point to Current Task in 485 kernel mode. This saves memory access for each such access 486 487 488config ARC_EMUL_UNALIGNED 489 bool "Emulate unaligned memory access (userspace only)" 490 select SYSCTL_ARCH_UNALIGN_NO_WARN 491 select SYSCTL_ARCH_UNALIGN_ALLOW 492 depends on ISA_ARCOMPACT 493 help 494 This enables misaligned 16 & 32 bit memory access from user space. 495 Use ONLY-IF-ABS-NECESSARY as it will be very slow and also can hide 496 potential bugs in code 497 498config HZ 499 int "Timer Frequency" 500 default 100 501 502config ARC_METAWARE_HLINK 503 bool "Support for Metaware debugger assisted Host access" 504 help 505 This options allows a Linux userland apps to directly access 506 host file system (open/creat/read/write etc) with help from 507 Metaware Debugger. This can come in handy for Linux-host communication 508 when there is no real usable peripheral such as EMAC. 509 510menuconfig ARC_DBG 511 bool "ARC debugging" 512 default y 513 514if ARC_DBG 515 516config ARC_DW2_UNWIND 517 bool "Enable DWARF specific kernel stack unwind" 518 default y 519 select KALLSYMS 520 help 521 Compiles the kernel with DWARF unwind information and can be used 522 to get stack backtraces. 523 524 If you say Y here the resulting kernel image will be slightly larger 525 but not slower, and it will give very useful debugging information. 526 If you don't debug the kernel, you can say N, but we may not be able 527 to solve problems without frame unwind information 528 529config ARC_DBG_TLB_PARANOIA 530 bool "Paranoia Checks in Low Level TLB Handlers" 531 532endif 533 534config ARC_BUILTIN_DTB_NAME 535 string "Built in DTB" 536 help 537 Set the name of the DTB to embed in the vmlinux binary 538 Leaving it blank selects the minimal "skeleton" dtb 539 540endmenu # "ARC Architecture Configuration" 541 542config FORCE_MAX_ZONEORDER 543 int "Maximum zone order" 544 default "12" if ARC_HUGEPAGE_16M 545 default "11" 546 547source "kernel/power/Kconfig" 548