1# 2# Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com) 3# 4# This program is free software; you can redistribute it and/or modify 5# it under the terms of the GNU General Public License version 2 as 6# published by the Free Software Foundation. 7# 8 9config ARC 10 def_bool y 11 select ARC_TIMERS 12 select ARCH_HAS_DMA_COHERENT_TO_PFN 13 select ARCH_HAS_PTE_SPECIAL 14 select ARCH_HAS_SYNC_DMA_FOR_CPU 15 select ARCH_HAS_SYNC_DMA_FOR_DEVICE 16 select ARCH_SUPPORTS_ATOMIC_RMW if ARC_HAS_LLSC 17 select ARCH_32BIT_OFF_T 18 select BUILDTIME_EXTABLE_SORT 19 select CLONE_BACKWARDS 20 select COMMON_CLK 21 select GENERIC_ATOMIC64 if !ISA_ARCV2 || !(ARC_HAS_LL64 && ARC_HAS_LLSC) 22 select GENERIC_CLOCKEVENTS 23 select GENERIC_FIND_FIRST_BIT 24 # for now, we don't need GENERIC_IRQ_PROBE, CONFIG_GENERIC_IRQ_CHIP 25 select GENERIC_IRQ_SHOW 26 select GENERIC_PCI_IOMAP 27 select GENERIC_PENDING_IRQ if SMP 28 select GENERIC_SCHED_CLOCK 29 select GENERIC_SMP_IDLE_THREAD 30 select HAVE_ARCH_KGDB 31 select HAVE_ARCH_TRACEHOOK 32 select HAVE_DEBUG_STACKOVERFLOW 33 select HAVE_FUTEX_CMPXCHG if FUTEX 34 select HAVE_GENERIC_DMA_COHERENT 35 select HAVE_IOREMAP_PROT 36 select HAVE_KERNEL_GZIP 37 select HAVE_KERNEL_LZMA 38 select HAVE_KPROBES 39 select HAVE_KRETPROBES 40 select HAVE_MOD_ARCH_SPECIFIC 41 select HAVE_OPROFILE 42 select HAVE_PERF_EVENTS 43 select HANDLE_DOMAIN_IRQ 44 select IRQ_DOMAIN 45 select MODULES_USE_ELF_RELA 46 select OF 47 select OF_EARLY_FLATTREE 48 select OF_RESERVED_MEM 49 select PCI_SYSCALL if PCI 50 select PERF_USE_VMALLOC if ARC_CACHE_VIPT_ALIASING 51 52config ARCH_HAS_CACHE_LINE_SIZE 53 def_bool y 54 55config TRACE_IRQFLAGS_SUPPORT 56 def_bool y 57 58config LOCKDEP_SUPPORT 59 def_bool y 60 61config SCHED_OMIT_FRAME_POINTER 62 def_bool y 63 64config GENERIC_CSUM 65 def_bool y 66 67config RWSEM_GENERIC_SPINLOCK 68 def_bool y 69 70config ARCH_DISCONTIGMEM_ENABLE 71 def_bool n 72 73config ARCH_FLATMEM_ENABLE 74 def_bool y 75 76config MMU 77 def_bool y 78 79config NO_IOPORT_MAP 80 def_bool y 81 82config GENERIC_CALIBRATE_DELAY 83 def_bool y 84 85config GENERIC_HWEIGHT 86 def_bool y 87 88config STACKTRACE_SUPPORT 89 def_bool y 90 select STACKTRACE 91 92config HAVE_ARCH_TRANSPARENT_HUGEPAGE 93 def_bool y 94 depends on ARC_MMU_V4 95 96menu "ARC Architecture Configuration" 97 98menu "ARC Platform/SoC/Board" 99 100source "arch/arc/plat-tb10x/Kconfig" 101source "arch/arc/plat-axs10x/Kconfig" 102#New platform adds here 103source "arch/arc/plat-eznps/Kconfig" 104source "arch/arc/plat-hsdk/Kconfig" 105 106endmenu 107 108choice 109 prompt "ARC Instruction Set" 110 default ISA_ARCV2 111 112config ISA_ARCOMPACT 113 bool "ARCompact ISA" 114 select CPU_NO_EFFICIENT_FFS 115 help 116 The original ARC ISA of ARC600/700 cores 117 118config ISA_ARCV2 119 bool "ARC ISA v2" 120 select ARC_TIMERS_64BIT 121 help 122 ISA for the Next Generation ARC-HS cores 123 124endchoice 125 126menu "ARC CPU Configuration" 127 128choice 129 prompt "ARC Core" 130 default ARC_CPU_770 if ISA_ARCOMPACT 131 default ARC_CPU_HS if ISA_ARCV2 132 133if ISA_ARCOMPACT 134 135config ARC_CPU_750D 136 bool "ARC750D" 137 select ARC_CANT_LLSC 138 help 139 Support for ARC750 core 140 141config ARC_CPU_770 142 bool "ARC770" 143 select ARC_HAS_SWAPE 144 help 145 Support for ARC770 core introduced with Rel 4.10 (Summer 2011) 146 This core has a bunch of cool new features: 147 -MMU-v3: Variable Page Sz (4k, 8k, 16k), bigger J-TLB (128x4) 148 Shared Address Spaces (for sharing TLB entries in MMU) 149 -Caches: New Prog Model, Region Flush 150 -Insns: endian swap, load-locked/store-conditional, time-stamp-ctr 151 152endif #ISA_ARCOMPACT 153 154config ARC_CPU_HS 155 bool "ARC-HS" 156 depends on ISA_ARCV2 157 help 158 Support for ARC HS38x Cores based on ARCv2 ISA 159 The notable features are: 160 - SMP configurations of upto 4 core with coherency 161 - Optional L2 Cache and IO-Coherency 162 - Revised Interrupt Architecture (multiple priorites, reg banks, 163 auto stack switch, auto regfile save/restore) 164 - MMUv4 (PIPT dcache, Huge Pages) 165 - Instructions for 166 * 64bit load/store: LDD, STD 167 * Hardware assisted divide/remainder: DIV, REM 168 * Function prologue/epilogue: ENTER_S, LEAVE_S 169 * IRQ enable/disable: CLRI, SETI 170 * pop count: FFS, FLS 171 * SETcc, BMSKN, XBFU... 172 173endchoice 174 175config CPU_BIG_ENDIAN 176 bool "Enable Big Endian Mode" 177 help 178 Build kernel for Big Endian Mode of ARC CPU 179 180config SMP 181 bool "Symmetric Multi-Processing" 182 select ARC_MCIP if ISA_ARCV2 183 help 184 This enables support for systems with more than one CPU. 185 186if SMP 187 188config NR_CPUS 189 int "Maximum number of CPUs (2-4096)" 190 range 2 4096 191 default "4" 192 193config ARC_SMP_HALT_ON_RESET 194 bool "Enable Halt-on-reset boot mode" 195 default y if ARC_UBOOT_SUPPORT 196 help 197 In SMP configuration cores can be configured as Halt-on-reset 198 or they could all start at same time. For Halt-on-reset, non 199 masters are parked until Master kicks them so they can start of 200 at designated entry point. For other case, all jump to common 201 entry point and spin wait for Master's signal. 202 203endif #SMP 204 205config ARC_MCIP 206 bool "ARConnect Multicore IP (MCIP) Support " 207 depends on ISA_ARCV2 208 default y if SMP 209 help 210 This IP block enables SMP in ARC-HS38 cores. 211 It provides for cross-core interrupts, multi-core debug 212 hardware semaphores, shared memory,.... 213 214menuconfig ARC_CACHE 215 bool "Enable Cache Support" 216 default y 217 218if ARC_CACHE 219 220config ARC_CACHE_LINE_SHIFT 221 int "Cache Line Length (as power of 2)" 222 range 5 7 223 default "6" 224 help 225 Starting with ARC700 4.9, Cache line length is configurable, 226 This option specifies "N", with Line-len = 2 power N 227 So line lengths of 32, 64, 128 are specified by 5,6,7, respectively 228 Linux only supports same line lengths for I and D caches. 229 230config ARC_HAS_ICACHE 231 bool "Use Instruction Cache" 232 default y 233 234config ARC_HAS_DCACHE 235 bool "Use Data Cache" 236 default y 237 238config ARC_CACHE_PAGES 239 bool "Per Page Cache Control" 240 default y 241 depends on ARC_HAS_ICACHE || ARC_HAS_DCACHE 242 help 243 This can be used to over-ride the global I/D Cache Enable on a 244 per-page basis (but only for pages accessed via MMU such as 245 Kernel Virtual address or User Virtual Address) 246 TLB entries have a per-page Cache Enable Bit. 247 Note that Global I/D ENABLE + Per Page DISABLE works but corollary 248 Global DISABLE + Per Page ENABLE won't work 249 250config ARC_CACHE_VIPT_ALIASING 251 bool "Support VIPT Aliasing D$" 252 depends on ARC_HAS_DCACHE && ISA_ARCOMPACT 253 254endif #ARC_CACHE 255 256config ARC_HAS_ICCM 257 bool "Use ICCM" 258 help 259 Single Cycle RAMS to store Fast Path Code 260 261config ARC_ICCM_SZ 262 int "ICCM Size in KB" 263 default "64" 264 depends on ARC_HAS_ICCM 265 266config ARC_HAS_DCCM 267 bool "Use DCCM" 268 help 269 Single Cycle RAMS to store Fast Path Data 270 271config ARC_DCCM_SZ 272 int "DCCM Size in KB" 273 default "64" 274 depends on ARC_HAS_DCCM 275 276config ARC_DCCM_BASE 277 hex "DCCM map address" 278 default "0xA0000000" 279 depends on ARC_HAS_DCCM 280 281choice 282 prompt "MMU Version" 283 default ARC_MMU_V3 if ARC_CPU_770 284 default ARC_MMU_V2 if ARC_CPU_750D 285 default ARC_MMU_V4 if ARC_CPU_HS 286 287if ISA_ARCOMPACT 288 289config ARC_MMU_V1 290 bool "MMU v1" 291 help 292 Orig ARC700 MMU 293 294config ARC_MMU_V2 295 bool "MMU v2" 296 help 297 Fixed the deficiency of v1 - possible thrashing in memcpy scenario 298 when 2 D-TLB and 1 I-TLB entries index into same 2way set. 299 300config ARC_MMU_V3 301 bool "MMU v3" 302 depends on ARC_CPU_770 303 help 304 Introduced with ARC700 4.10: New Features 305 Variable Page size (1k-16k), var JTLB size 128 x (2 or 4) 306 Shared Address Spaces (SASID) 307 308endif 309 310config ARC_MMU_V4 311 bool "MMU v4" 312 depends on ISA_ARCV2 313 314endchoice 315 316 317choice 318 prompt "MMU Page Size" 319 default ARC_PAGE_SIZE_8K 320 321config ARC_PAGE_SIZE_8K 322 bool "8KB" 323 help 324 Choose between 8k vs 16k 325 326config ARC_PAGE_SIZE_16K 327 bool "16KB" 328 depends on ARC_MMU_V3 || ARC_MMU_V4 329 330config ARC_PAGE_SIZE_4K 331 bool "4KB" 332 depends on ARC_MMU_V3 || ARC_MMU_V4 333 334endchoice 335 336choice 337 prompt "MMU Super Page Size" 338 depends on ISA_ARCV2 && TRANSPARENT_HUGEPAGE 339 default ARC_HUGEPAGE_2M 340 341config ARC_HUGEPAGE_2M 342 bool "2MB" 343 344config ARC_HUGEPAGE_16M 345 bool "16MB" 346 347endchoice 348 349config NODES_SHIFT 350 int "Maximum NUMA Nodes (as a power of 2)" 351 default "0" if !DISCONTIGMEM 352 default "1" if DISCONTIGMEM 353 depends on NEED_MULTIPLE_NODES 354 ---help--- 355 Accessing memory beyond 1GB (with or w/o PAE) requires 2 memory 356 zones. 357 358if ISA_ARCOMPACT 359 360config ARC_COMPACT_IRQ_LEVELS 361 bool "Setup Timer IRQ as high Priority" 362 # if SMP, LV2 enabled ONLY if ARC implementation has LV2 re-entrancy 363 depends on !SMP 364 365config ARC_FPU_SAVE_RESTORE 366 bool "Enable FPU state persistence across context switch" 367 help 368 Double Precision Floating Point unit had dedicated regs which 369 need to be saved/restored across context-switch. 370 Note that ARC FPU is overly simplistic, unlike say x86, which has 371 hardware pieces to allow software to conditionally save/restore, 372 based on actual usage of FPU by a task. Thus our implemn does 373 this for all tasks in system. 374 375endif #ISA_ARCOMPACT 376 377config ARC_CANT_LLSC 378 def_bool n 379 380config ARC_HAS_LLSC 381 bool "Insn: LLOCK/SCOND (efficient atomic ops)" 382 default y 383 depends on !ARC_CANT_LLSC 384 385config ARC_HAS_SWAPE 386 bool "Insn: SWAPE (endian-swap)" 387 default y 388 389if ISA_ARCV2 390 391config ARC_HAS_LL64 392 bool "Insn: 64bit LDD/STD" 393 help 394 Enable gcc to generate 64-bit load/store instructions 395 ISA mandates even/odd registers to allow encoding of two 396 dest operands with 2 possible source operands. 397 default y 398 399config ARC_HAS_DIV_REM 400 bool "Insn: div, divu, rem, remu" 401 default y 402 403config ARC_HAS_ACCL_REGS 404 bool "Reg Pair ACCL:ACCH (FPU and/or MPY > 6)" 405 default y 406 help 407 Depending on the configuration, CPU can contain accumulator reg-pair 408 (also referred to as r58:r59). These can also be used by gcc as GPR so 409 kernel needs to save/restore per process 410 411endif # ISA_ARCV2 412 413endmenu # "ARC CPU Configuration" 414 415config LINUX_LINK_BASE 416 hex "Kernel link address" 417 default "0x80000000" 418 help 419 ARC700 divides the 32 bit phy address space into two equal halves 420 -Lower 2G (0 - 0x7FFF_FFFF ) is user virtual, translated by MMU 421 -Upper 2G (0x8000_0000 onwards) is untranslated, for kernel 422 Typically Linux kernel is linked at the start of untransalted addr, 423 hence the default value of 0x8zs. 424 However some customers have peripherals mapped at this addr, so 425 Linux needs to be scooted a bit. 426 If you don't know what the above means, leave this setting alone. 427 This needs to match memory start address specified in Device Tree 428 429config LINUX_RAM_BASE 430 hex "RAM base address" 431 default LINUX_LINK_BASE 432 help 433 By default Linux is linked at base of RAM. However in some special 434 cases (such as HSDK), Linux can't be linked at start of DDR, hence 435 this option. 436 437config HIGHMEM 438 bool "High Memory Support" 439 select ARCH_DISCONTIGMEM_ENABLE 440 help 441 With ARC 2G:2G address split, only upper 2G is directly addressable by 442 kernel. Enable this to potentially allow access to rest of 2G and PAE 443 in future 444 445config ARC_HAS_PAE40 446 bool "Support for the 40-bit Physical Address Extension" 447 depends on ISA_ARCV2 448 select HIGHMEM 449 select PHYS_ADDR_T_64BIT 450 help 451 Enable access to physical memory beyond 4G, only supported on 452 ARC cores with 40 bit Physical Addressing support 453 454config ARC_KVADDR_SIZE 455 int "Kernel Virtual Address Space size (MB)" 456 range 0 512 457 default "256" 458 help 459 The kernel address space is carved out of 256MB of translated address 460 space for catering to vmalloc, modules, pkmap, fixmap. This however may 461 not suffice vmalloc requirements of a 4K CPU EZChip system. So allow 462 this to be stretched to 512 MB (by extending into the reserved 463 kernel-user gutter) 464 465config ARC_CURR_IN_REG 466 bool "Dedicate Register r25 for current_task pointer" 467 default y 468 help 469 This reserved Register R25 to point to Current Task in 470 kernel mode. This saves memory access for each such access 471 472 473config ARC_EMUL_UNALIGNED 474 bool "Emulate unaligned memory access (userspace only)" 475 select SYSCTL_ARCH_UNALIGN_NO_WARN 476 select SYSCTL_ARCH_UNALIGN_ALLOW 477 depends on ISA_ARCOMPACT 478 help 479 This enables misaligned 16 & 32 bit memory access from user space. 480 Use ONLY-IF-ABS-NECESSARY as it will be very slow and also can hide 481 potential bugs in code 482 483config HZ 484 int "Timer Frequency" 485 default 100 486 487config ARC_METAWARE_HLINK 488 bool "Support for Metaware debugger assisted Host access" 489 help 490 This options allows a Linux userland apps to directly access 491 host file system (open/creat/read/write etc) with help from 492 Metaware Debugger. This can come in handy for Linux-host communication 493 when there is no real usable peripheral such as EMAC. 494 495menuconfig ARC_DBG 496 bool "ARC debugging" 497 default y 498 499if ARC_DBG 500 501config ARC_DW2_UNWIND 502 bool "Enable DWARF specific kernel stack unwind" 503 default y 504 select KALLSYMS 505 help 506 Compiles the kernel with DWARF unwind information and can be used 507 to get stack backtraces. 508 509 If you say Y here the resulting kernel image will be slightly larger 510 but not slower, and it will give very useful debugging information. 511 If you don't debug the kernel, you can say N, but we may not be able 512 to solve problems without frame unwind information 513 514config ARC_DBG_TLB_PARANOIA 515 bool "Paranoia Checks in Low Level TLB Handlers" 516 517endif 518 519config ARC_UBOOT_SUPPORT 520 bool "Support uboot arg Handling" 521 help 522 ARC Linux by default checks for uboot provided args as pointers to 523 external cmdline or DTB. This however breaks in absence of uboot, 524 when booting from Metaware debugger directly, as the registers are 525 not zeroed out on reset by mdb and/or ARCv2 based cores. The bogus 526 registers look like uboot args to kernel which then chokes. 527 So only enable the uboot arg checking/processing if users are sure 528 of uboot being in play. 529 530config ARC_BUILTIN_DTB_NAME 531 string "Built in DTB" 532 help 533 Set the name of the DTB to embed in the vmlinux binary 534 Leaving it blank selects the minimal "skeleton" dtb 535 536endmenu # "ARC Architecture Configuration" 537 538config FORCE_MAX_ZONEORDER 539 int "Maximum zone order" 540 default "12" if ARC_HUGEPAGE_16M 541 default "11" 542 543source "kernel/power/Kconfig" 544