1# 2# Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com) 3# 4# This program is free software; you can redistribute it and/or modify 5# it under the terms of the GNU General Public License version 2 as 6# published by the Free Software Foundation. 7# 8 9config ARC 10 def_bool y 11 select ARC_TIMERS 12 select ARCH_HAS_SG_CHAIN 13 select ARCH_SUPPORTS_ATOMIC_RMW if ARC_HAS_LLSC 14 select BUILDTIME_EXTABLE_SORT 15 select CLONE_BACKWARDS 16 select COMMON_CLK 17 select GENERIC_ATOMIC64 if !ISA_ARCV2 || !(ARC_HAS_LL64 && ARC_HAS_LLSC) 18 select GENERIC_CLOCKEVENTS 19 select GENERIC_FIND_FIRST_BIT 20 # for now, we don't need GENERIC_IRQ_PROBE, CONFIG_GENERIC_IRQ_CHIP 21 select GENERIC_IRQ_SHOW 22 select GENERIC_PCI_IOMAP 23 select GENERIC_PENDING_IRQ if SMP 24 select GENERIC_SMP_IDLE_THREAD 25 select HAVE_ARCH_KGDB 26 select HAVE_ARCH_TRACEHOOK 27 select HAVE_FUTEX_CMPXCHG 28 select HAVE_IOREMAP_PROT 29 select HAVE_KPROBES 30 select HAVE_KRETPROBES 31 select HAVE_MEMBLOCK 32 select HAVE_MOD_ARCH_SPECIFIC 33 select HAVE_OPROFILE 34 select HAVE_PERF_EVENTS 35 select HANDLE_DOMAIN_IRQ 36 select IRQ_DOMAIN 37 select MODULES_USE_ELF_RELA 38 select NO_BOOTMEM 39 select OF 40 select OF_EARLY_FLATTREE 41 select OF_RESERVED_MEM 42 select PERF_USE_VMALLOC 43 select HAVE_DEBUG_STACKOVERFLOW 44 select HAVE_GENERIC_DMA_COHERENT 45 select HAVE_KERNEL_GZIP 46 select HAVE_KERNEL_LZMA 47 48config MIGHT_HAVE_PCI 49 bool 50 51config TRACE_IRQFLAGS_SUPPORT 52 def_bool y 53 54config LOCKDEP_SUPPORT 55 def_bool y 56 57config SCHED_OMIT_FRAME_POINTER 58 def_bool y 59 60config GENERIC_CSUM 61 def_bool y 62 63config RWSEM_GENERIC_SPINLOCK 64 def_bool y 65 66config ARCH_DISCONTIGMEM_ENABLE 67 def_bool n 68 69config ARCH_FLATMEM_ENABLE 70 def_bool y 71 72config MMU 73 def_bool y 74 75config NO_IOPORT_MAP 76 def_bool y 77 78config GENERIC_CALIBRATE_DELAY 79 def_bool y 80 81config GENERIC_HWEIGHT 82 def_bool y 83 84config STACKTRACE_SUPPORT 85 def_bool y 86 select STACKTRACE 87 88config HAVE_ARCH_TRANSPARENT_HUGEPAGE 89 def_bool y 90 depends on ARC_MMU_V4 91 92source "init/Kconfig" 93source "kernel/Kconfig.freezer" 94 95menu "ARC Architecture Configuration" 96 97menu "ARC Platform/SoC/Board" 98 99source "arch/arc/plat-sim/Kconfig" 100source "arch/arc/plat-tb10x/Kconfig" 101source "arch/arc/plat-axs10x/Kconfig" 102#New platform adds here 103source "arch/arc/plat-eznps/Kconfig" 104 105endmenu 106 107choice 108 prompt "ARC Instruction Set" 109 default ISA_ARCOMPACT 110 111config ISA_ARCOMPACT 112 bool "ARCompact ISA" 113 select CPU_NO_EFFICIENT_FFS 114 help 115 The original ARC ISA of ARC600/700 cores 116 117config ISA_ARCV2 118 bool "ARC ISA v2" 119 select ARC_TIMERS_64BIT 120 help 121 ISA for the Next Generation ARC-HS cores 122 123endchoice 124 125menu "ARC CPU Configuration" 126 127choice 128 prompt "ARC Core" 129 default ARC_CPU_770 if ISA_ARCOMPACT 130 default ARC_CPU_HS if ISA_ARCV2 131 132if ISA_ARCOMPACT 133 134config ARC_CPU_750D 135 bool "ARC750D" 136 select ARC_CANT_LLSC 137 help 138 Support for ARC750 core 139 140config ARC_CPU_770 141 bool "ARC770" 142 select ARC_HAS_SWAPE 143 help 144 Support for ARC770 core introduced with Rel 4.10 (Summer 2011) 145 This core has a bunch of cool new features: 146 -MMU-v3: Variable Page Sz (4k, 8k, 16k), bigger J-TLB (128x4) 147 Shared Address Spaces (for sharing TLB entires in MMU) 148 -Caches: New Prog Model, Region Flush 149 -Insns: endian swap, load-locked/store-conditional, time-stamp-ctr 150 151endif #ISA_ARCOMPACT 152 153config ARC_CPU_HS 154 bool "ARC-HS" 155 depends on ISA_ARCV2 156 help 157 Support for ARC HS38x Cores based on ARCv2 ISA 158 The notable features are: 159 - SMP configurations of upto 4 core with coherency 160 - Optional L2 Cache and IO-Coherency 161 - Revised Interrupt Architecture (multiple priorites, reg banks, 162 auto stack switch, auto regfile save/restore) 163 - MMUv4 (PIPT dcache, Huge Pages) 164 - Instructions for 165 * 64bit load/store: LDD, STD 166 * Hardware assisted divide/remainder: DIV, REM 167 * Function prologue/epilogue: ENTER_S, LEAVE_S 168 * IRQ enable/disable: CLRI, SETI 169 * pop count: FFS, FLS 170 * SETcc, BMSKN, XBFU... 171 172endchoice 173 174config CPU_BIG_ENDIAN 175 bool "Enable Big Endian Mode" 176 default n 177 help 178 Build kernel for Big Endian Mode of ARC CPU 179 180config SMP 181 bool "Symmetric Multi-Processing" 182 default n 183 select ARC_HAS_COH_CACHES if ISA_ARCV2 184 select ARC_MCIP if ISA_ARCV2 185 help 186 This enables support for systems with more than one CPU. 187 188if SMP 189 190config ARC_HAS_COH_CACHES 191 def_bool n 192 193config NR_CPUS 194 int "Maximum number of CPUs (2-4096)" 195 range 2 4096 196 default "4" 197 198config ARC_SMP_HALT_ON_RESET 199 bool "Enable Halt-on-reset boot mode" 200 default y if ARC_UBOOT_SUPPORT 201 help 202 In SMP configuration cores can be configured as Halt-on-reset 203 or they could all start at same time. For Halt-on-reset, non 204 masters are parked until Master kicks them so they can start of 205 at designated entry point. For other case, all jump to common 206 entry point and spin wait for Master's signal. 207 208endif #SMP 209 210config ARC_MCIP 211 bool "ARConnect Multicore IP (MCIP) Support " 212 depends on ISA_ARCV2 213 default y if SMP 214 help 215 This IP block enables SMP in ARC-HS38 cores. 216 It provides for cross-core interrupts, multi-core debug 217 hardware semaphores, shared memory,.... 218 219menuconfig ARC_CACHE 220 bool "Enable Cache Support" 221 default y 222 # if SMP, cache enabled ONLY if ARC implementation has cache coherency 223 depends on !SMP || ARC_HAS_COH_CACHES 224 225if ARC_CACHE 226 227config ARC_CACHE_LINE_SHIFT 228 int "Cache Line Length (as power of 2)" 229 range 5 7 230 default "6" 231 help 232 Starting with ARC700 4.9, Cache line length is configurable, 233 This option specifies "N", with Line-len = 2 power N 234 So line lengths of 32, 64, 128 are specified by 5,6,7, respectively 235 Linux only supports same line lengths for I and D caches. 236 237config ARC_HAS_ICACHE 238 bool "Use Instruction Cache" 239 default y 240 241config ARC_HAS_DCACHE 242 bool "Use Data Cache" 243 default y 244 245config ARC_CACHE_PAGES 246 bool "Per Page Cache Control" 247 default y 248 depends on ARC_HAS_ICACHE || ARC_HAS_DCACHE 249 help 250 This can be used to over-ride the global I/D Cache Enable on a 251 per-page basis (but only for pages accessed via MMU such as 252 Kernel Virtual address or User Virtual Address) 253 TLB entries have a per-page Cache Enable Bit. 254 Note that Global I/D ENABLE + Per Page DISABLE works but corollary 255 Global DISABLE + Per Page ENABLE won't work 256 257config ARC_CACHE_VIPT_ALIASING 258 bool "Support VIPT Aliasing D$" 259 depends on ARC_HAS_DCACHE && ISA_ARCOMPACT 260 default n 261 262endif #ARC_CACHE 263 264config ARC_HAS_ICCM 265 bool "Use ICCM" 266 help 267 Single Cycle RAMS to store Fast Path Code 268 default n 269 270config ARC_ICCM_SZ 271 int "ICCM Size in KB" 272 default "64" 273 depends on ARC_HAS_ICCM 274 275config ARC_HAS_DCCM 276 bool "Use DCCM" 277 help 278 Single Cycle RAMS to store Fast Path Data 279 default n 280 281config ARC_DCCM_SZ 282 int "DCCM Size in KB" 283 default "64" 284 depends on ARC_HAS_DCCM 285 286config ARC_DCCM_BASE 287 hex "DCCM map address" 288 default "0xA0000000" 289 depends on ARC_HAS_DCCM 290 291choice 292 prompt "MMU Version" 293 default ARC_MMU_V3 if ARC_CPU_770 294 default ARC_MMU_V2 if ARC_CPU_750D 295 default ARC_MMU_V4 if ARC_CPU_HS 296 297if ISA_ARCOMPACT 298 299config ARC_MMU_V1 300 bool "MMU v1" 301 help 302 Orig ARC700 MMU 303 304config ARC_MMU_V2 305 bool "MMU v2" 306 help 307 Fixed the deficiency of v1 - possible thrashing in memcpy sceanrio 308 when 2 D-TLB and 1 I-TLB entries index into same 2way set. 309 310config ARC_MMU_V3 311 bool "MMU v3" 312 depends on ARC_CPU_770 313 help 314 Introduced with ARC700 4.10: New Features 315 Variable Page size (1k-16k), var JTLB size 128 x (2 or 4) 316 Shared Address Spaces (SASID) 317 318endif 319 320config ARC_MMU_V4 321 bool "MMU v4" 322 depends on ISA_ARCV2 323 324endchoice 325 326 327choice 328 prompt "MMU Page Size" 329 default ARC_PAGE_SIZE_8K 330 331config ARC_PAGE_SIZE_8K 332 bool "8KB" 333 help 334 Choose between 8k vs 16k 335 336config ARC_PAGE_SIZE_16K 337 bool "16KB" 338 depends on ARC_MMU_V3 || ARC_MMU_V4 339 340config ARC_PAGE_SIZE_4K 341 bool "4KB" 342 depends on ARC_MMU_V3 || ARC_MMU_V4 343 344endchoice 345 346choice 347 prompt "MMU Super Page Size" 348 depends on ISA_ARCV2 && TRANSPARENT_HUGEPAGE 349 default ARC_HUGEPAGE_2M 350 351config ARC_HUGEPAGE_2M 352 bool "2MB" 353 354config ARC_HUGEPAGE_16M 355 bool "16MB" 356 357endchoice 358 359config NODES_SHIFT 360 int "Maximum NUMA Nodes (as a power of 2)" 361 default "0" if !DISCONTIGMEM 362 default "1" if DISCONTIGMEM 363 depends on NEED_MULTIPLE_NODES 364 ---help--- 365 Accessing memory beyond 1GB (with or w/o PAE) requires 2 memory 366 zones. 367 368if ISA_ARCOMPACT 369 370config ARC_COMPACT_IRQ_LEVELS 371 bool "Setup Timer IRQ as high Priority" 372 default n 373 # if SMP, LV2 enabled ONLY if ARC implementation has LV2 re-entrancy 374 depends on !SMP 375 376config ARC_FPU_SAVE_RESTORE 377 bool "Enable FPU state persistence across context switch" 378 default n 379 help 380 Double Precision Floating Point unit had dedictaed regs which 381 need to be saved/restored across context-switch. 382 Note that ARC FPU is overly simplistic, unlike say x86, which has 383 hardware pieces to allow software to conditionally save/restore, 384 based on actual usage of FPU by a task. Thus our implemn does 385 this for all tasks in system. 386 387endif #ISA_ARCOMPACT 388 389config ARC_CANT_LLSC 390 def_bool n 391 392config ARC_HAS_LLSC 393 bool "Insn: LLOCK/SCOND (efficient atomic ops)" 394 default y 395 depends on !ARC_CANT_LLSC 396 397config ARC_HAS_SWAPE 398 bool "Insn: SWAPE (endian-swap)" 399 default y 400 401if ISA_ARCV2 402 403config ARC_HAS_LL64 404 bool "Insn: 64bit LDD/STD" 405 help 406 Enable gcc to generate 64-bit load/store instructions 407 ISA mandates even/odd registers to allow encoding of two 408 dest operands with 2 possible source operands. 409 default y 410 411config ARC_HAS_DIV_REM 412 bool "Insn: div, divu, rem, remu" 413 default y 414 415endif # ISA_ARCV2 416 417endmenu # "ARC CPU Configuration" 418 419config LINUX_LINK_BASE 420 hex "Linux Link Address" 421 default "0x80000000" 422 help 423 ARC700 divides the 32 bit phy address space into two equal halves 424 -Lower 2G (0 - 0x7FFF_FFFF ) is user virtual, translated by MMU 425 -Upper 2G (0x8000_0000 onwards) is untranslated, for kernel 426 Typically Linux kernel is linked at the start of untransalted addr, 427 hence the default value of 0x8zs. 428 However some customers have peripherals mapped at this addr, so 429 Linux needs to be scooted a bit. 430 If you don't know what the above means, leave this setting alone. 431 This needs to match memory start address specified in Device Tree 432 433config HIGHMEM 434 bool "High Memory Support" 435 select ARCH_DISCONTIGMEM_ENABLE 436 help 437 With ARC 2G:2G address split, only upper 2G is directly addressable by 438 kernel. Enable this to potentially allow access to rest of 2G and PAE 439 in future 440 441config ARC_HAS_PAE40 442 bool "Support for the 40-bit Physical Address Extension" 443 default n 444 depends on ISA_ARCV2 445 help 446 Enable access to physical memory beyond 4G, only supported on 447 ARC cores with 40 bit Physical Addressing support 448 449config ARCH_PHYS_ADDR_T_64BIT 450 def_bool ARC_HAS_PAE40 451 452config ARCH_DMA_ADDR_T_64BIT 453 bool 454 455config ARC_PLAT_NEEDS_PHYS_TO_DMA 456 bool 457 458config ARC_KVADDR_SIZE 459 int "Kernel Virtaul Address Space size (MB)" 460 range 0 512 461 default "256" 462 help 463 The kernel address space is carved out of 256MB of translated address 464 space for catering to vmalloc, modules, pkmap, fixmap. This however may 465 not suffice vmalloc requirements of a 4K CPU EZChip system. So allow 466 this to be stretched to 512 MB (by extending into the reserved 467 kernel-user gutter) 468 469config ARC_CURR_IN_REG 470 bool "Dedicate Register r25 for current_task pointer" 471 default y 472 help 473 This reserved Register R25 to point to Current Task in 474 kernel mode. This saves memory access for each such access 475 476 477config ARC_EMUL_UNALIGNED 478 bool "Emulate unaligned memory access (userspace only)" 479 default N 480 select SYSCTL_ARCH_UNALIGN_NO_WARN 481 select SYSCTL_ARCH_UNALIGN_ALLOW 482 depends on ISA_ARCOMPACT 483 help 484 This enables misaligned 16 & 32 bit memory access from user space. 485 Use ONLY-IF-ABS-NECESSARY as it will be very slow and also can hide 486 potential bugs in code 487 488config HZ 489 int "Timer Frequency" 490 default 100 491 492config ARC_METAWARE_HLINK 493 bool "Support for Metaware debugger assisted Host access" 494 default n 495 help 496 This options allows a Linux userland apps to directly access 497 host file system (open/creat/read/write etc) with help from 498 Metaware Debugger. This can come in handy for Linux-host communication 499 when there is no real usable peripheral such as EMAC. 500 501menuconfig ARC_DBG 502 bool "ARC debugging" 503 default y 504 505if ARC_DBG 506 507config ARC_DW2_UNWIND 508 bool "Enable DWARF specific kernel stack unwind" 509 default y 510 select KALLSYMS 511 help 512 Compiles the kernel with DWARF unwind information and can be used 513 to get stack backtraces. 514 515 If you say Y here the resulting kernel image will be slightly larger 516 but not slower, and it will give very useful debugging information. 517 If you don't debug the kernel, you can say N, but we may not be able 518 to solve problems without frame unwind information 519 520config ARC_DBG_TLB_PARANOIA 521 bool "Paranoia Checks in Low Level TLB Handlers" 522 default n 523 524endif 525 526config ARC_UBOOT_SUPPORT 527 bool "Support uboot arg Handling" 528 default n 529 help 530 ARC Linux by default checks for uboot provided args as pointers to 531 external cmdline or DTB. This however breaks in absence of uboot, 532 when booting from Metaware debugger directly, as the registers are 533 not zeroed out on reset by mdb and/or ARCv2 based cores. The bogus 534 registers look like uboot args to kernel which then chokes. 535 So only enable the uboot arg checking/processing if users are sure 536 of uboot being in play. 537 538config ARC_BUILTIN_DTB_NAME 539 string "Built in DTB" 540 help 541 Set the name of the DTB to embed in the vmlinux binary 542 Leaving it blank selects the minimal "skeleton" dtb 543 544source "kernel/Kconfig.preempt" 545 546menu "Executable file formats" 547source "fs/Kconfig.binfmt" 548endmenu 549 550endmenu # "ARC Architecture Configuration" 551 552source "mm/Kconfig" 553 554config FORCE_MAX_ZONEORDER 555 int "Maximum zone order" 556 default "12" if ARC_HUGEPAGE_16M 557 default "11" 558 559source "net/Kconfig" 560source "drivers/Kconfig" 561 562menu "Bus Support" 563 564config PCI 565 bool "PCI support" if MIGHT_HAVE_PCI 566 help 567 PCI is the name of a bus system, i.e., the way the CPU talks to 568 the other stuff inside your box. Find out if your board/platform 569 has PCI. 570 571 Note: PCIe support for Synopsys Device will be available only 572 when HAPS DX is configured with PCIe RC bitmap. If you have PCI, 573 say Y, otherwise N. 574 575config PCI_SYSCALL 576 def_bool PCI 577 578source "drivers/pci/Kconfig" 579 580endmenu 581 582source "fs/Kconfig" 583source "arch/arc/Kconfig.debug" 584source "security/Kconfig" 585source "crypto/Kconfig" 586source "lib/Kconfig" 587source "kernel/power/Kconfig" 588