1# 2# Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com) 3# 4# This program is free software; you can redistribute it and/or modify 5# it under the terms of the GNU General Public License version 2 as 6# published by the Free Software Foundation. 7# 8 9config ARC 10 def_bool y 11 select ARC_TIMERS 12 select ARCH_HAS_SYNC_DMA_FOR_CPU 13 select ARCH_HAS_SYNC_DMA_FOR_DEVICE 14 select ARCH_HAS_SG_CHAIN 15 select ARCH_SUPPORTS_ATOMIC_RMW if ARC_HAS_LLSC 16 select BUILDTIME_EXTABLE_SORT 17 select CLONE_BACKWARDS 18 select COMMON_CLK 19 select DMA_NONCOHERENT_OPS 20 select DMA_NONCOHERENT_MMAP 21 select GENERIC_ATOMIC64 if !ISA_ARCV2 || !(ARC_HAS_LL64 && ARC_HAS_LLSC) 22 select GENERIC_CLOCKEVENTS 23 select GENERIC_FIND_FIRST_BIT 24 # for now, we don't need GENERIC_IRQ_PROBE, CONFIG_GENERIC_IRQ_CHIP 25 select GENERIC_IRQ_SHOW 26 select GENERIC_PCI_IOMAP 27 select GENERIC_PENDING_IRQ if SMP 28 select GENERIC_SMP_IDLE_THREAD 29 select HAVE_ARCH_KGDB 30 select HAVE_ARCH_TRACEHOOK 31 select HAVE_FUTEX_CMPXCHG if FUTEX 32 select HAVE_IOREMAP_PROT 33 select HAVE_KPROBES 34 select HAVE_KRETPROBES 35 select HAVE_MEMBLOCK 36 select HAVE_MOD_ARCH_SPECIFIC 37 select HAVE_OPROFILE 38 select HAVE_PERF_EVENTS 39 select HANDLE_DOMAIN_IRQ 40 select IRQ_DOMAIN 41 select MODULES_USE_ELF_RELA 42 select NO_BOOTMEM 43 select OF 44 select OF_EARLY_FLATTREE 45 select OF_RESERVED_MEM 46 select PERF_USE_VMALLOC if ARC_CACHE_VIPT_ALIASING 47 select HAVE_DEBUG_STACKOVERFLOW 48 select HAVE_GENERIC_DMA_COHERENT 49 select HAVE_KERNEL_GZIP 50 select HAVE_KERNEL_LZMA 51 52config MIGHT_HAVE_PCI 53 bool 54 55config TRACE_IRQFLAGS_SUPPORT 56 def_bool y 57 58config LOCKDEP_SUPPORT 59 def_bool y 60 61config SCHED_OMIT_FRAME_POINTER 62 def_bool y 63 64config GENERIC_CSUM 65 def_bool y 66 67config RWSEM_GENERIC_SPINLOCK 68 def_bool y 69 70config ARCH_DISCONTIGMEM_ENABLE 71 def_bool n 72 73config ARCH_FLATMEM_ENABLE 74 def_bool y 75 76config MMU 77 def_bool y 78 79config NO_IOPORT_MAP 80 def_bool y 81 82config GENERIC_CALIBRATE_DELAY 83 def_bool y 84 85config GENERIC_HWEIGHT 86 def_bool y 87 88config STACKTRACE_SUPPORT 89 def_bool y 90 select STACKTRACE 91 92config HAVE_ARCH_TRANSPARENT_HUGEPAGE 93 def_bool y 94 depends on ARC_MMU_V4 95 96source "init/Kconfig" 97source "kernel/Kconfig.freezer" 98 99menu "ARC Architecture Configuration" 100 101menu "ARC Platform/SoC/Board" 102 103source "arch/arc/plat-tb10x/Kconfig" 104source "arch/arc/plat-axs10x/Kconfig" 105#New platform adds here 106source "arch/arc/plat-eznps/Kconfig" 107source "arch/arc/plat-hsdk/Kconfig" 108 109endmenu 110 111choice 112 prompt "ARC Instruction Set" 113 default ISA_ARCOMPACT 114 115config ISA_ARCOMPACT 116 bool "ARCompact ISA" 117 select CPU_NO_EFFICIENT_FFS 118 help 119 The original ARC ISA of ARC600/700 cores 120 121config ISA_ARCV2 122 bool "ARC ISA v2" 123 select ARC_TIMERS_64BIT 124 help 125 ISA for the Next Generation ARC-HS cores 126 127endchoice 128 129menu "ARC CPU Configuration" 130 131choice 132 prompt "ARC Core" 133 default ARC_CPU_770 if ISA_ARCOMPACT 134 default ARC_CPU_HS if ISA_ARCV2 135 136if ISA_ARCOMPACT 137 138config ARC_CPU_750D 139 bool "ARC750D" 140 select ARC_CANT_LLSC 141 help 142 Support for ARC750 core 143 144config ARC_CPU_770 145 bool "ARC770" 146 select ARC_HAS_SWAPE 147 help 148 Support for ARC770 core introduced with Rel 4.10 (Summer 2011) 149 This core has a bunch of cool new features: 150 -MMU-v3: Variable Page Sz (4k, 8k, 16k), bigger J-TLB (128x4) 151 Shared Address Spaces (for sharing TLB entires in MMU) 152 -Caches: New Prog Model, Region Flush 153 -Insns: endian swap, load-locked/store-conditional, time-stamp-ctr 154 155endif #ISA_ARCOMPACT 156 157config ARC_CPU_HS 158 bool "ARC-HS" 159 depends on ISA_ARCV2 160 help 161 Support for ARC HS38x Cores based on ARCv2 ISA 162 The notable features are: 163 - SMP configurations of upto 4 core with coherency 164 - Optional L2 Cache and IO-Coherency 165 - Revised Interrupt Architecture (multiple priorites, reg banks, 166 auto stack switch, auto regfile save/restore) 167 - MMUv4 (PIPT dcache, Huge Pages) 168 - Instructions for 169 * 64bit load/store: LDD, STD 170 * Hardware assisted divide/remainder: DIV, REM 171 * Function prologue/epilogue: ENTER_S, LEAVE_S 172 * IRQ enable/disable: CLRI, SETI 173 * pop count: FFS, FLS 174 * SETcc, BMSKN, XBFU... 175 176endchoice 177 178config CPU_BIG_ENDIAN 179 bool "Enable Big Endian Mode" 180 default n 181 help 182 Build kernel for Big Endian Mode of ARC CPU 183 184config SMP 185 bool "Symmetric Multi-Processing" 186 default n 187 select ARC_MCIP if ISA_ARCV2 188 help 189 This enables support for systems with more than one CPU. 190 191if SMP 192 193config NR_CPUS 194 int "Maximum number of CPUs (2-4096)" 195 range 2 4096 196 default "4" 197 198config ARC_SMP_HALT_ON_RESET 199 bool "Enable Halt-on-reset boot mode" 200 default y if ARC_UBOOT_SUPPORT 201 help 202 In SMP configuration cores can be configured as Halt-on-reset 203 or they could all start at same time. For Halt-on-reset, non 204 masters are parked until Master kicks them so they can start of 205 at designated entry point. For other case, all jump to common 206 entry point and spin wait for Master's signal. 207 208endif #SMP 209 210config ARC_MCIP 211 bool "ARConnect Multicore IP (MCIP) Support " 212 depends on ISA_ARCV2 213 default y if SMP 214 help 215 This IP block enables SMP in ARC-HS38 cores. 216 It provides for cross-core interrupts, multi-core debug 217 hardware semaphores, shared memory,.... 218 219menuconfig ARC_CACHE 220 bool "Enable Cache Support" 221 default y 222 223if ARC_CACHE 224 225config ARC_CACHE_LINE_SHIFT 226 int "Cache Line Length (as power of 2)" 227 range 5 7 228 default "6" 229 help 230 Starting with ARC700 4.9, Cache line length is configurable, 231 This option specifies "N", with Line-len = 2 power N 232 So line lengths of 32, 64, 128 are specified by 5,6,7, respectively 233 Linux only supports same line lengths for I and D caches. 234 235config ARC_HAS_ICACHE 236 bool "Use Instruction Cache" 237 default y 238 239config ARC_HAS_DCACHE 240 bool "Use Data Cache" 241 default y 242 243config ARC_CACHE_PAGES 244 bool "Per Page Cache Control" 245 default y 246 depends on ARC_HAS_ICACHE || ARC_HAS_DCACHE 247 help 248 This can be used to over-ride the global I/D Cache Enable on a 249 per-page basis (but only for pages accessed via MMU such as 250 Kernel Virtual address or User Virtual Address) 251 TLB entries have a per-page Cache Enable Bit. 252 Note that Global I/D ENABLE + Per Page DISABLE works but corollary 253 Global DISABLE + Per Page ENABLE won't work 254 255config ARC_CACHE_VIPT_ALIASING 256 bool "Support VIPT Aliasing D$" 257 depends on ARC_HAS_DCACHE && ISA_ARCOMPACT 258 default n 259 260endif #ARC_CACHE 261 262config ARC_HAS_ICCM 263 bool "Use ICCM" 264 help 265 Single Cycle RAMS to store Fast Path Code 266 default n 267 268config ARC_ICCM_SZ 269 int "ICCM Size in KB" 270 default "64" 271 depends on ARC_HAS_ICCM 272 273config ARC_HAS_DCCM 274 bool "Use DCCM" 275 help 276 Single Cycle RAMS to store Fast Path Data 277 default n 278 279config ARC_DCCM_SZ 280 int "DCCM Size in KB" 281 default "64" 282 depends on ARC_HAS_DCCM 283 284config ARC_DCCM_BASE 285 hex "DCCM map address" 286 default "0xA0000000" 287 depends on ARC_HAS_DCCM 288 289choice 290 prompt "MMU Version" 291 default ARC_MMU_V3 if ARC_CPU_770 292 default ARC_MMU_V2 if ARC_CPU_750D 293 default ARC_MMU_V4 if ARC_CPU_HS 294 295if ISA_ARCOMPACT 296 297config ARC_MMU_V1 298 bool "MMU v1" 299 help 300 Orig ARC700 MMU 301 302config ARC_MMU_V2 303 bool "MMU v2" 304 help 305 Fixed the deficiency of v1 - possible thrashing in memcpy scenario 306 when 2 D-TLB and 1 I-TLB entries index into same 2way set. 307 308config ARC_MMU_V3 309 bool "MMU v3" 310 depends on ARC_CPU_770 311 help 312 Introduced with ARC700 4.10: New Features 313 Variable Page size (1k-16k), var JTLB size 128 x (2 or 4) 314 Shared Address Spaces (SASID) 315 316endif 317 318config ARC_MMU_V4 319 bool "MMU v4" 320 depends on ISA_ARCV2 321 322endchoice 323 324 325choice 326 prompt "MMU Page Size" 327 default ARC_PAGE_SIZE_8K 328 329config ARC_PAGE_SIZE_8K 330 bool "8KB" 331 help 332 Choose between 8k vs 16k 333 334config ARC_PAGE_SIZE_16K 335 bool "16KB" 336 depends on ARC_MMU_V3 || ARC_MMU_V4 337 338config ARC_PAGE_SIZE_4K 339 bool "4KB" 340 depends on ARC_MMU_V3 || ARC_MMU_V4 341 342endchoice 343 344choice 345 prompt "MMU Super Page Size" 346 depends on ISA_ARCV2 && TRANSPARENT_HUGEPAGE 347 default ARC_HUGEPAGE_2M 348 349config ARC_HUGEPAGE_2M 350 bool "2MB" 351 352config ARC_HUGEPAGE_16M 353 bool "16MB" 354 355endchoice 356 357config NODES_SHIFT 358 int "Maximum NUMA Nodes (as a power of 2)" 359 default "0" if !DISCONTIGMEM 360 default "1" if DISCONTIGMEM 361 depends on NEED_MULTIPLE_NODES 362 ---help--- 363 Accessing memory beyond 1GB (with or w/o PAE) requires 2 memory 364 zones. 365 366if ISA_ARCOMPACT 367 368config ARC_COMPACT_IRQ_LEVELS 369 bool "Setup Timer IRQ as high Priority" 370 default n 371 # if SMP, LV2 enabled ONLY if ARC implementation has LV2 re-entrancy 372 depends on !SMP 373 374config ARC_FPU_SAVE_RESTORE 375 bool "Enable FPU state persistence across context switch" 376 default n 377 help 378 Double Precision Floating Point unit had dedicated regs which 379 need to be saved/restored across context-switch. 380 Note that ARC FPU is overly simplistic, unlike say x86, which has 381 hardware pieces to allow software to conditionally save/restore, 382 based on actual usage of FPU by a task. Thus our implemn does 383 this for all tasks in system. 384 385endif #ISA_ARCOMPACT 386 387config ARC_CANT_LLSC 388 def_bool n 389 390config ARC_HAS_LLSC 391 bool "Insn: LLOCK/SCOND (efficient atomic ops)" 392 default y 393 depends on !ARC_CANT_LLSC 394 395config ARC_HAS_SWAPE 396 bool "Insn: SWAPE (endian-swap)" 397 default y 398 399if ISA_ARCV2 400 401config ARC_HAS_LL64 402 bool "Insn: 64bit LDD/STD" 403 help 404 Enable gcc to generate 64-bit load/store instructions 405 ISA mandates even/odd registers to allow encoding of two 406 dest operands with 2 possible source operands. 407 default y 408 409config ARC_HAS_DIV_REM 410 bool "Insn: div, divu, rem, remu" 411 default y 412 413config ARC_HAS_ACCL_REGS 414 bool "Reg Pair ACCL:ACCH (FPU and/or MPY > 6)" 415 default n 416 help 417 Depending on the configuration, CPU can contain accumulator reg-pair 418 (also referred to as r58:r59). These can also be used by gcc as GPR so 419 kernel needs to save/restore per process 420 421endif # ISA_ARCV2 422 423endmenu # "ARC CPU Configuration" 424 425config LINUX_LINK_BASE 426 hex "Kernel link address" 427 default "0x80000000" 428 help 429 ARC700 divides the 32 bit phy address space into two equal halves 430 -Lower 2G (0 - 0x7FFF_FFFF ) is user virtual, translated by MMU 431 -Upper 2G (0x8000_0000 onwards) is untranslated, for kernel 432 Typically Linux kernel is linked at the start of untransalted addr, 433 hence the default value of 0x8zs. 434 However some customers have peripherals mapped at this addr, so 435 Linux needs to be scooted a bit. 436 If you don't know what the above means, leave this setting alone. 437 This needs to match memory start address specified in Device Tree 438 439config LINUX_RAM_BASE 440 hex "RAM base address" 441 default LINUX_LINK_BASE 442 help 443 By default Linux is linked at base of RAM. However in some special 444 cases (such as HSDK), Linux can't be linked at start of DDR, hence 445 this option. 446 447config HIGHMEM 448 bool "High Memory Support" 449 select ARCH_DISCONTIGMEM_ENABLE 450 help 451 With ARC 2G:2G address split, only upper 2G is directly addressable by 452 kernel. Enable this to potentially allow access to rest of 2G and PAE 453 in future 454 455config ARC_HAS_PAE40 456 bool "Support for the 40-bit Physical Address Extension" 457 default n 458 depends on ISA_ARCV2 459 select HIGHMEM 460 select PHYS_ADDR_T_64BIT 461 help 462 Enable access to physical memory beyond 4G, only supported on 463 ARC cores with 40 bit Physical Addressing support 464 465config ARC_KVADDR_SIZE 466 int "Kernel Virtual Address Space size (MB)" 467 range 0 512 468 default "256" 469 help 470 The kernel address space is carved out of 256MB of translated address 471 space for catering to vmalloc, modules, pkmap, fixmap. This however may 472 not suffice vmalloc requirements of a 4K CPU EZChip system. So allow 473 this to be stretched to 512 MB (by extending into the reserved 474 kernel-user gutter) 475 476config ARC_CURR_IN_REG 477 bool "Dedicate Register r25 for current_task pointer" 478 default y 479 help 480 This reserved Register R25 to point to Current Task in 481 kernel mode. This saves memory access for each such access 482 483 484config ARC_EMUL_UNALIGNED 485 bool "Emulate unaligned memory access (userspace only)" 486 select SYSCTL_ARCH_UNALIGN_NO_WARN 487 select SYSCTL_ARCH_UNALIGN_ALLOW 488 depends on ISA_ARCOMPACT 489 help 490 This enables misaligned 16 & 32 bit memory access from user space. 491 Use ONLY-IF-ABS-NECESSARY as it will be very slow and also can hide 492 potential bugs in code 493 494config HZ 495 int "Timer Frequency" 496 default 100 497 498config ARC_METAWARE_HLINK 499 bool "Support for Metaware debugger assisted Host access" 500 default n 501 help 502 This options allows a Linux userland apps to directly access 503 host file system (open/creat/read/write etc) with help from 504 Metaware Debugger. This can come in handy for Linux-host communication 505 when there is no real usable peripheral such as EMAC. 506 507menuconfig ARC_DBG 508 bool "ARC debugging" 509 default y 510 511if ARC_DBG 512 513config ARC_DW2_UNWIND 514 bool "Enable DWARF specific kernel stack unwind" 515 default y 516 select KALLSYMS 517 help 518 Compiles the kernel with DWARF unwind information and can be used 519 to get stack backtraces. 520 521 If you say Y here the resulting kernel image will be slightly larger 522 but not slower, and it will give very useful debugging information. 523 If you don't debug the kernel, you can say N, but we may not be able 524 to solve problems without frame unwind information 525 526config ARC_DBG_TLB_PARANOIA 527 bool "Paranoia Checks in Low Level TLB Handlers" 528 default n 529 530endif 531 532config ARC_UBOOT_SUPPORT 533 bool "Support uboot arg Handling" 534 default n 535 help 536 ARC Linux by default checks for uboot provided args as pointers to 537 external cmdline or DTB. This however breaks in absence of uboot, 538 when booting from Metaware debugger directly, as the registers are 539 not zeroed out on reset by mdb and/or ARCv2 based cores. The bogus 540 registers look like uboot args to kernel which then chokes. 541 So only enable the uboot arg checking/processing if users are sure 542 of uboot being in play. 543 544config ARC_BUILTIN_DTB_NAME 545 string "Built in DTB" 546 help 547 Set the name of the DTB to embed in the vmlinux binary 548 Leaving it blank selects the minimal "skeleton" dtb 549 550source "kernel/Kconfig.preempt" 551 552menu "Executable file formats" 553source "fs/Kconfig.binfmt" 554endmenu 555 556endmenu # "ARC Architecture Configuration" 557 558source "mm/Kconfig" 559 560config FORCE_MAX_ZONEORDER 561 int "Maximum zone order" 562 default "12" if ARC_HUGEPAGE_16M 563 default "11" 564 565source "net/Kconfig" 566source "drivers/Kconfig" 567 568menu "Bus Support" 569 570config PCI 571 bool "PCI support" if MIGHT_HAVE_PCI 572 help 573 PCI is the name of a bus system, i.e., the way the CPU talks to 574 the other stuff inside your box. Find out if your board/platform 575 has PCI. 576 577 Note: PCIe support for Synopsys Device will be available only 578 when HAPS DX is configured with PCIe RC bitmap. If you have PCI, 579 say Y, otherwise N. 580 581config PCI_SYSCALL 582 def_bool PCI 583 584source "drivers/pci/Kconfig" 585 586endmenu 587 588source "fs/Kconfig" 589source "arch/arc/Kconfig.debug" 590source "security/Kconfig" 591source "crypto/Kconfig" 592source "lib/Kconfig" 593source "kernel/power/Kconfig" 594