1# SPDX-License-Identifier: GPL-2.0-only 2# 3# Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com) 4# 5 6config ARC 7 def_bool y 8 select ARC_TIMERS 9 select ARCH_HAS_CACHE_LINE_SIZE 10 select ARCH_HAS_DEBUG_VM_PGTABLE 11 select ARCH_HAS_DMA_PREP_COHERENT 12 select ARCH_HAS_PTE_SPECIAL 13 select ARCH_HAS_SETUP_DMA_OPS 14 select ARCH_HAS_SYNC_DMA_FOR_CPU 15 select ARCH_HAS_SYNC_DMA_FOR_DEVICE 16 select ARCH_SUPPORTS_ATOMIC_RMW if ARC_HAS_LLSC 17 select ARCH_32BIT_OFF_T 18 select BUILDTIME_TABLE_SORT 19 select CLONE_BACKWARDS 20 select COMMON_CLK 21 select DMA_DIRECT_REMAP 22 select GENERIC_ATOMIC64 if !ISA_ARCV2 || !(ARC_HAS_LL64 && ARC_HAS_LLSC) 23 # for now, we don't need GENERIC_IRQ_PROBE, CONFIG_GENERIC_IRQ_CHIP 24 select GENERIC_IRQ_SHOW 25 select GENERIC_PCI_IOMAP 26 select GENERIC_PENDING_IRQ if SMP 27 select GENERIC_SCHED_CLOCK 28 select GENERIC_SMP_IDLE_THREAD 29 select HAVE_ARCH_KGDB 30 select HAVE_ARCH_TRACEHOOK 31 select HAVE_ARCH_TRANSPARENT_HUGEPAGE if ARC_MMU_V4 32 select HAVE_DEBUG_STACKOVERFLOW 33 select HAVE_DEBUG_KMEMLEAK 34 select HAVE_IOREMAP_PROT 35 select HAVE_KERNEL_GZIP 36 select HAVE_KERNEL_LZMA 37 select HAVE_KPROBES 38 select HAVE_KRETPROBES 39 select HAVE_MOD_ARCH_SPECIFIC 40 select HAVE_PERF_EVENTS 41 select IRQ_DOMAIN 42 select MODULES_USE_ELF_RELA 43 select OF 44 select OF_EARLY_FLATTREE 45 select PCI_SYSCALL if PCI 46 select PERF_USE_VMALLOC if ARC_CACHE_VIPT_ALIASING 47 select HAVE_ARCH_JUMP_LABEL if ISA_ARCV2 && !CPU_ENDIAN_BE32 48 select SET_FS 49 select TRACE_IRQFLAGS_SUPPORT 50 51config LOCKDEP_SUPPORT 52 def_bool y 53 54config SCHED_OMIT_FRAME_POINTER 55 def_bool y 56 57config GENERIC_CSUM 58 def_bool y 59 60config ARCH_FLATMEM_ENABLE 61 def_bool y 62 63config MMU 64 def_bool y 65 66config NO_IOPORT_MAP 67 def_bool y 68 69config GENERIC_CALIBRATE_DELAY 70 def_bool y 71 72config GENERIC_HWEIGHT 73 def_bool y 74 75config STACKTRACE_SUPPORT 76 def_bool y 77 select STACKTRACE 78 79menu "ARC Architecture Configuration" 80 81menu "ARC Platform/SoC/Board" 82 83source "arch/arc/plat-tb10x/Kconfig" 84source "arch/arc/plat-axs10x/Kconfig" 85source "arch/arc/plat-hsdk/Kconfig" 86 87endmenu 88 89choice 90 prompt "ARC Instruction Set" 91 default ISA_ARCV2 92 93config ISA_ARCOMPACT 94 bool "ARCompact ISA" 95 select CPU_NO_EFFICIENT_FFS 96 help 97 The original ARC ISA of ARC600/700 cores 98 99config ISA_ARCV2 100 bool "ARC ISA v2" 101 select ARC_TIMERS_64BIT 102 help 103 ISA for the Next Generation ARC-HS cores 104 105endchoice 106 107menu "ARC CPU Configuration" 108 109choice 110 prompt "ARC Core" 111 default ARC_CPU_770 if ISA_ARCOMPACT 112 default ARC_CPU_HS if ISA_ARCV2 113 114config ARC_CPU_770 115 bool "ARC770" 116 depends on ISA_ARCOMPACT 117 select ARC_HAS_SWAPE 118 help 119 Support for ARC770 core introduced with Rel 4.10 (Summer 2011) 120 This core has a bunch of cool new features: 121 -MMU-v3: Variable Page Sz (4k, 8k, 16k), bigger J-TLB (128x4) 122 Shared Address Spaces (for sharing TLB entries in MMU) 123 -Caches: New Prog Model, Region Flush 124 -Insns: endian swap, load-locked/store-conditional, time-stamp-ctr 125 126config ARC_CPU_HS 127 bool "ARC-HS" 128 depends on ISA_ARCV2 129 help 130 Support for ARC HS38x Cores based on ARCv2 ISA 131 The notable features are: 132 - SMP configurations of up to 4 cores with coherency 133 - Optional L2 Cache and IO-Coherency 134 - Revised Interrupt Architecture (multiple priorites, reg banks, 135 auto stack switch, auto regfile save/restore) 136 - MMUv4 (PIPT dcache, Huge Pages) 137 - Instructions for 138 * 64bit load/store: LDD, STD 139 * Hardware assisted divide/remainder: DIV, REM 140 * Function prologue/epilogue: ENTER_S, LEAVE_S 141 * IRQ enable/disable: CLRI, SETI 142 * pop count: FFS, FLS 143 * SETcc, BMSKN, XBFU... 144 145endchoice 146 147config ARC_TUNE_MCPU 148 string "Override default -mcpu compiler flag" 149 default "" 150 help 151 Override default -mcpu=xxx compiler flag (which is set depending on 152 the ISA version) with the specified value. 153 NOTE: If specified flag isn't supported by current compiler the 154 ISA default value will be used as a fallback. 155 156config CPU_BIG_ENDIAN 157 bool "Enable Big Endian Mode" 158 help 159 Build kernel for Big Endian Mode of ARC CPU 160 161config SMP 162 bool "Symmetric Multi-Processing" 163 select ARC_MCIP if ISA_ARCV2 164 help 165 This enables support for systems with more than one CPU. 166 167if SMP 168 169config NR_CPUS 170 int "Maximum number of CPUs (2-4096)" 171 range 2 4096 172 default "4" 173 174config ARC_SMP_HALT_ON_RESET 175 bool "Enable Halt-on-reset boot mode" 176 help 177 In SMP configuration cores can be configured as Halt-on-reset 178 or they could all start at same time. For Halt-on-reset, non 179 masters are parked until Master kicks them so they can start off 180 at designated entry point. For other case, all jump to common 181 entry point and spin wait for Master's signal. 182 183endif #SMP 184 185config ARC_MCIP 186 bool "ARConnect Multicore IP (MCIP) Support " 187 depends on ISA_ARCV2 188 default y if SMP 189 help 190 This IP block enables SMP in ARC-HS38 cores. 191 It provides for cross-core interrupts, multi-core debug 192 hardware semaphores, shared memory,.... 193 194menuconfig ARC_CACHE 195 bool "Enable Cache Support" 196 default y 197 198if ARC_CACHE 199 200config ARC_CACHE_LINE_SHIFT 201 int "Cache Line Length (as power of 2)" 202 range 5 7 203 default "6" 204 help 205 Starting with ARC700 4.9, Cache line length is configurable, 206 This option specifies "N", with Line-len = 2 power N 207 So line lengths of 32, 64, 128 are specified by 5,6,7, respectively 208 Linux only supports same line lengths for I and D caches. 209 210config ARC_HAS_ICACHE 211 bool "Use Instruction Cache" 212 default y 213 214config ARC_HAS_DCACHE 215 bool "Use Data Cache" 216 default y 217 218config ARC_CACHE_PAGES 219 bool "Per Page Cache Control" 220 default y 221 depends on ARC_HAS_ICACHE || ARC_HAS_DCACHE 222 help 223 This can be used to over-ride the global I/D Cache Enable on a 224 per-page basis (but only for pages accessed via MMU such as 225 Kernel Virtual address or User Virtual Address) 226 TLB entries have a per-page Cache Enable Bit. 227 Note that Global I/D ENABLE + Per Page DISABLE works but corollary 228 Global DISABLE + Per Page ENABLE won't work 229 230config ARC_CACHE_VIPT_ALIASING 231 bool "Support VIPT Aliasing D$" 232 depends on ARC_HAS_DCACHE && ISA_ARCOMPACT 233 234endif #ARC_CACHE 235 236config ARC_HAS_ICCM 237 bool "Use ICCM" 238 help 239 Single Cycle RAMS to store Fast Path Code 240 241config ARC_ICCM_SZ 242 int "ICCM Size in KB" 243 default "64" 244 depends on ARC_HAS_ICCM 245 246config ARC_HAS_DCCM 247 bool "Use DCCM" 248 help 249 Single Cycle RAMS to store Fast Path Data 250 251config ARC_DCCM_SZ 252 int "DCCM Size in KB" 253 default "64" 254 depends on ARC_HAS_DCCM 255 256config ARC_DCCM_BASE 257 hex "DCCM map address" 258 default "0xA0000000" 259 depends on ARC_HAS_DCCM 260 261choice 262 prompt "MMU Version" 263 default ARC_MMU_V3 if ISA_ARCOMPACT 264 default ARC_MMU_V4 if ISA_ARCV2 265 266config ARC_MMU_V3 267 bool "MMU v3" 268 depends on ISA_ARCOMPACT 269 help 270 Introduced with ARC700 4.10: New Features 271 Variable Page size (1k-16k), var JTLB size 128 x (2 or 4) 272 Shared Address Spaces (SASID) 273 274config ARC_MMU_V4 275 bool "MMU v4" 276 depends on ISA_ARCV2 277 278endchoice 279 280 281choice 282 prompt "MMU Page Size" 283 default ARC_PAGE_SIZE_8K 284 285config ARC_PAGE_SIZE_8K 286 bool "8KB" 287 help 288 Choose between 8k vs 16k 289 290config ARC_PAGE_SIZE_16K 291 bool "16KB" 292 293config ARC_PAGE_SIZE_4K 294 bool "4KB" 295 depends on ARC_MMU_V3 || ARC_MMU_V4 296 297endchoice 298 299choice 300 prompt "MMU Super Page Size" 301 depends on ISA_ARCV2 && TRANSPARENT_HUGEPAGE 302 default ARC_HUGEPAGE_2M 303 304config ARC_HUGEPAGE_2M 305 bool "2MB" 306 307config ARC_HUGEPAGE_16M 308 bool "16MB" 309 310endchoice 311 312config PGTABLE_LEVELS 313 int "Number of Page table levels" 314 default 2 315 316config ARC_COMPACT_IRQ_LEVELS 317 depends on ISA_ARCOMPACT 318 bool "Setup Timer IRQ as high Priority" 319 # if SMP, LV2 enabled ONLY if ARC implementation has LV2 re-entrancy 320 depends on !SMP 321 322config ARC_FPU_SAVE_RESTORE 323 bool "Enable FPU state persistence across context switch" 324 help 325 ARCompact FPU has internal registers to assist with Double precision 326 Floating Point operations. There are control and stauts registers 327 for floating point exceptions and rounding modes. These are 328 preserved across task context switch when enabled. 329 330config ARC_CANT_LLSC 331 def_bool n 332 333config ARC_HAS_LLSC 334 bool "Insn: LLOCK/SCOND (efficient atomic ops)" 335 default y 336 depends on !ARC_CANT_LLSC 337 338config ARC_HAS_SWAPE 339 bool "Insn: SWAPE (endian-swap)" 340 default y 341 342if ISA_ARCV2 343 344config ARC_USE_UNALIGNED_MEM_ACCESS 345 bool "Enable unaligned access in HW" 346 default y 347 select HAVE_EFFICIENT_UNALIGNED_ACCESS 348 help 349 The ARC HS architecture supports unaligned memory access 350 which is disabled by default. Enable unaligned access in 351 hardware and use software to use it 352 353config ARC_HAS_LL64 354 bool "Insn: 64bit LDD/STD" 355 help 356 Enable gcc to generate 64-bit load/store instructions 357 ISA mandates even/odd registers to allow encoding of two 358 dest operands with 2 possible source operands. 359 default y 360 361config ARC_HAS_DIV_REM 362 bool "Insn: div, divu, rem, remu" 363 default y 364 365config ARC_HAS_ACCL_REGS 366 bool "Reg Pair ACCL:ACCH (FPU and/or MPY > 6 and/or DSP)" 367 default y 368 help 369 Depending on the configuration, CPU can contain accumulator reg-pair 370 (also referred to as r58:r59). These can also be used by gcc as GPR so 371 kernel needs to save/restore per process 372 373config ARC_DSP_HANDLED 374 def_bool n 375 376config ARC_DSP_SAVE_RESTORE_REGS 377 def_bool n 378 379choice 380 prompt "DSP support" 381 default ARC_DSP_NONE 382 help 383 Depending on the configuration, CPU can contain DSP registers 384 (ACC0_GLO, ACC0_GHI, DSP_BFLY0, DSP_CTRL, DSP_FFT_CTRL). 385 Below are options describing how to handle these registers in 386 interrupt entry / exit and in context switch. 387 388config ARC_DSP_NONE 389 bool "No DSP extension presence in HW" 390 help 391 No DSP extension presence in HW 392 393config ARC_DSP_KERNEL 394 bool "DSP extension in HW, no support for userspace" 395 select ARC_HAS_ACCL_REGS 396 select ARC_DSP_HANDLED 397 help 398 DSP extension presence in HW, no support for DSP-enabled userspace 399 applications. We don't save / restore DSP registers and only do 400 some minimal preparations so userspace won't be able to break kernel 401 402config ARC_DSP_USERSPACE 403 bool "Support DSP for userspace apps" 404 select ARC_HAS_ACCL_REGS 405 select ARC_DSP_HANDLED 406 select ARC_DSP_SAVE_RESTORE_REGS 407 help 408 DSP extension presence in HW, support save / restore DSP registers to 409 run DSP-enabled userspace applications 410 411config ARC_DSP_AGU_USERSPACE 412 bool "Support DSP with AGU for userspace apps" 413 select ARC_HAS_ACCL_REGS 414 select ARC_DSP_HANDLED 415 select ARC_DSP_SAVE_RESTORE_REGS 416 help 417 DSP and AGU extensions presence in HW, support save / restore DSP 418 and AGU registers to run DSP-enabled userspace applications 419endchoice 420 421config ARC_IRQ_NO_AUTOSAVE 422 bool "Disable hardware autosave regfile on interrupts" 423 default n 424 help 425 On HS cores, taken interrupt auto saves the regfile on stack. 426 This is programmable and can be optionally disabled in which case 427 software INTERRUPT_PROLOGUE/EPILGUE do the needed work 428 429config ARC_LPB_DISABLE 430 bool "Disable loop buffer (LPB)" 431 help 432 On HS cores, loop buffer (LPB) is programmable in runtime and can 433 be optionally disabled. 434 435endif # ISA_ARCV2 436 437endmenu # "ARC CPU Configuration" 438 439config LINUX_LINK_BASE 440 hex "Kernel link address" 441 default "0x80000000" 442 help 443 ARC700 divides the 32 bit phy address space into two equal halves 444 -Lower 2G (0 - 0x7FFF_FFFF ) is user virtual, translated by MMU 445 -Upper 2G (0x8000_0000 onwards) is untranslated, for kernel 446 Typically Linux kernel is linked at the start of untransalted addr, 447 hence the default value of 0x8zs. 448 However some customers have peripherals mapped at this addr, so 449 Linux needs to be scooted a bit. 450 If you don't know what the above means, leave this setting alone. 451 This needs to match memory start address specified in Device Tree 452 453config LINUX_RAM_BASE 454 hex "RAM base address" 455 default LINUX_LINK_BASE 456 help 457 By default Linux is linked at base of RAM. However in some special 458 cases (such as HSDK), Linux can't be linked at start of DDR, hence 459 this option. 460 461config HIGHMEM 462 bool "High Memory Support" 463 select HAVE_ARCH_PFN_VALID 464 select KMAP_LOCAL 465 help 466 With ARC 2G:2G address split, only upper 2G is directly addressable by 467 kernel. Enable this to potentially allow access to rest of 2G and PAE 468 in future 469 470config ARC_HAS_PAE40 471 bool "Support for the 40-bit Physical Address Extension" 472 depends on ISA_ARCV2 473 select HIGHMEM 474 select PHYS_ADDR_T_64BIT 475 help 476 Enable access to physical memory beyond 4G, only supported on 477 ARC cores with 40 bit Physical Addressing support 478 479config ARC_KVADDR_SIZE 480 int "Kernel Virtual Address Space size (MB)" 481 range 0 512 482 default "256" 483 help 484 The kernel address space is carved out of 256MB of translated address 485 space for catering to vmalloc, modules, pkmap, fixmap. This however may 486 not suffice vmalloc requirements of a 4K CPU EZChip system. So allow 487 this to be stretched to 512 MB (by extending into the reserved 488 kernel-user gutter) 489 490config ARC_CURR_IN_REG 491 bool "Dedicate Register r25 for current_task pointer" 492 default y 493 help 494 This reserved Register R25 to point to Current Task in 495 kernel mode. This saves memory access for each such access 496 497 498config ARC_EMUL_UNALIGNED 499 bool "Emulate unaligned memory access (userspace only)" 500 select SYSCTL_ARCH_UNALIGN_NO_WARN 501 select SYSCTL_ARCH_UNALIGN_ALLOW 502 depends on ISA_ARCOMPACT 503 help 504 This enables misaligned 16 & 32 bit memory access from user space. 505 Use ONLY-IF-ABS-NECESSARY as it will be very slow and also can hide 506 potential bugs in code 507 508config HZ 509 int "Timer Frequency" 510 default 100 511 512config ARC_METAWARE_HLINK 513 bool "Support for Metaware debugger assisted Host access" 514 help 515 This options allows a Linux userland apps to directly access 516 host file system (open/creat/read/write etc) with help from 517 Metaware Debugger. This can come in handy for Linux-host communication 518 when there is no real usable peripheral such as EMAC. 519 520menuconfig ARC_DBG 521 bool "ARC debugging" 522 default y 523 524if ARC_DBG 525 526config ARC_DW2_UNWIND 527 bool "Enable DWARF specific kernel stack unwind" 528 default y 529 select KALLSYMS 530 help 531 Compiles the kernel with DWARF unwind information and can be used 532 to get stack backtraces. 533 534 If you say Y here the resulting kernel image will be slightly larger 535 but not slower, and it will give very useful debugging information. 536 If you don't debug the kernel, you can say N, but we may not be able 537 to solve problems without frame unwind information 538 539config ARC_DBG_JUMP_LABEL 540 bool "Paranoid checks in Static Keys (jump labels) code" 541 depends on JUMP_LABEL 542 default y if STATIC_KEYS_SELFTEST 543 help 544 Enable paranoid checks and self-test of both ARC-specific and generic 545 part of static keys (jump labels) related code. 546endif 547 548config ARC_BUILTIN_DTB_NAME 549 string "Built in DTB" 550 help 551 Set the name of the DTB to embed in the vmlinux binary 552 Leaving it blank selects the minimal "skeleton" dtb 553 554endmenu # "ARC Architecture Configuration" 555 556config FORCE_MAX_ZONEORDER 557 int "Maximum zone order" 558 default "12" if ARC_HUGEPAGE_16M 559 default "11" 560 561source "kernel/power/Kconfig" 562