1# 2# Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com) 3# 4# This program is free software; you can redistribute it and/or modify 5# it under the terms of the GNU General Public License version 2 as 6# published by the Free Software Foundation. 7# 8 9config ARC 10 def_bool y 11 select BUILDTIME_EXTABLE_SORT 12 select COMMON_CLK 13 select CLONE_BACKWARDS 14 # ARC Busybox based initramfs absolutely relies on DEVTMPFS for /dev 15 select DEVTMPFS if !INITRAMFS_SOURCE="" 16 select GENERIC_ATOMIC64 17 select GENERIC_CLOCKEVENTS 18 select GENERIC_FIND_FIRST_BIT 19 # for now, we don't need GENERIC_IRQ_PROBE, CONFIG_GENERIC_IRQ_CHIP 20 select GENERIC_IRQ_SHOW 21 select GENERIC_PENDING_IRQ if SMP 22 select GENERIC_SMP_IDLE_THREAD 23 select HAVE_ARCH_KGDB 24 select HAVE_ARCH_TRACEHOOK 25 select HAVE_IOREMAP_PROT 26 select HAVE_KPROBES 27 select HAVE_KRETPROBES 28 select HAVE_MEMBLOCK 29 select HAVE_MOD_ARCH_SPECIFIC if ARC_DW2_UNWIND 30 select HAVE_OPROFILE 31 select HAVE_PERF_EVENTS 32 select IRQ_DOMAIN 33 select MODULES_USE_ELF_RELA 34 select NO_BOOTMEM 35 select OF 36 select OF_EARLY_FLATTREE 37 select PERF_USE_VMALLOC 38 select HAVE_DEBUG_STACKOVERFLOW 39 40config TRACE_IRQFLAGS_SUPPORT 41 def_bool y 42 43config LOCKDEP_SUPPORT 44 def_bool y 45 46config SCHED_OMIT_FRAME_POINTER 47 def_bool y 48 49config GENERIC_CSUM 50 def_bool y 51 52config RWSEM_GENERIC_SPINLOCK 53 def_bool y 54 55config ARCH_FLATMEM_ENABLE 56 def_bool y 57 58config MMU 59 def_bool y 60 61config NO_IOPORT_MAP 62 def_bool y 63 64config GENERIC_CALIBRATE_DELAY 65 def_bool y 66 67config GENERIC_HWEIGHT 68 def_bool y 69 70config STACKTRACE_SUPPORT 71 def_bool y 72 select STACKTRACE 73 74config HAVE_LATENCYTOP_SUPPORT 75 def_bool y 76 77source "init/Kconfig" 78source "kernel/Kconfig.freezer" 79 80menu "ARC Architecture Configuration" 81 82menu "ARC Platform/SoC/Board" 83 84source "arch/arc/plat-sim/Kconfig" 85source "arch/arc/plat-tb10x/Kconfig" 86source "arch/arc/plat-axs10x/Kconfig" 87#New platform adds here 88 89endmenu 90 91choice 92 prompt "ARC Instruction Set" 93 default ISA_ARCOMPACT 94 95config ISA_ARCOMPACT 96 bool "ARCompact ISA" 97 help 98 The original ARC ISA of ARC600/700 cores 99 100config ISA_ARCV2 101 bool "ARC ISA v2" 102 help 103 ISA for the Next Generation ARC-HS cores 104 105endchoice 106 107menu "ARC CPU Configuration" 108 109choice 110 prompt "ARC Core" 111 default ARC_CPU_770 if ISA_ARCOMPACT 112 default ARC_CPU_HS if ISA_ARCV2 113 114if ISA_ARCOMPACT 115 116config ARC_CPU_750D 117 bool "ARC750D" 118 select ARC_CANT_LLSC 119 help 120 Support for ARC750 core 121 122config ARC_CPU_770 123 bool "ARC770" 124 select ARC_HAS_SWAPE 125 help 126 Support for ARC770 core introduced with Rel 4.10 (Summer 2011) 127 This core has a bunch of cool new features: 128 -MMU-v3: Variable Page Sz (4k, 8k, 16k), bigger J-TLB (128x4) 129 Shared Address Spaces (for sharing TLB entires in MMU) 130 -Caches: New Prog Model, Region Flush 131 -Insns: endian swap, load-locked/store-conditional, time-stamp-ctr 132 133endif #ISA_ARCOMPACT 134 135config ARC_CPU_HS 136 bool "ARC-HS" 137 depends on ISA_ARCV2 138 help 139 Support for ARC HS38x Cores based on ARCv2 ISA 140 The notable features are: 141 - SMP configurations of upto 4 core with coherency 142 - Optional L2 Cache and IO-Coherency 143 - Revised Interrupt Architecture (multiple priorites, reg banks, 144 auto stack switch, auto regfile save/restore) 145 - MMUv4 (PIPT dcache, Huge Pages) 146 - Instructions for 147 * 64bit load/store: LDD, STD 148 * Hardware assisted divide/remainder: DIV, REM 149 * Function prologue/epilogue: ENTER_S, LEAVE_S 150 * IRQ enable/disable: CLRI, SETI 151 * pop count: FFS, FLS 152 * SETcc, BMSKN, XBFU... 153 154endchoice 155 156config CPU_BIG_ENDIAN 157 bool "Enable Big Endian Mode" 158 default n 159 help 160 Build kernel for Big Endian Mode of ARC CPU 161 162config SMP 163 bool "Symmetric Multi-Processing" 164 default n 165 select ARC_HAS_COH_CACHES if ISA_ARCV2 166 select ARC_MCIP if ISA_ARCV2 167 help 168 This enables support for systems with more than one CPU. 169 170if SMP 171 172config ARC_HAS_COH_CACHES 173 def_bool n 174 175config ARC_HAS_REENTRANT_IRQ_LV2 176 def_bool n 177 178config ARC_MCIP 179 bool "ARConnect Multicore IP (MCIP) Support " 180 depends on ISA_ARCV2 181 help 182 This IP block enables SMP in ARC-HS38 cores. 183 It provides for cross-core interrupts, multi-core debug 184 hardware semaphores, shared memory,.... 185 186config NR_CPUS 187 int "Maximum number of CPUs (2-4096)" 188 range 2 4096 189 default "4" 190 191endif #SMP 192 193menuconfig ARC_CACHE 194 bool "Enable Cache Support" 195 default y 196 # if SMP, cache enabled ONLY if ARC implementation has cache coherency 197 depends on !SMP || ARC_HAS_COH_CACHES 198 199if ARC_CACHE 200 201config ARC_CACHE_LINE_SHIFT 202 int "Cache Line Length (as power of 2)" 203 range 5 7 204 default "6" 205 help 206 Starting with ARC700 4.9, Cache line length is configurable, 207 This option specifies "N", with Line-len = 2 power N 208 So line lengths of 32, 64, 128 are specified by 5,6,7, respectively 209 Linux only supports same line lengths for I and D caches. 210 211config ARC_HAS_ICACHE 212 bool "Use Instruction Cache" 213 default y 214 215config ARC_HAS_DCACHE 216 bool "Use Data Cache" 217 default y 218 219config ARC_CACHE_PAGES 220 bool "Per Page Cache Control" 221 default y 222 depends on ARC_HAS_ICACHE || ARC_HAS_DCACHE 223 help 224 This can be used to over-ride the global I/D Cache Enable on a 225 per-page basis (but only for pages accessed via MMU such as 226 Kernel Virtual address or User Virtual Address) 227 TLB entries have a per-page Cache Enable Bit. 228 Note that Global I/D ENABLE + Per Page DISABLE works but corollary 229 Global DISABLE + Per Page ENABLE won't work 230 231config ARC_CACHE_VIPT_ALIASING 232 bool "Support VIPT Aliasing D$" 233 depends on ARC_HAS_DCACHE && ISA_ARCOMPACT 234 default n 235 236endif #ARC_CACHE 237 238config ARC_HAS_ICCM 239 bool "Use ICCM" 240 help 241 Single Cycle RAMS to store Fast Path Code 242 default n 243 244config ARC_ICCM_SZ 245 int "ICCM Size in KB" 246 default "64" 247 depends on ARC_HAS_ICCM 248 249config ARC_HAS_DCCM 250 bool "Use DCCM" 251 help 252 Single Cycle RAMS to store Fast Path Data 253 default n 254 255config ARC_DCCM_SZ 256 int "DCCM Size in KB" 257 default "64" 258 depends on ARC_HAS_DCCM 259 260config ARC_DCCM_BASE 261 hex "DCCM map address" 262 default "0xA0000000" 263 depends on ARC_HAS_DCCM 264 265config ARC_HAS_HW_MPY 266 bool "Use Hardware Multiplier (Normal or Faster XMAC)" 267 default y 268 help 269 Influences how gcc generates code for MPY operations. 270 If enabled, MPYxx insns are generated, provided by Standard/XMAC 271 Multipler. Otherwise software multipy lib is used 272 273choice 274 prompt "MMU Version" 275 default ARC_MMU_V3 if ARC_CPU_770 276 default ARC_MMU_V2 if ARC_CPU_750D 277 default ARC_MMU_V4 if ARC_CPU_HS 278 279config ARC_MMU_V1 280 bool "MMU v1" 281 help 282 Orig ARC700 MMU 283 284config ARC_MMU_V2 285 bool "MMU v2" 286 help 287 Fixed the deficiency of v1 - possible thrashing in memcpy sceanrio 288 when 2 D-TLB and 1 I-TLB entries index into same 2way set. 289 290config ARC_MMU_V3 291 bool "MMU v3" 292 depends on ARC_CPU_770 293 help 294 Introduced with ARC700 4.10: New Features 295 Variable Page size (1k-16k), var JTLB size 128 x (2 or 4) 296 Shared Address Spaces (SASID) 297 298config ARC_MMU_V4 299 bool "MMU v4" 300 depends on ISA_ARCV2 301 302endchoice 303 304 305choice 306 prompt "MMU Page Size" 307 default ARC_PAGE_SIZE_8K 308 309config ARC_PAGE_SIZE_8K 310 bool "8KB" 311 help 312 Choose between 8k vs 16k 313 314config ARC_PAGE_SIZE_16K 315 bool "16KB" 316 depends on ARC_MMU_V3 || ARC_MMU_V4 317 318config ARC_PAGE_SIZE_4K 319 bool "4KB" 320 depends on ARC_MMU_V3 || ARC_MMU_V4 321 322endchoice 323 324if ISA_ARCOMPACT 325 326config ARC_COMPACT_IRQ_LEVELS 327 bool "ARCompact IRQ Priorities: High(2)/Low(1)" 328 default n 329 # Timer HAS to be high priority, for any other high priority config 330 select ARC_IRQ3_LV2 331 # if SMP, LV2 enabled ONLY if ARC implementation has LV2 re-entrancy 332 depends on !SMP || ARC_HAS_REENTRANT_IRQ_LV2 333 334if ARC_COMPACT_IRQ_LEVELS 335 336config ARC_IRQ3_LV2 337 bool 338 339config ARC_IRQ5_LV2 340 bool 341 342config ARC_IRQ6_LV2 343 bool 344 345endif #ARC_COMPACT_IRQ_LEVELS 346 347config ARC_FPU_SAVE_RESTORE 348 bool "Enable FPU state persistence across context switch" 349 default n 350 help 351 Double Precision Floating Point unit had dedictaed regs which 352 need to be saved/restored across context-switch. 353 Note that ARC FPU is overly simplistic, unlike say x86, which has 354 hardware pieces to allow software to conditionally save/restore, 355 based on actual usage of FPU by a task. Thus our implemn does 356 this for all tasks in system. 357 358endif #ISA_ARCOMPACT 359 360config ARC_CANT_LLSC 361 def_bool n 362 363config ARC_HAS_LLSC 364 bool "Insn: LLOCK/SCOND (efficient atomic ops)" 365 default y 366 depends on !ARC_CANT_LLSC 367 368config ARC_STAR_9000923308 369 bool "Workaround for llock/scond livelock" 370 default y 371 depends on ISA_ARCV2 && SMP && ARC_HAS_LLSC 372 373config ARC_HAS_SWAPE 374 bool "Insn: SWAPE (endian-swap)" 375 default y 376 377if ISA_ARCV2 378 379config ARC_HAS_LL64 380 bool "Insn: 64bit LDD/STD" 381 help 382 Enable gcc to generate 64-bit load/store instructions 383 ISA mandates even/odd registers to allow encoding of two 384 dest operands with 2 possible source operands. 385 default y 386 387config ARC_HAS_DIV_REM 388 bool "Insn: div, divu, rem, remu" 389 default y 390 391config ARC_HAS_RTC 392 bool "Local 64-bit r/o cycle counter" 393 default n 394 depends on !SMP 395 396config ARC_HAS_GRTC 397 bool "SMP synchronized 64-bit cycle counter" 398 default y 399 depends on SMP 400 401config ARC_NUMBER_OF_INTERRUPTS 402 int "Number of interrupts" 403 range 8 240 404 default 32 405 help 406 This defines the number of interrupts on the ARCv2HS core. 407 It affects the size of vector table. 408 The initial 8 IRQs are fixed (Timer, ICI etc) and although configurable 409 in hardware, it keep things simple for Linux to assume they are always 410 present. 411 412endif # ISA_ARCV2 413 414endmenu # "ARC CPU Configuration" 415 416config LINUX_LINK_BASE 417 hex "Linux Link Address" 418 default "0x80000000" 419 help 420 ARC700 divides the 32 bit phy address space into two equal halves 421 -Lower 2G (0 - 0x7FFF_FFFF ) is user virtual, translated by MMU 422 -Upper 2G (0x8000_0000 onwards) is untranslated, for kernel 423 Typically Linux kernel is linked at the start of untransalted addr, 424 hence the default value of 0x8zs. 425 However some customers have peripherals mapped at this addr, so 426 Linux needs to be scooted a bit. 427 If you don't know what the above means, leave this setting alone. 428 429config ARC_CURR_IN_REG 430 bool "Dedicate Register r25 for current_task pointer" 431 default y 432 help 433 This reserved Register R25 to point to Current Task in 434 kernel mode. This saves memory access for each such access 435 436 437config ARC_EMUL_UNALIGNED 438 bool "Emulate unaligned memory access (userspace only)" 439 default N 440 select SYSCTL_ARCH_UNALIGN_NO_WARN 441 select SYSCTL_ARCH_UNALIGN_ALLOW 442 depends on ISA_ARCOMPACT 443 help 444 This enables misaligned 16 & 32 bit memory access from user space. 445 Use ONLY-IF-ABS-NECESSARY as it will be very slow and also can hide 446 potential bugs in code 447 448config HZ 449 int "Timer Frequency" 450 default 100 451 452config ARC_METAWARE_HLINK 453 bool "Support for Metaware debugger assisted Host access" 454 default n 455 help 456 This options allows a Linux userland apps to directly access 457 host file system (open/creat/read/write etc) with help from 458 Metaware Debugger. This can come in handy for Linux-host communication 459 when there is no real usable peripheral such as EMAC. 460 461menuconfig ARC_DBG 462 bool "ARC debugging" 463 default y 464 465if ARC_DBG 466 467config ARC_DW2_UNWIND 468 bool "Enable DWARF specific kernel stack unwind" 469 default y 470 select KALLSYMS 471 help 472 Compiles the kernel with DWARF unwind information and can be used 473 to get stack backtraces. 474 475 If you say Y here the resulting kernel image will be slightly larger 476 but not slower, and it will give very useful debugging information. 477 If you don't debug the kernel, you can say N, but we may not be able 478 to solve problems without frame unwind information 479 480config ARC_DBG_TLB_PARANOIA 481 bool "Paranoia Checks in Low Level TLB Handlers" 482 default n 483 484config ARC_DBG_TLB_MISS_COUNT 485 bool "Profile TLB Misses" 486 default n 487 select DEBUG_FS 488 help 489 Counts number of I and D TLB Misses and exports them via Debugfs 490 The counters can be cleared via Debugfs as well 491 492if SMP 493 494config ARC_IPI_DBG 495 bool "Debug Inter Core interrupts" 496 default n 497 498endif 499 500endif 501 502config ARC_UBOOT_SUPPORT 503 bool "Support uboot arg Handling" 504 default n 505 help 506 ARC Linux by default checks for uboot provided args as pointers to 507 external cmdline or DTB. This however breaks in absence of uboot, 508 when booting from Metaware debugger directly, as the registers are 509 not zeroed out on reset by mdb and/or ARCv2 based cores. The bogus 510 registers look like uboot args to kernel which then chokes. 511 So only enable the uboot arg checking/processing if users are sure 512 of uboot being in play. 513 514config ARC_BUILTIN_DTB_NAME 515 string "Built in DTB" 516 help 517 Set the name of the DTB to embed in the vmlinux binary 518 Leaving it blank selects the minimal "skeleton" dtb 519 520source "kernel/Kconfig.preempt" 521 522menu "Executable file formats" 523source "fs/Kconfig.binfmt" 524endmenu 525 526endmenu # "ARC Architecture Configuration" 527 528source "mm/Kconfig" 529source "net/Kconfig" 530source "drivers/Kconfig" 531source "fs/Kconfig" 532source "arch/arc/Kconfig.debug" 533source "security/Kconfig" 534source "crypto/Kconfig" 535source "lib/Kconfig" 536source "kernel/power/Kconfig" 537