1# 2# Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com) 3# 4# This program is free software; you can redistribute it and/or modify 5# it under the terms of the GNU General Public License version 2 as 6# published by the Free Software Foundation. 7# 8 9config ARC 10 def_bool y 11 select ARCH_SUPPORTS_ATOMIC_RMW if ARC_HAS_LLSC 12 select BUILDTIME_EXTABLE_SORT 13 select CLKSRC_OF 14 select CLONE_BACKWARDS 15 select COMMON_CLK 16 select GENERIC_ATOMIC64 17 select GENERIC_CLOCKEVENTS 18 select GENERIC_FIND_FIRST_BIT 19 # for now, we don't need GENERIC_IRQ_PROBE, CONFIG_GENERIC_IRQ_CHIP 20 select GENERIC_IRQ_SHOW 21 select GENERIC_PCI_IOMAP 22 select GENERIC_PENDING_IRQ if SMP 23 select GENERIC_SMP_IDLE_THREAD 24 select HAVE_ARCH_KGDB 25 select HAVE_ARCH_TRACEHOOK 26 select HAVE_FUTEX_CMPXCHG 27 select HAVE_IOREMAP_PROT 28 select HAVE_KPROBES 29 select HAVE_KRETPROBES 30 select HAVE_MEMBLOCK 31 select HAVE_MOD_ARCH_SPECIFIC if ARC_DW2_UNWIND 32 select HAVE_OPROFILE 33 select HAVE_PERF_EVENTS 34 select HANDLE_DOMAIN_IRQ 35 select IRQ_DOMAIN 36 select MODULES_USE_ELF_RELA 37 select NO_BOOTMEM 38 select OF 39 select OF_EARLY_FLATTREE 40 select OF_RESERVED_MEM 41 select PERF_USE_VMALLOC 42 select HAVE_DEBUG_STACKOVERFLOW 43 select HAVE_GENERIC_DMA_COHERENT 44 45config MIGHT_HAVE_PCI 46 bool 47 48config TRACE_IRQFLAGS_SUPPORT 49 def_bool y 50 51config LOCKDEP_SUPPORT 52 def_bool y 53 54config SCHED_OMIT_FRAME_POINTER 55 def_bool y 56 57config GENERIC_CSUM 58 def_bool y 59 60config RWSEM_GENERIC_SPINLOCK 61 def_bool y 62 63config ARCH_DISCONTIGMEM_ENABLE 64 def_bool y 65 66config ARCH_FLATMEM_ENABLE 67 def_bool y 68 69config MMU 70 def_bool y 71 72config NO_IOPORT_MAP 73 def_bool y 74 75config GENERIC_CALIBRATE_DELAY 76 def_bool y 77 78config GENERIC_HWEIGHT 79 def_bool y 80 81config STACKTRACE_SUPPORT 82 def_bool y 83 select STACKTRACE 84 85config HAVE_ARCH_TRANSPARENT_HUGEPAGE 86 def_bool y 87 depends on ARC_MMU_V4 88 89source "init/Kconfig" 90source "kernel/Kconfig.freezer" 91 92menu "ARC Architecture Configuration" 93 94menu "ARC Platform/SoC/Board" 95 96source "arch/arc/plat-sim/Kconfig" 97source "arch/arc/plat-tb10x/Kconfig" 98source "arch/arc/plat-axs10x/Kconfig" 99#New platform adds here 100 101endmenu 102 103choice 104 prompt "ARC Instruction Set" 105 default ISA_ARCOMPACT 106 107config ISA_ARCOMPACT 108 bool "ARCompact ISA" 109 help 110 The original ARC ISA of ARC600/700 cores 111 112config ISA_ARCV2 113 bool "ARC ISA v2" 114 help 115 ISA for the Next Generation ARC-HS cores 116 117endchoice 118 119menu "ARC CPU Configuration" 120 121choice 122 prompt "ARC Core" 123 default ARC_CPU_770 if ISA_ARCOMPACT 124 default ARC_CPU_HS if ISA_ARCV2 125 126if ISA_ARCOMPACT 127 128config ARC_CPU_750D 129 bool "ARC750D" 130 select ARC_CANT_LLSC 131 help 132 Support for ARC750 core 133 134config ARC_CPU_770 135 bool "ARC770" 136 select ARC_HAS_SWAPE 137 help 138 Support for ARC770 core introduced with Rel 4.10 (Summer 2011) 139 This core has a bunch of cool new features: 140 -MMU-v3: Variable Page Sz (4k, 8k, 16k), bigger J-TLB (128x4) 141 Shared Address Spaces (for sharing TLB entires in MMU) 142 -Caches: New Prog Model, Region Flush 143 -Insns: endian swap, load-locked/store-conditional, time-stamp-ctr 144 145endif #ISA_ARCOMPACT 146 147config ARC_CPU_HS 148 bool "ARC-HS" 149 depends on ISA_ARCV2 150 help 151 Support for ARC HS38x Cores based on ARCv2 ISA 152 The notable features are: 153 - SMP configurations of upto 4 core with coherency 154 - Optional L2 Cache and IO-Coherency 155 - Revised Interrupt Architecture (multiple priorites, reg banks, 156 auto stack switch, auto regfile save/restore) 157 - MMUv4 (PIPT dcache, Huge Pages) 158 - Instructions for 159 * 64bit load/store: LDD, STD 160 * Hardware assisted divide/remainder: DIV, REM 161 * Function prologue/epilogue: ENTER_S, LEAVE_S 162 * IRQ enable/disable: CLRI, SETI 163 * pop count: FFS, FLS 164 * SETcc, BMSKN, XBFU... 165 166endchoice 167 168config CPU_BIG_ENDIAN 169 bool "Enable Big Endian Mode" 170 default n 171 help 172 Build kernel for Big Endian Mode of ARC CPU 173 174config SMP 175 bool "Symmetric Multi-Processing" 176 default n 177 select ARC_HAS_COH_CACHES if ISA_ARCV2 178 select ARC_MCIP if ISA_ARCV2 179 help 180 This enables support for systems with more than one CPU. 181 182if SMP 183 184config ARC_HAS_COH_CACHES 185 def_bool n 186 187config ARC_HAS_REENTRANT_IRQ_LV2 188 def_bool n 189 190config ARC_MCIP 191 bool "ARConnect Multicore IP (MCIP) Support " 192 depends on ISA_ARCV2 193 help 194 This IP block enables SMP in ARC-HS38 cores. 195 It provides for cross-core interrupts, multi-core debug 196 hardware semaphores, shared memory,.... 197 198config NR_CPUS 199 int "Maximum number of CPUs (2-4096)" 200 range 2 4096 201 default "4" 202 203config ARC_SMP_HALT_ON_RESET 204 bool "Enable Halt-on-reset boot mode" 205 default y if ARC_UBOOT_SUPPORT 206 help 207 In SMP configuration cores can be configured as Halt-on-reset 208 or they could all start at same time. For Halt-on-reset, non 209 masters are parked until Master kicks them so they can start of 210 at designated entry point. For other case, all jump to common 211 entry point and spin wait for Master's signal. 212 213endif #SMP 214 215menuconfig ARC_CACHE 216 bool "Enable Cache Support" 217 default y 218 # if SMP, cache enabled ONLY if ARC implementation has cache coherency 219 depends on !SMP || ARC_HAS_COH_CACHES 220 221if ARC_CACHE 222 223config ARC_CACHE_LINE_SHIFT 224 int "Cache Line Length (as power of 2)" 225 range 5 7 226 default "6" 227 help 228 Starting with ARC700 4.9, Cache line length is configurable, 229 This option specifies "N", with Line-len = 2 power N 230 So line lengths of 32, 64, 128 are specified by 5,6,7, respectively 231 Linux only supports same line lengths for I and D caches. 232 233config ARC_HAS_ICACHE 234 bool "Use Instruction Cache" 235 default y 236 237config ARC_HAS_DCACHE 238 bool "Use Data Cache" 239 default y 240 241config ARC_CACHE_PAGES 242 bool "Per Page Cache Control" 243 default y 244 depends on ARC_HAS_ICACHE || ARC_HAS_DCACHE 245 help 246 This can be used to over-ride the global I/D Cache Enable on a 247 per-page basis (but only for pages accessed via MMU such as 248 Kernel Virtual address or User Virtual Address) 249 TLB entries have a per-page Cache Enable Bit. 250 Note that Global I/D ENABLE + Per Page DISABLE works but corollary 251 Global DISABLE + Per Page ENABLE won't work 252 253config ARC_CACHE_VIPT_ALIASING 254 bool "Support VIPT Aliasing D$" 255 depends on ARC_HAS_DCACHE && ISA_ARCOMPACT 256 default n 257 258endif #ARC_CACHE 259 260config ARC_HAS_ICCM 261 bool "Use ICCM" 262 help 263 Single Cycle RAMS to store Fast Path Code 264 default n 265 266config ARC_ICCM_SZ 267 int "ICCM Size in KB" 268 default "64" 269 depends on ARC_HAS_ICCM 270 271config ARC_HAS_DCCM 272 bool "Use DCCM" 273 help 274 Single Cycle RAMS to store Fast Path Data 275 default n 276 277config ARC_DCCM_SZ 278 int "DCCM Size in KB" 279 default "64" 280 depends on ARC_HAS_DCCM 281 282config ARC_DCCM_BASE 283 hex "DCCM map address" 284 default "0xA0000000" 285 depends on ARC_HAS_DCCM 286 287choice 288 prompt "MMU Version" 289 default ARC_MMU_V3 if ARC_CPU_770 290 default ARC_MMU_V2 if ARC_CPU_750D 291 default ARC_MMU_V4 if ARC_CPU_HS 292 293if ISA_ARCOMPACT 294 295config ARC_MMU_V1 296 bool "MMU v1" 297 help 298 Orig ARC700 MMU 299 300config ARC_MMU_V2 301 bool "MMU v2" 302 help 303 Fixed the deficiency of v1 - possible thrashing in memcpy sceanrio 304 when 2 D-TLB and 1 I-TLB entries index into same 2way set. 305 306config ARC_MMU_V3 307 bool "MMU v3" 308 depends on ARC_CPU_770 309 help 310 Introduced with ARC700 4.10: New Features 311 Variable Page size (1k-16k), var JTLB size 128 x (2 or 4) 312 Shared Address Spaces (SASID) 313 314endif 315 316config ARC_MMU_V4 317 bool "MMU v4" 318 depends on ISA_ARCV2 319 320endchoice 321 322 323choice 324 prompt "MMU Page Size" 325 default ARC_PAGE_SIZE_8K 326 327config ARC_PAGE_SIZE_8K 328 bool "8KB" 329 help 330 Choose between 8k vs 16k 331 332config ARC_PAGE_SIZE_16K 333 bool "16KB" 334 depends on ARC_MMU_V3 || ARC_MMU_V4 335 336config ARC_PAGE_SIZE_4K 337 bool "4KB" 338 depends on ARC_MMU_V3 || ARC_MMU_V4 339 340endchoice 341 342choice 343 prompt "MMU Super Page Size" 344 depends on ISA_ARCV2 && TRANSPARENT_HUGEPAGE 345 default ARC_HUGEPAGE_2M 346 347config ARC_HUGEPAGE_2M 348 bool "2MB" 349 350config ARC_HUGEPAGE_16M 351 bool "16MB" 352 353endchoice 354 355config NODES_SHIFT 356 int "Maximum NUMA Nodes (as a power of 2)" 357 default "1" if !DISCONTIGMEM 358 default "2" if DISCONTIGMEM 359 depends on NEED_MULTIPLE_NODES 360 ---help--- 361 Accessing memory beyond 1GB (with or w/o PAE) requires 2 memory 362 zones. 363 364if ISA_ARCOMPACT 365 366config ARC_COMPACT_IRQ_LEVELS 367 bool "ARCompact IRQ Priorities: High(2)/Low(1)" 368 default n 369 # Timer HAS to be high priority, for any other high priority config 370 select ARC_IRQ3_LV2 371 # if SMP, LV2 enabled ONLY if ARC implementation has LV2 re-entrancy 372 depends on !SMP || ARC_HAS_REENTRANT_IRQ_LV2 373 374if ARC_COMPACT_IRQ_LEVELS 375 376config ARC_IRQ3_LV2 377 bool 378 379config ARC_IRQ5_LV2 380 bool 381 382config ARC_IRQ6_LV2 383 bool 384 385endif #ARC_COMPACT_IRQ_LEVELS 386 387config ARC_FPU_SAVE_RESTORE 388 bool "Enable FPU state persistence across context switch" 389 default n 390 help 391 Double Precision Floating Point unit had dedictaed regs which 392 need to be saved/restored across context-switch. 393 Note that ARC FPU is overly simplistic, unlike say x86, which has 394 hardware pieces to allow software to conditionally save/restore, 395 based on actual usage of FPU by a task. Thus our implemn does 396 this for all tasks in system. 397 398endif #ISA_ARCOMPACT 399 400config ARC_CANT_LLSC 401 def_bool n 402 403config ARC_HAS_LLSC 404 bool "Insn: LLOCK/SCOND (efficient atomic ops)" 405 default y 406 depends on !ARC_CANT_LLSC 407 408config ARC_STAR_9000923308 409 bool "Workaround for llock/scond livelock" 410 default n 411 depends on ISA_ARCV2 && SMP && ARC_HAS_LLSC 412 413config ARC_HAS_SWAPE 414 bool "Insn: SWAPE (endian-swap)" 415 default y 416 417if ISA_ARCV2 418 419config ARC_HAS_LL64 420 bool "Insn: 64bit LDD/STD" 421 help 422 Enable gcc to generate 64-bit load/store instructions 423 ISA mandates even/odd registers to allow encoding of two 424 dest operands with 2 possible source operands. 425 default y 426 427config ARC_HAS_DIV_REM 428 bool "Insn: div, divu, rem, remu" 429 default y 430 431config ARC_HAS_RTC 432 bool "Local 64-bit r/o cycle counter" 433 default n 434 depends on !SMP 435 436config ARC_HAS_GFRC 437 bool "SMP synchronized 64-bit cycle counter" 438 default y 439 depends on SMP 440 441config ARC_NUMBER_OF_INTERRUPTS 442 int "Number of interrupts" 443 range 8 240 444 default 32 445 help 446 This defines the number of interrupts on the ARCv2HS core. 447 It affects the size of vector table. 448 The initial 8 IRQs are fixed (Timer, ICI etc) and although configurable 449 in hardware, it keep things simple for Linux to assume they are always 450 present. 451 452endif # ISA_ARCV2 453 454endmenu # "ARC CPU Configuration" 455 456config LINUX_LINK_BASE 457 hex "Linux Link Address" 458 default "0x80000000" 459 help 460 ARC700 divides the 32 bit phy address space into two equal halves 461 -Lower 2G (0 - 0x7FFF_FFFF ) is user virtual, translated by MMU 462 -Upper 2G (0x8000_0000 onwards) is untranslated, for kernel 463 Typically Linux kernel is linked at the start of untransalted addr, 464 hence the default value of 0x8zs. 465 However some customers have peripherals mapped at this addr, so 466 Linux needs to be scooted a bit. 467 If you don't know what the above means, leave this setting alone. 468 This needs to match memory start address specified in Device Tree 469 470config HIGHMEM 471 bool "High Memory Support" 472 select DISCONTIGMEM 473 help 474 With ARC 2G:2G address split, only upper 2G is directly addressable by 475 kernel. Enable this to potentially allow access to rest of 2G and PAE 476 in future 477 478config ARC_HAS_PAE40 479 bool "Support for the 40-bit Physical Address Extension" 480 default n 481 depends on ISA_ARCV2 482 help 483 Enable access to physical memory beyond 4G, only supported on 484 ARC cores with 40 bit Physical Addressing support 485 486config ARCH_PHYS_ADDR_T_64BIT 487 def_bool ARC_HAS_PAE40 488 489config ARCH_DMA_ADDR_T_64BIT 490 bool 491 492config ARC_PLAT_NEEDS_PHYS_TO_DMA 493 bool 494 495config ARC_CURR_IN_REG 496 bool "Dedicate Register r25 for current_task pointer" 497 default y 498 help 499 This reserved Register R25 to point to Current Task in 500 kernel mode. This saves memory access for each such access 501 502 503config ARC_EMUL_UNALIGNED 504 bool "Emulate unaligned memory access (userspace only)" 505 default N 506 select SYSCTL_ARCH_UNALIGN_NO_WARN 507 select SYSCTL_ARCH_UNALIGN_ALLOW 508 depends on ISA_ARCOMPACT 509 help 510 This enables misaligned 16 & 32 bit memory access from user space. 511 Use ONLY-IF-ABS-NECESSARY as it will be very slow and also can hide 512 potential bugs in code 513 514config HZ 515 int "Timer Frequency" 516 default 100 517 518config ARC_METAWARE_HLINK 519 bool "Support for Metaware debugger assisted Host access" 520 default n 521 help 522 This options allows a Linux userland apps to directly access 523 host file system (open/creat/read/write etc) with help from 524 Metaware Debugger. This can come in handy for Linux-host communication 525 when there is no real usable peripheral such as EMAC. 526 527menuconfig ARC_DBG 528 bool "ARC debugging" 529 default y 530 531if ARC_DBG 532 533config ARC_DW2_UNWIND 534 bool "Enable DWARF specific kernel stack unwind" 535 default y 536 select KALLSYMS 537 help 538 Compiles the kernel with DWARF unwind information and can be used 539 to get stack backtraces. 540 541 If you say Y here the resulting kernel image will be slightly larger 542 but not slower, and it will give very useful debugging information. 543 If you don't debug the kernel, you can say N, but we may not be able 544 to solve problems without frame unwind information 545 546config ARC_DBG_TLB_PARANOIA 547 bool "Paranoia Checks in Low Level TLB Handlers" 548 default n 549 550config ARC_DBG_TLB_MISS_COUNT 551 bool "Profile TLB Misses" 552 default n 553 select DEBUG_FS 554 help 555 Counts number of I and D TLB Misses and exports them via Debugfs 556 The counters can be cleared via Debugfs as well 557 558endif 559 560config ARC_UBOOT_SUPPORT 561 bool "Support uboot arg Handling" 562 default n 563 help 564 ARC Linux by default checks for uboot provided args as pointers to 565 external cmdline or DTB. This however breaks in absence of uboot, 566 when booting from Metaware debugger directly, as the registers are 567 not zeroed out on reset by mdb and/or ARCv2 based cores. The bogus 568 registers look like uboot args to kernel which then chokes. 569 So only enable the uboot arg checking/processing if users are sure 570 of uboot being in play. 571 572config ARC_BUILTIN_DTB_NAME 573 string "Built in DTB" 574 help 575 Set the name of the DTB to embed in the vmlinux binary 576 Leaving it blank selects the minimal "skeleton" dtb 577 578source "kernel/Kconfig.preempt" 579 580menu "Executable file formats" 581source "fs/Kconfig.binfmt" 582endmenu 583 584endmenu # "ARC Architecture Configuration" 585 586source "mm/Kconfig" 587 588config FORCE_MAX_ZONEORDER 589 int "Maximum zone order" 590 default "12" if ARC_HUGEPAGE_16M 591 default "11" 592 593source "net/Kconfig" 594source "drivers/Kconfig" 595 596menu "Bus Support" 597 598config PCI 599 bool "PCI support" if MIGHT_HAVE_PCI 600 help 601 PCI is the name of a bus system, i.e., the way the CPU talks to 602 the other stuff inside your box. Find out if your board/platform 603 has PCI. 604 605 Note: PCIe support for Synopsys Device will be available only 606 when HAPS DX is configured with PCIe RC bitmap. If you have PCI, 607 say Y, otherwise N. 608 609config PCI_SYSCALL 610 def_bool PCI 611 612source "drivers/pci/Kconfig" 613 614endmenu 615 616source "fs/Kconfig" 617source "arch/arc/Kconfig.debug" 618source "security/Kconfig" 619source "crypto/Kconfig" 620source "lib/Kconfig" 621source "kernel/power/Kconfig" 622