1# SPDX-License-Identifier: GPL-2.0-only 2# 3# Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com) 4# 5 6config ARC 7 def_bool y 8 select ARC_TIMERS 9 select ARCH_HAS_CACHE_LINE_SIZE 10 select ARCH_HAS_DEBUG_VM_PGTABLE 11 select ARCH_HAS_DMA_PREP_COHERENT 12 select ARCH_HAS_PTE_SPECIAL 13 select ARCH_HAS_SETUP_DMA_OPS 14 select ARCH_HAS_SYNC_DMA_FOR_CPU 15 select ARCH_HAS_SYNC_DMA_FOR_DEVICE 16 select ARCH_SUPPORTS_ATOMIC_RMW if ARC_HAS_LLSC 17 select ARCH_32BIT_OFF_T 18 select BUILDTIME_TABLE_SORT 19 select CLONE_BACKWARDS 20 select COMMON_CLK 21 select DMA_DIRECT_REMAP 22 select GENERIC_ATOMIC64 if !ISA_ARCV2 || !(ARC_HAS_LL64 && ARC_HAS_LLSC) 23 # for now, we don't need GENERIC_IRQ_PROBE, CONFIG_GENERIC_IRQ_CHIP 24 select GENERIC_IRQ_SHOW 25 select GENERIC_PCI_IOMAP 26 select GENERIC_PENDING_IRQ if SMP 27 select GENERIC_SCHED_CLOCK 28 select GENERIC_SMP_IDLE_THREAD 29 select HAVE_ARCH_KGDB 30 select HAVE_ARCH_TRACEHOOK 31 select HAVE_ARCH_TRANSPARENT_HUGEPAGE if ARC_MMU_V4 32 select HAVE_DEBUG_STACKOVERFLOW 33 select HAVE_DEBUG_KMEMLEAK 34 select HAVE_IOREMAP_PROT 35 select HAVE_KERNEL_GZIP 36 select HAVE_KERNEL_LZMA 37 select HAVE_KPROBES 38 select HAVE_KRETPROBES 39 select HAVE_MOD_ARCH_SPECIFIC 40 select HAVE_PERF_EVENTS 41 select IRQ_DOMAIN 42 select MODULES_USE_ELF_RELA 43 select OF 44 select OF_EARLY_FLATTREE 45 select PCI_SYSCALL if PCI 46 select PERF_USE_VMALLOC if ARC_CACHE_VIPT_ALIASING 47 select HAVE_ARCH_JUMP_LABEL if ISA_ARCV2 && !CPU_ENDIAN_BE32 48 select TRACE_IRQFLAGS_SUPPORT 49 50config LOCKDEP_SUPPORT 51 def_bool y 52 53config SCHED_OMIT_FRAME_POINTER 54 def_bool y 55 56config GENERIC_CSUM 57 def_bool y 58 59config ARCH_FLATMEM_ENABLE 60 def_bool y 61 62config MMU 63 def_bool y 64 65config NO_IOPORT_MAP 66 def_bool y 67 68config GENERIC_CALIBRATE_DELAY 69 def_bool y 70 71config GENERIC_HWEIGHT 72 def_bool y 73 74config STACKTRACE_SUPPORT 75 def_bool y 76 select STACKTRACE 77 78menu "ARC Architecture Configuration" 79 80menu "ARC Platform/SoC/Board" 81 82source "arch/arc/plat-tb10x/Kconfig" 83source "arch/arc/plat-axs10x/Kconfig" 84source "arch/arc/plat-hsdk/Kconfig" 85 86endmenu 87 88choice 89 prompt "ARC Instruction Set" 90 default ISA_ARCV2 91 92config ISA_ARCOMPACT 93 bool "ARCompact ISA" 94 select CPU_NO_EFFICIENT_FFS 95 help 96 The original ARC ISA of ARC600/700 cores 97 98config ISA_ARCV2 99 bool "ARC ISA v2" 100 select ARC_TIMERS_64BIT 101 help 102 ISA for the Next Generation ARC-HS cores 103 104endchoice 105 106menu "ARC CPU Configuration" 107 108choice 109 prompt "ARC Core" 110 default ARC_CPU_770 if ISA_ARCOMPACT 111 default ARC_CPU_HS if ISA_ARCV2 112 113config ARC_CPU_770 114 bool "ARC770" 115 depends on ISA_ARCOMPACT 116 select ARC_HAS_SWAPE 117 help 118 Support for ARC770 core introduced with Rel 4.10 (Summer 2011) 119 This core has a bunch of cool new features: 120 -MMU-v3: Variable Page Sz (4k, 8k, 16k), bigger J-TLB (128x4) 121 Shared Address Spaces (for sharing TLB entries in MMU) 122 -Caches: New Prog Model, Region Flush 123 -Insns: endian swap, load-locked/store-conditional, time-stamp-ctr 124 125config ARC_CPU_HS 126 bool "ARC-HS" 127 depends on ISA_ARCV2 128 help 129 Support for ARC HS38x Cores based on ARCv2 ISA 130 The notable features are: 131 - SMP configurations of up to 4 cores with coherency 132 - Optional L2 Cache and IO-Coherency 133 - Revised Interrupt Architecture (multiple priorites, reg banks, 134 auto stack switch, auto regfile save/restore) 135 - MMUv4 (PIPT dcache, Huge Pages) 136 - Instructions for 137 * 64bit load/store: LDD, STD 138 * Hardware assisted divide/remainder: DIV, REM 139 * Function prologue/epilogue: ENTER_S, LEAVE_S 140 * IRQ enable/disable: CLRI, SETI 141 * pop count: FFS, FLS 142 * SETcc, BMSKN, XBFU... 143 144endchoice 145 146config ARC_TUNE_MCPU 147 string "Override default -mcpu compiler flag" 148 default "" 149 help 150 Override default -mcpu=xxx compiler flag (which is set depending on 151 the ISA version) with the specified value. 152 NOTE: If specified flag isn't supported by current compiler the 153 ISA default value will be used as a fallback. 154 155config CPU_BIG_ENDIAN 156 bool "Enable Big Endian Mode" 157 help 158 Build kernel for Big Endian Mode of ARC CPU 159 160config SMP 161 bool "Symmetric Multi-Processing" 162 select ARC_MCIP if ISA_ARCV2 163 help 164 This enables support for systems with more than one CPU. 165 166if SMP 167 168config NR_CPUS 169 int "Maximum number of CPUs (2-4096)" 170 range 2 4096 171 default "4" 172 173config ARC_SMP_HALT_ON_RESET 174 bool "Enable Halt-on-reset boot mode" 175 help 176 In SMP configuration cores can be configured as Halt-on-reset 177 or they could all start at same time. For Halt-on-reset, non 178 masters are parked until Master kicks them so they can start off 179 at designated entry point. For other case, all jump to common 180 entry point and spin wait for Master's signal. 181 182endif #SMP 183 184config ARC_MCIP 185 bool "ARConnect Multicore IP (MCIP) Support " 186 depends on ISA_ARCV2 187 default y if SMP 188 help 189 This IP block enables SMP in ARC-HS38 cores. 190 It provides for cross-core interrupts, multi-core debug 191 hardware semaphores, shared memory,.... 192 193menuconfig ARC_CACHE 194 bool "Enable Cache Support" 195 default y 196 197if ARC_CACHE 198 199config ARC_CACHE_LINE_SHIFT 200 int "Cache Line Length (as power of 2)" 201 range 5 7 202 default "6" 203 help 204 Starting with ARC700 4.9, Cache line length is configurable, 205 This option specifies "N", with Line-len = 2 power N 206 So line lengths of 32, 64, 128 are specified by 5,6,7, respectively 207 Linux only supports same line lengths for I and D caches. 208 209config ARC_HAS_ICACHE 210 bool "Use Instruction Cache" 211 default y 212 213config ARC_HAS_DCACHE 214 bool "Use Data Cache" 215 default y 216 217config ARC_CACHE_PAGES 218 bool "Per Page Cache Control" 219 default y 220 depends on ARC_HAS_ICACHE || ARC_HAS_DCACHE 221 help 222 This can be used to over-ride the global I/D Cache Enable on a 223 per-page basis (but only for pages accessed via MMU such as 224 Kernel Virtual address or User Virtual Address) 225 TLB entries have a per-page Cache Enable Bit. 226 Note that Global I/D ENABLE + Per Page DISABLE works but corollary 227 Global DISABLE + Per Page ENABLE won't work 228 229config ARC_CACHE_VIPT_ALIASING 230 bool "Support VIPT Aliasing D$" 231 depends on ARC_HAS_DCACHE && ISA_ARCOMPACT 232 233endif #ARC_CACHE 234 235config ARC_HAS_ICCM 236 bool "Use ICCM" 237 help 238 Single Cycle RAMS to store Fast Path Code 239 240config ARC_ICCM_SZ 241 int "ICCM Size in KB" 242 default "64" 243 depends on ARC_HAS_ICCM 244 245config ARC_HAS_DCCM 246 bool "Use DCCM" 247 help 248 Single Cycle RAMS to store Fast Path Data 249 250config ARC_DCCM_SZ 251 int "DCCM Size in KB" 252 default "64" 253 depends on ARC_HAS_DCCM 254 255config ARC_DCCM_BASE 256 hex "DCCM map address" 257 default "0xA0000000" 258 depends on ARC_HAS_DCCM 259 260choice 261 prompt "MMU Version" 262 default ARC_MMU_V3 if ISA_ARCOMPACT 263 default ARC_MMU_V4 if ISA_ARCV2 264 265config ARC_MMU_V3 266 bool "MMU v3" 267 depends on ISA_ARCOMPACT 268 help 269 Introduced with ARC700 4.10: New Features 270 Variable Page size (1k-16k), var JTLB size 128 x (2 or 4) 271 Shared Address Spaces (SASID) 272 273config ARC_MMU_V4 274 bool "MMU v4" 275 depends on ISA_ARCV2 276 277endchoice 278 279 280choice 281 prompt "MMU Page Size" 282 default ARC_PAGE_SIZE_8K 283 284config ARC_PAGE_SIZE_8K 285 bool "8KB" 286 help 287 Choose between 8k vs 16k 288 289config ARC_PAGE_SIZE_16K 290 bool "16KB" 291 292config ARC_PAGE_SIZE_4K 293 bool "4KB" 294 depends on ARC_MMU_V3 || ARC_MMU_V4 295 296endchoice 297 298choice 299 prompt "MMU Super Page Size" 300 depends on ISA_ARCV2 && TRANSPARENT_HUGEPAGE 301 default ARC_HUGEPAGE_2M 302 303config ARC_HUGEPAGE_2M 304 bool "2MB" 305 306config ARC_HUGEPAGE_16M 307 bool "16MB" 308 309endchoice 310 311config PGTABLE_LEVELS 312 int "Number of Page table levels" 313 default 2 314 315config ARC_COMPACT_IRQ_LEVELS 316 depends on ISA_ARCOMPACT 317 bool "Setup Timer IRQ as high Priority" 318 # if SMP, LV2 enabled ONLY if ARC implementation has LV2 re-entrancy 319 depends on !SMP 320 321config ARC_FPU_SAVE_RESTORE 322 bool "Enable FPU state persistence across context switch" 323 help 324 ARCompact FPU has internal registers to assist with Double precision 325 Floating Point operations. There are control and stauts registers 326 for floating point exceptions and rounding modes. These are 327 preserved across task context switch when enabled. 328 329config ARC_CANT_LLSC 330 def_bool n 331 332config ARC_HAS_LLSC 333 bool "Insn: LLOCK/SCOND (efficient atomic ops)" 334 default y 335 depends on !ARC_CANT_LLSC 336 337config ARC_HAS_SWAPE 338 bool "Insn: SWAPE (endian-swap)" 339 default y 340 341if ISA_ARCV2 342 343config ARC_USE_UNALIGNED_MEM_ACCESS 344 bool "Enable unaligned access in HW" 345 default y 346 select HAVE_EFFICIENT_UNALIGNED_ACCESS 347 help 348 The ARC HS architecture supports unaligned memory access 349 which is disabled by default. Enable unaligned access in 350 hardware and use software to use it 351 352config ARC_HAS_LL64 353 bool "Insn: 64bit LDD/STD" 354 help 355 Enable gcc to generate 64-bit load/store instructions 356 ISA mandates even/odd registers to allow encoding of two 357 dest operands with 2 possible source operands. 358 default y 359 360config ARC_HAS_DIV_REM 361 bool "Insn: div, divu, rem, remu" 362 default y 363 364config ARC_HAS_ACCL_REGS 365 bool "Reg Pair ACCL:ACCH (FPU and/or MPY > 6 and/or DSP)" 366 default y 367 help 368 Depending on the configuration, CPU can contain accumulator reg-pair 369 (also referred to as r58:r59). These can also be used by gcc as GPR so 370 kernel needs to save/restore per process 371 372config ARC_DSP_HANDLED 373 def_bool n 374 375config ARC_DSP_SAVE_RESTORE_REGS 376 def_bool n 377 378choice 379 prompt "DSP support" 380 default ARC_DSP_NONE 381 help 382 Depending on the configuration, CPU can contain DSP registers 383 (ACC0_GLO, ACC0_GHI, DSP_BFLY0, DSP_CTRL, DSP_FFT_CTRL). 384 Below are options describing how to handle these registers in 385 interrupt entry / exit and in context switch. 386 387config ARC_DSP_NONE 388 bool "No DSP extension presence in HW" 389 help 390 No DSP extension presence in HW 391 392config ARC_DSP_KERNEL 393 bool "DSP extension in HW, no support for userspace" 394 select ARC_HAS_ACCL_REGS 395 select ARC_DSP_HANDLED 396 help 397 DSP extension presence in HW, no support for DSP-enabled userspace 398 applications. We don't save / restore DSP registers and only do 399 some minimal preparations so userspace won't be able to break kernel 400 401config ARC_DSP_USERSPACE 402 bool "Support DSP for userspace apps" 403 select ARC_HAS_ACCL_REGS 404 select ARC_DSP_HANDLED 405 select ARC_DSP_SAVE_RESTORE_REGS 406 help 407 DSP extension presence in HW, support save / restore DSP registers to 408 run DSP-enabled userspace applications 409 410config ARC_DSP_AGU_USERSPACE 411 bool "Support DSP with AGU for userspace apps" 412 select ARC_HAS_ACCL_REGS 413 select ARC_DSP_HANDLED 414 select ARC_DSP_SAVE_RESTORE_REGS 415 help 416 DSP and AGU extensions presence in HW, support save / restore DSP 417 and AGU registers to run DSP-enabled userspace applications 418endchoice 419 420config ARC_IRQ_NO_AUTOSAVE 421 bool "Disable hardware autosave regfile on interrupts" 422 default n 423 help 424 On HS cores, taken interrupt auto saves the regfile on stack. 425 This is programmable and can be optionally disabled in which case 426 software INTERRUPT_PROLOGUE/EPILGUE do the needed work 427 428config ARC_LPB_DISABLE 429 bool "Disable loop buffer (LPB)" 430 help 431 On HS cores, loop buffer (LPB) is programmable in runtime and can 432 be optionally disabled. 433 434endif # ISA_ARCV2 435 436endmenu # "ARC CPU Configuration" 437 438config LINUX_LINK_BASE 439 hex "Kernel link address" 440 default "0x80000000" 441 help 442 ARC700 divides the 32 bit phy address space into two equal halves 443 -Lower 2G (0 - 0x7FFF_FFFF ) is user virtual, translated by MMU 444 -Upper 2G (0x8000_0000 onwards) is untranslated, for kernel 445 Typically Linux kernel is linked at the start of untransalted addr, 446 hence the default value of 0x8zs. 447 However some customers have peripherals mapped at this addr, so 448 Linux needs to be scooted a bit. 449 If you don't know what the above means, leave this setting alone. 450 This needs to match memory start address specified in Device Tree 451 452config LINUX_RAM_BASE 453 hex "RAM base address" 454 default LINUX_LINK_BASE 455 help 456 By default Linux is linked at base of RAM. However in some special 457 cases (such as HSDK), Linux can't be linked at start of DDR, hence 458 this option. 459 460config HIGHMEM 461 bool "High Memory Support" 462 select HAVE_ARCH_PFN_VALID 463 select KMAP_LOCAL 464 help 465 With ARC 2G:2G address split, only upper 2G is directly addressable by 466 kernel. Enable this to potentially allow access to rest of 2G and PAE 467 in future 468 469config ARC_HAS_PAE40 470 bool "Support for the 40-bit Physical Address Extension" 471 depends on ISA_ARCV2 472 select HIGHMEM 473 select PHYS_ADDR_T_64BIT 474 help 475 Enable access to physical memory beyond 4G, only supported on 476 ARC cores with 40 bit Physical Addressing support 477 478config ARC_KVADDR_SIZE 479 int "Kernel Virtual Address Space size (MB)" 480 range 0 512 481 default "256" 482 help 483 The kernel address space is carved out of 256MB of translated address 484 space for catering to vmalloc, modules, pkmap, fixmap. This however may 485 not suffice vmalloc requirements of a 4K CPU EZChip system. So allow 486 this to be stretched to 512 MB (by extending into the reserved 487 kernel-user gutter) 488 489config ARC_CURR_IN_REG 490 bool "Dedicate Register r25 for current_task pointer" 491 default y 492 help 493 This reserved Register R25 to point to Current Task in 494 kernel mode. This saves memory access for each such access 495 496 497config ARC_EMUL_UNALIGNED 498 bool "Emulate unaligned memory access (userspace only)" 499 select SYSCTL_ARCH_UNALIGN_NO_WARN 500 select SYSCTL_ARCH_UNALIGN_ALLOW 501 depends on ISA_ARCOMPACT 502 help 503 This enables misaligned 16 & 32 bit memory access from user space. 504 Use ONLY-IF-ABS-NECESSARY as it will be very slow and also can hide 505 potential bugs in code 506 507config HZ 508 int "Timer Frequency" 509 default 100 510 511config ARC_METAWARE_HLINK 512 bool "Support for Metaware debugger assisted Host access" 513 help 514 This options allows a Linux userland apps to directly access 515 host file system (open/creat/read/write etc) with help from 516 Metaware Debugger. This can come in handy for Linux-host communication 517 when there is no real usable peripheral such as EMAC. 518 519menuconfig ARC_DBG 520 bool "ARC debugging" 521 default y 522 523if ARC_DBG 524 525config ARC_DW2_UNWIND 526 bool "Enable DWARF specific kernel stack unwind" 527 default y 528 select KALLSYMS 529 help 530 Compiles the kernel with DWARF unwind information and can be used 531 to get stack backtraces. 532 533 If you say Y here the resulting kernel image will be slightly larger 534 but not slower, and it will give very useful debugging information. 535 If you don't debug the kernel, you can say N, but we may not be able 536 to solve problems without frame unwind information 537 538config ARC_DBG_JUMP_LABEL 539 bool "Paranoid checks in Static Keys (jump labels) code" 540 depends on JUMP_LABEL 541 default y if STATIC_KEYS_SELFTEST 542 help 543 Enable paranoid checks and self-test of both ARC-specific and generic 544 part of static keys (jump labels) related code. 545endif 546 547config ARC_BUILTIN_DTB_NAME 548 string "Built in DTB" 549 help 550 Set the name of the DTB to embed in the vmlinux binary 551 Leaving it blank selects the minimal "skeleton" dtb 552 553endmenu # "ARC Architecture Configuration" 554 555config FORCE_MAX_ZONEORDER 556 int "Maximum zone order" 557 default "12" if ARC_HUGEPAGE_16M 558 default "11" 559 560source "kernel/power/Kconfig" 561