1# SPDX-License-Identifier: GPL-2.0-only 2# 3# Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com) 4# 5 6config ARC 7 def_bool y 8 select ARC_TIMERS 9 select ARCH_HAS_CACHE_LINE_SIZE 10 select ARCH_HAS_DEBUG_VM_PGTABLE 11 select ARCH_HAS_DMA_PREP_COHERENT 12 select ARCH_HAS_PTE_SPECIAL 13 select ARCH_HAS_SETUP_DMA_OPS 14 select ARCH_HAS_SYNC_DMA_FOR_CPU 15 select ARCH_HAS_SYNC_DMA_FOR_DEVICE 16 select ARCH_SUPPORTS_ATOMIC_RMW if ARC_HAS_LLSC 17 select ARCH_32BIT_OFF_T 18 select BUILDTIME_TABLE_SORT 19 select CLONE_BACKWARDS 20 select COMMON_CLK 21 select DMA_DIRECT_REMAP 22 select GENERIC_ATOMIC64 if !ISA_ARCV2 || !(ARC_HAS_LL64 && ARC_HAS_LLSC) 23 # for now, we don't need GENERIC_IRQ_PROBE, CONFIG_GENERIC_IRQ_CHIP 24 select GENERIC_IRQ_SHOW 25 select GENERIC_PCI_IOMAP 26 select GENERIC_PENDING_IRQ if SMP 27 select GENERIC_SCHED_CLOCK 28 select GENERIC_SMP_IDLE_THREAD 29 select GENERIC_IOREMAP 30 select GENERIC_STRNCPY_FROM_USER if MMU 31 select GENERIC_STRNLEN_USER if MMU 32 select HAVE_ARCH_KGDB 33 select HAVE_ARCH_TRACEHOOK 34 select HAVE_ARCH_TRANSPARENT_HUGEPAGE if ARC_MMU_V4 35 select HAVE_DEBUG_STACKOVERFLOW 36 select HAVE_DEBUG_KMEMLEAK 37 select HAVE_IOREMAP_PROT 38 select HAVE_KERNEL_GZIP 39 select HAVE_KERNEL_LZMA 40 select HAVE_KPROBES 41 select HAVE_KRETPROBES 42 select HAVE_REGS_AND_STACK_ACCESS_API 43 select HAVE_MOD_ARCH_SPECIFIC 44 select HAVE_PERF_EVENTS 45 select HAVE_SYSCALL_TRACEPOINTS 46 select IRQ_DOMAIN 47 select LOCK_MM_AND_FIND_VMA 48 select MODULES_USE_ELF_RELA 49 select OF 50 select OF_EARLY_FLATTREE 51 select PCI_SYSCALL if PCI 52 select HAVE_ARCH_JUMP_LABEL if ISA_ARCV2 && !CPU_ENDIAN_BE32 53 select TRACE_IRQFLAGS_SUPPORT 54 select HAVE_EBPF_JIT if ISA_ARCV2 55 56config LOCKDEP_SUPPORT 57 def_bool y 58 59config SCHED_OMIT_FRAME_POINTER 60 def_bool y 61 62config GENERIC_CSUM 63 def_bool y 64 65config ARCH_FLATMEM_ENABLE 66 def_bool y 67 68config MMU 69 def_bool y 70 71config NO_IOPORT_MAP 72 def_bool y 73 74config GENERIC_CALIBRATE_DELAY 75 def_bool y 76 77config GENERIC_HWEIGHT 78 def_bool y 79 80config STACKTRACE_SUPPORT 81 def_bool y 82 select STACKTRACE 83 84menu "ARC Architecture Configuration" 85 86menu "ARC Platform/SoC/Board" 87 88source "arch/arc/plat-tb10x/Kconfig" 89source "arch/arc/plat-axs10x/Kconfig" 90source "arch/arc/plat-hsdk/Kconfig" 91 92endmenu 93 94choice 95 prompt "ARC Instruction Set" 96 default ISA_ARCV2 97 98config ISA_ARCOMPACT 99 bool "ARCompact ISA" 100 select CPU_NO_EFFICIENT_FFS 101 help 102 The original ARC ISA of ARC600/700 cores 103 104config ISA_ARCV2 105 bool "ARC ISA v2" 106 select ARC_TIMERS_64BIT 107 help 108 ISA for the Next Generation ARC-HS cores 109 110endchoice 111 112menu "ARC CPU Configuration" 113 114choice 115 prompt "ARC Core" 116 default ARC_CPU_770 if ISA_ARCOMPACT 117 default ARC_CPU_HS if ISA_ARCV2 118 119config ARC_CPU_770 120 bool "ARC770" 121 depends on ISA_ARCOMPACT 122 select ARC_HAS_SWAPE 123 help 124 Support for ARC770 core introduced with Rel 4.10 (Summer 2011) 125 This core has a bunch of cool new features: 126 -MMU-v3: Variable Page Sz (4k, 8k, 16k), bigger J-TLB (128x4) 127 Shared Address Spaces (for sharing TLB entries in MMU) 128 -Caches: New Prog Model, Region Flush 129 -Insns: endian swap, load-locked/store-conditional, time-stamp-ctr 130 131config ARC_CPU_HS 132 bool "ARC-HS" 133 depends on ISA_ARCV2 134 help 135 Support for ARC HS38x Cores based on ARCv2 ISA 136 The notable features are: 137 - SMP configurations of up to 4 cores with coherency 138 - Optional L2 Cache and IO-Coherency 139 - Revised Interrupt Architecture (multiple priorites, reg banks, 140 auto stack switch, auto regfile save/restore) 141 - MMUv4 (PIPT dcache, Huge Pages) 142 - Instructions for 143 * 64bit load/store: LDD, STD 144 * Hardware assisted divide/remainder: DIV, REM 145 * Function prologue/epilogue: ENTER_S, LEAVE_S 146 * IRQ enable/disable: CLRI, SETI 147 * pop count: FFS, FLS 148 * SETcc, BMSKN, XBFU... 149 150endchoice 151 152config ARC_TUNE_MCPU 153 string "Override default -mcpu compiler flag" 154 default "" 155 help 156 Override default -mcpu=xxx compiler flag (which is set depending on 157 the ISA version) with the specified value. 158 NOTE: If specified flag isn't supported by current compiler the 159 ISA default value will be used as a fallback. 160 161config CPU_BIG_ENDIAN 162 bool "Enable Big Endian Mode" 163 help 164 Build kernel for Big Endian Mode of ARC CPU 165 166config SMP 167 bool "Symmetric Multi-Processing" 168 select ARC_MCIP if ISA_ARCV2 169 help 170 This enables support for systems with more than one CPU. 171 172if SMP 173 174config NR_CPUS 175 int "Maximum number of CPUs (2-4096)" 176 range 2 4096 177 default "4" 178 179config ARC_SMP_HALT_ON_RESET 180 bool "Enable Halt-on-reset boot mode" 181 help 182 In SMP configuration cores can be configured as Halt-on-reset 183 or they could all start at same time. For Halt-on-reset, non 184 masters are parked until Master kicks them so they can start off 185 at designated entry point. For other case, all jump to common 186 entry point and spin wait for Master's signal. 187 188endif #SMP 189 190config ARC_MCIP 191 bool "ARConnect Multicore IP (MCIP) Support " 192 depends on ISA_ARCV2 193 default y if SMP 194 help 195 This IP block enables SMP in ARC-HS38 cores. 196 It provides for cross-core interrupts, multi-core debug 197 hardware semaphores, shared memory,.... 198 199menuconfig ARC_CACHE 200 bool "Enable Cache Support" 201 default y 202 203if ARC_CACHE 204 205config ARC_CACHE_LINE_SHIFT 206 int "Cache Line Length (as power of 2)" 207 range 5 7 208 default "6" 209 help 210 Starting with ARC700 4.9, Cache line length is configurable, 211 This option specifies "N", with Line-len = 2 power N 212 So line lengths of 32, 64, 128 are specified by 5,6,7, respectively 213 Linux only supports same line lengths for I and D caches. 214 215config ARC_HAS_ICACHE 216 bool "Use Instruction Cache" 217 default y 218 219config ARC_HAS_DCACHE 220 bool "Use Data Cache" 221 default y 222 223config ARC_CACHE_PAGES 224 bool "Per Page Cache Control" 225 default y 226 depends on ARC_HAS_ICACHE || ARC_HAS_DCACHE 227 help 228 This can be used to over-ride the global I/D Cache Enable on a 229 per-page basis (but only for pages accessed via MMU such as 230 Kernel Virtual address or User Virtual Address) 231 TLB entries have a per-page Cache Enable Bit. 232 Note that Global I/D ENABLE + Per Page DISABLE works but corollary 233 Global DISABLE + Per Page ENABLE won't work 234 235endif #ARC_CACHE 236 237config ARC_HAS_ICCM 238 bool "Use ICCM" 239 help 240 Single Cycle RAMS to store Fast Path Code 241 242config ARC_ICCM_SZ 243 int "ICCM Size in KB" 244 default "64" 245 depends on ARC_HAS_ICCM 246 247config ARC_HAS_DCCM 248 bool "Use DCCM" 249 help 250 Single Cycle RAMS to store Fast Path Data 251 252config ARC_DCCM_SZ 253 int "DCCM Size in KB" 254 default "64" 255 depends on ARC_HAS_DCCM 256 257config ARC_DCCM_BASE 258 hex "DCCM map address" 259 default "0xA0000000" 260 depends on ARC_HAS_DCCM 261 262choice 263 prompt "MMU Version" 264 default ARC_MMU_V3 if ISA_ARCOMPACT 265 default ARC_MMU_V4 if ISA_ARCV2 266 267config ARC_MMU_V3 268 bool "MMU v3" 269 depends on ISA_ARCOMPACT 270 help 271 Introduced with ARC700 4.10: New Features 272 Variable Page size (1k-16k), var JTLB size 128 x (2 or 4) 273 Shared Address Spaces (SASID) 274 275config ARC_MMU_V4 276 bool "MMU v4" 277 depends on ISA_ARCV2 278 279endchoice 280 281 282choice 283 prompt "MMU Page Size" 284 default ARC_PAGE_SIZE_8K 285 286config ARC_PAGE_SIZE_8K 287 bool "8KB" 288 select HAVE_PAGE_SIZE_8KB 289 help 290 Choose between 8k vs 16k 291 292config ARC_PAGE_SIZE_16K 293 select HAVE_PAGE_SIZE_16KB 294 bool "16KB" 295 296config ARC_PAGE_SIZE_4K 297 bool "4KB" 298 select HAVE_PAGE_SIZE_4KB 299 depends on ARC_MMU_V3 || ARC_MMU_V4 300 301endchoice 302 303choice 304 prompt "MMU Super Page Size" 305 depends on ISA_ARCV2 && TRANSPARENT_HUGEPAGE 306 default ARC_HUGEPAGE_2M 307 308config ARC_HUGEPAGE_2M 309 bool "2MB" 310 311config ARC_HUGEPAGE_16M 312 bool "16MB" 313 314endchoice 315 316config PGTABLE_LEVELS 317 int "Number of Page table levels" 318 default 2 319 320config ARC_COMPACT_IRQ_LEVELS 321 depends on ISA_ARCOMPACT 322 bool "Setup Timer IRQ as high Priority" 323 # if SMP, LV2 enabled ONLY if ARC implementation has LV2 re-entrancy 324 depends on !SMP 325 326config ARC_FPU_SAVE_RESTORE 327 bool "Enable FPU state persistence across context switch" 328 help 329 ARCompact FPU has internal registers to assist with Double precision 330 Floating Point operations. There are control and stauts registers 331 for floating point exceptions and rounding modes. These are 332 preserved across task context switch when enabled. 333 334config ARC_CANT_LLSC 335 def_bool n 336 337config ARC_HAS_LLSC 338 bool "Insn: LLOCK/SCOND (efficient atomic ops)" 339 default y 340 depends on !ARC_CANT_LLSC 341 342config ARC_HAS_SWAPE 343 bool "Insn: SWAPE (endian-swap)" 344 default y 345 346if ISA_ARCV2 347 348config ARC_USE_UNALIGNED_MEM_ACCESS 349 bool "Enable unaligned access in HW" 350 default y 351 select HAVE_EFFICIENT_UNALIGNED_ACCESS 352 help 353 The ARC HS architecture supports unaligned memory access 354 which is disabled by default. Enable unaligned access in 355 hardware and use software to use it 356 357config ARC_HAS_LL64 358 bool "Insn: 64bit LDD/STD" 359 help 360 Enable gcc to generate 64-bit load/store instructions 361 ISA mandates even/odd registers to allow encoding of two 362 dest operands with 2 possible source operands. 363 default y 364 365config ARC_HAS_DIV_REM 366 bool "Insn: div, divu, rem, remu" 367 default y 368 369config ARC_HAS_ACCL_REGS 370 bool "Reg Pair ACCL:ACCH (FPU and/or MPY > 6 and/or DSP)" 371 default y 372 help 373 Depending on the configuration, CPU can contain accumulator reg-pair 374 (also referred to as r58:r59). These can also be used by gcc as GPR so 375 kernel needs to save/restore per process 376 377config ARC_DSP_HANDLED 378 def_bool n 379 380config ARC_DSP_SAVE_RESTORE_REGS 381 def_bool n 382 383choice 384 prompt "DSP support" 385 default ARC_DSP_NONE 386 help 387 Depending on the configuration, CPU can contain DSP registers 388 (ACC0_GLO, ACC0_GHI, DSP_BFLY0, DSP_CTRL, DSP_FFT_CTRL). 389 Below are options describing how to handle these registers in 390 interrupt entry / exit and in context switch. 391 392config ARC_DSP_NONE 393 bool "No DSP extension presence in HW" 394 help 395 No DSP extension presence in HW 396 397config ARC_DSP_KERNEL 398 bool "DSP extension in HW, no support for userspace" 399 select ARC_HAS_ACCL_REGS 400 select ARC_DSP_HANDLED 401 help 402 DSP extension presence in HW, no support for DSP-enabled userspace 403 applications. We don't save / restore DSP registers and only do 404 some minimal preparations so userspace won't be able to break kernel 405 406config ARC_DSP_USERSPACE 407 bool "Support DSP for userspace apps" 408 select ARC_HAS_ACCL_REGS 409 select ARC_DSP_HANDLED 410 select ARC_DSP_SAVE_RESTORE_REGS 411 help 412 DSP extension presence in HW, support save / restore DSP registers to 413 run DSP-enabled userspace applications 414 415config ARC_DSP_AGU_USERSPACE 416 bool "Support DSP with AGU for userspace apps" 417 select ARC_HAS_ACCL_REGS 418 select ARC_DSP_HANDLED 419 select ARC_DSP_SAVE_RESTORE_REGS 420 help 421 DSP and AGU extensions presence in HW, support save / restore DSP 422 and AGU registers to run DSP-enabled userspace applications 423endchoice 424 425config ARC_IRQ_NO_AUTOSAVE 426 bool "Disable hardware autosave regfile on interrupts" 427 default n 428 help 429 On HS cores, taken interrupt auto saves the regfile on stack. 430 This is programmable and can be optionally disabled in which case 431 software INTERRUPT_PROLOGUE/EPILGUE do the needed work 432 433config ARC_LPB_DISABLE 434 bool "Disable loop buffer (LPB)" 435 help 436 On HS cores, loop buffer (LPB) is programmable in runtime and can 437 be optionally disabled. 438 439endif # ISA_ARCV2 440 441endmenu # "ARC CPU Configuration" 442 443config LINUX_LINK_BASE 444 hex "Kernel link address" 445 default "0x80000000" 446 help 447 ARC700 divides the 32 bit phy address space into two equal halves 448 -Lower 2G (0 - 0x7FFF_FFFF ) is user virtual, translated by MMU 449 -Upper 2G (0x8000_0000 onwards) is untranslated, for kernel 450 Typically Linux kernel is linked at the start of untransalted addr, 451 hence the default value of 0x8zs. 452 However some customers have peripherals mapped at this addr, so 453 Linux needs to be scooted a bit. 454 If you don't know what the above means, leave this setting alone. 455 This needs to match memory start address specified in Device Tree 456 457config LINUX_RAM_BASE 458 hex "RAM base address" 459 default LINUX_LINK_BASE 460 help 461 By default Linux is linked at base of RAM. However in some special 462 cases (such as HSDK), Linux can't be linked at start of DDR, hence 463 this option. 464 465config HIGHMEM 466 bool "High Memory Support" 467 select HAVE_ARCH_PFN_VALID 468 select KMAP_LOCAL 469 help 470 With ARC 2G:2G address split, only upper 2G is directly addressable by 471 kernel. Enable this to potentially allow access to rest of 2G and PAE 472 in future 473 474config ARC_HAS_PAE40 475 bool "Support for the 40-bit Physical Address Extension" 476 depends on ISA_ARCV2 477 select HIGHMEM 478 select PHYS_ADDR_T_64BIT 479 help 480 Enable access to physical memory beyond 4G, only supported on 481 ARC cores with 40 bit Physical Addressing support 482 483config ARC_KVADDR_SIZE 484 int "Kernel Virtual Address Space size (MB)" 485 range 0 512 486 default "256" 487 help 488 The kernel address space is carved out of 256MB of translated address 489 space for catering to vmalloc, modules, pkmap, fixmap. This however may 490 not suffice vmalloc requirements of a 4K CPU EZChip system. So allow 491 this to be stretched to 512 MB (by extending into the reserved 492 kernel-user gutter) 493 494config ARC_CURR_IN_REG 495 bool "cache current task pointer in gp" 496 default y 497 help 498 This reserves gp register to point to Current Task in 499 kernel mode eliding memory access for each access 500 501 502config ARC_EMUL_UNALIGNED 503 bool "Emulate unaligned memory access (userspace only)" 504 select SYSCTL_ARCH_UNALIGN_NO_WARN 505 select SYSCTL_ARCH_UNALIGN_ALLOW 506 depends on ISA_ARCOMPACT 507 help 508 This enables misaligned 16 & 32 bit memory access from user space. 509 Use ONLY-IF-ABS-NECESSARY as it will be very slow and also can hide 510 potential bugs in code 511 512config HZ 513 int "Timer Frequency" 514 default 100 515 516config ARC_METAWARE_HLINK 517 bool "Support for Metaware debugger assisted Host access" 518 help 519 This options allows a Linux userland apps to directly access 520 host file system (open/creat/read/write etc) with help from 521 Metaware Debugger. This can come in handy for Linux-host communication 522 when there is no real usable peripheral such as EMAC. 523 524menuconfig ARC_DBG 525 bool "ARC debugging" 526 default y 527 528if ARC_DBG 529 530config ARC_DW2_UNWIND 531 bool "Enable DWARF specific kernel stack unwind" 532 default y 533 select KALLSYMS 534 help 535 Compiles the kernel with DWARF unwind information and can be used 536 to get stack backtraces. 537 538 If you say Y here the resulting kernel image will be slightly larger 539 but not slower, and it will give very useful debugging information. 540 If you don't debug the kernel, you can say N, but we may not be able 541 to solve problems without frame unwind information 542 543config ARC_DBG_JUMP_LABEL 544 bool "Paranoid checks in Static Keys (jump labels) code" 545 depends on JUMP_LABEL 546 default y if STATIC_KEYS_SELFTEST 547 help 548 Enable paranoid checks and self-test of both ARC-specific and generic 549 part of static keys (jump labels) related code. 550endif 551 552config ARC_BUILTIN_DTB_NAME 553 string "Built in DTB" 554 help 555 Set the name of the DTB to embed in the vmlinux binary 556 Leaving it blank selects the minimal "skeleton" dtb 557 558endmenu # "ARC Architecture Configuration" 559 560config ARCH_FORCE_MAX_ORDER 561 int "Maximum zone order" 562 default "11" if ARC_HUGEPAGE_16M 563 default "10" 564 565source "kernel/power/Kconfig" 566