1# SPDX-License-Identifier: GPL-2.0-only 2# 3# Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com) 4# 5 6config ARC 7 def_bool y 8 select ARC_TIMERS 9 select ARCH_HAS_DEBUG_VM_PGTABLE 10 select ARCH_HAS_DMA_PREP_COHERENT 11 select ARCH_HAS_PTE_SPECIAL 12 select ARCH_HAS_SETUP_DMA_OPS 13 select ARCH_HAS_SYNC_DMA_FOR_CPU 14 select ARCH_HAS_SYNC_DMA_FOR_DEVICE 15 select ARCH_SUPPORTS_ATOMIC_RMW if ARC_HAS_LLSC 16 select ARCH_32BIT_OFF_T 17 select BUILDTIME_TABLE_SORT 18 select CLONE_BACKWARDS 19 select COMMON_CLK 20 select DMA_DIRECT_REMAP 21 select GENERIC_ATOMIC64 if !ISA_ARCV2 || !(ARC_HAS_LL64 && ARC_HAS_LLSC) 22 select GENERIC_FIND_FIRST_BIT 23 # for now, we don't need GENERIC_IRQ_PROBE, CONFIG_GENERIC_IRQ_CHIP 24 select GENERIC_IRQ_SHOW 25 select GENERIC_PCI_IOMAP 26 select GENERIC_PENDING_IRQ if SMP 27 select GENERIC_SCHED_CLOCK 28 select GENERIC_SMP_IDLE_THREAD 29 select HAVE_ARCH_KGDB 30 select HAVE_ARCH_TRACEHOOK 31 select HAVE_DEBUG_STACKOVERFLOW 32 select HAVE_DEBUG_KMEMLEAK 33 select HAVE_FUTEX_CMPXCHG if FUTEX 34 select HAVE_IOREMAP_PROT 35 select HAVE_KERNEL_GZIP 36 select HAVE_KERNEL_LZMA 37 select HAVE_KPROBES 38 select HAVE_KRETPROBES 39 select HAVE_MOD_ARCH_SPECIFIC 40 select HAVE_OPROFILE 41 select HAVE_PERF_EVENTS 42 select HANDLE_DOMAIN_IRQ 43 select IRQ_DOMAIN 44 select MODULES_USE_ELF_RELA 45 select OF 46 select OF_EARLY_FLATTREE 47 select PCI_SYSCALL if PCI 48 select PERF_USE_VMALLOC if ARC_CACHE_VIPT_ALIASING 49 select HAVE_ARCH_JUMP_LABEL if ISA_ARCV2 && !CPU_ENDIAN_BE32 50 select SET_FS 51 52config ARCH_HAS_CACHE_LINE_SIZE 53 def_bool y 54 55config TRACE_IRQFLAGS_SUPPORT 56 def_bool y 57 58config LOCKDEP_SUPPORT 59 def_bool y 60 61config SCHED_OMIT_FRAME_POINTER 62 def_bool y 63 64config GENERIC_CSUM 65 def_bool y 66 67config ARCH_DISCONTIGMEM_ENABLE 68 def_bool n 69 depends on BROKEN 70 71config ARCH_FLATMEM_ENABLE 72 def_bool y 73 74config MMU 75 def_bool y 76 77config NO_IOPORT_MAP 78 def_bool y 79 80config GENERIC_CALIBRATE_DELAY 81 def_bool y 82 83config GENERIC_HWEIGHT 84 def_bool y 85 86config STACKTRACE_SUPPORT 87 def_bool y 88 select STACKTRACE 89 90config HAVE_ARCH_TRANSPARENT_HUGEPAGE 91 def_bool y 92 depends on ARC_MMU_V4 93 94menu "ARC Architecture Configuration" 95 96menu "ARC Platform/SoC/Board" 97 98source "arch/arc/plat-tb10x/Kconfig" 99source "arch/arc/plat-axs10x/Kconfig" 100source "arch/arc/plat-hsdk/Kconfig" 101 102endmenu 103 104choice 105 prompt "ARC Instruction Set" 106 default ISA_ARCV2 107 108config ISA_ARCOMPACT 109 bool "ARCompact ISA" 110 select CPU_NO_EFFICIENT_FFS 111 help 112 The original ARC ISA of ARC600/700 cores 113 114config ISA_ARCV2 115 bool "ARC ISA v2" 116 select ARC_TIMERS_64BIT 117 help 118 ISA for the Next Generation ARC-HS cores 119 120endchoice 121 122menu "ARC CPU Configuration" 123 124choice 125 prompt "ARC Core" 126 default ARC_CPU_770 if ISA_ARCOMPACT 127 default ARC_CPU_HS if ISA_ARCV2 128 129if ISA_ARCOMPACT 130 131config ARC_CPU_750D 132 bool "ARC750D" 133 select ARC_CANT_LLSC 134 help 135 Support for ARC750 core 136 137config ARC_CPU_770 138 bool "ARC770" 139 select ARC_HAS_SWAPE 140 help 141 Support for ARC770 core introduced with Rel 4.10 (Summer 2011) 142 This core has a bunch of cool new features: 143 -MMU-v3: Variable Page Sz (4k, 8k, 16k), bigger J-TLB (128x4) 144 Shared Address Spaces (for sharing TLB entries in MMU) 145 -Caches: New Prog Model, Region Flush 146 -Insns: endian swap, load-locked/store-conditional, time-stamp-ctr 147 148endif #ISA_ARCOMPACT 149 150config ARC_CPU_HS 151 bool "ARC-HS" 152 depends on ISA_ARCV2 153 help 154 Support for ARC HS38x Cores based on ARCv2 ISA 155 The notable features are: 156 - SMP configurations of up to 4 cores with coherency 157 - Optional L2 Cache and IO-Coherency 158 - Revised Interrupt Architecture (multiple priorites, reg banks, 159 auto stack switch, auto regfile save/restore) 160 - MMUv4 (PIPT dcache, Huge Pages) 161 - Instructions for 162 * 64bit load/store: LDD, STD 163 * Hardware assisted divide/remainder: DIV, REM 164 * Function prologue/epilogue: ENTER_S, LEAVE_S 165 * IRQ enable/disable: CLRI, SETI 166 * pop count: FFS, FLS 167 * SETcc, BMSKN, XBFU... 168 169endchoice 170 171config ARC_TUNE_MCPU 172 string "Override default -mcpu compiler flag" 173 default "" 174 help 175 Override default -mcpu=xxx compiler flag (which is set depending on 176 the ISA version) with the specified value. 177 NOTE: If specified flag isn't supported by current compiler the 178 ISA default value will be used as a fallback. 179 180config CPU_BIG_ENDIAN 181 bool "Enable Big Endian Mode" 182 help 183 Build kernel for Big Endian Mode of ARC CPU 184 185config SMP 186 bool "Symmetric Multi-Processing" 187 select ARC_MCIP if ISA_ARCV2 188 help 189 This enables support for systems with more than one CPU. 190 191if SMP 192 193config NR_CPUS 194 int "Maximum number of CPUs (2-4096)" 195 range 2 4096 196 default "4" 197 198config ARC_SMP_HALT_ON_RESET 199 bool "Enable Halt-on-reset boot mode" 200 help 201 In SMP configuration cores can be configured as Halt-on-reset 202 or they could all start at same time. For Halt-on-reset, non 203 masters are parked until Master kicks them so they can start off 204 at designated entry point. For other case, all jump to common 205 entry point and spin wait for Master's signal. 206 207endif #SMP 208 209config ARC_MCIP 210 bool "ARConnect Multicore IP (MCIP) Support " 211 depends on ISA_ARCV2 212 default y if SMP 213 help 214 This IP block enables SMP in ARC-HS38 cores. 215 It provides for cross-core interrupts, multi-core debug 216 hardware semaphores, shared memory,.... 217 218menuconfig ARC_CACHE 219 bool "Enable Cache Support" 220 default y 221 222if ARC_CACHE 223 224config ARC_CACHE_LINE_SHIFT 225 int "Cache Line Length (as power of 2)" 226 range 5 7 227 default "6" 228 help 229 Starting with ARC700 4.9, Cache line length is configurable, 230 This option specifies "N", with Line-len = 2 power N 231 So line lengths of 32, 64, 128 are specified by 5,6,7, respectively 232 Linux only supports same line lengths for I and D caches. 233 234config ARC_HAS_ICACHE 235 bool "Use Instruction Cache" 236 default y 237 238config ARC_HAS_DCACHE 239 bool "Use Data Cache" 240 default y 241 242config ARC_CACHE_PAGES 243 bool "Per Page Cache Control" 244 default y 245 depends on ARC_HAS_ICACHE || ARC_HAS_DCACHE 246 help 247 This can be used to over-ride the global I/D Cache Enable on a 248 per-page basis (but only for pages accessed via MMU such as 249 Kernel Virtual address or User Virtual Address) 250 TLB entries have a per-page Cache Enable Bit. 251 Note that Global I/D ENABLE + Per Page DISABLE works but corollary 252 Global DISABLE + Per Page ENABLE won't work 253 254config ARC_CACHE_VIPT_ALIASING 255 bool "Support VIPT Aliasing D$" 256 depends on ARC_HAS_DCACHE && ISA_ARCOMPACT 257 258endif #ARC_CACHE 259 260config ARC_HAS_ICCM 261 bool "Use ICCM" 262 help 263 Single Cycle RAMS to store Fast Path Code 264 265config ARC_ICCM_SZ 266 int "ICCM Size in KB" 267 default "64" 268 depends on ARC_HAS_ICCM 269 270config ARC_HAS_DCCM 271 bool "Use DCCM" 272 help 273 Single Cycle RAMS to store Fast Path Data 274 275config ARC_DCCM_SZ 276 int "DCCM Size in KB" 277 default "64" 278 depends on ARC_HAS_DCCM 279 280config ARC_DCCM_BASE 281 hex "DCCM map address" 282 default "0xA0000000" 283 depends on ARC_HAS_DCCM 284 285choice 286 prompt "MMU Version" 287 default ARC_MMU_V3 if ARC_CPU_770 288 default ARC_MMU_V2 if ARC_CPU_750D 289 default ARC_MMU_V4 if ARC_CPU_HS 290 291if ISA_ARCOMPACT 292 293config ARC_MMU_V1 294 bool "MMU v1" 295 help 296 Orig ARC700 MMU 297 298config ARC_MMU_V2 299 bool "MMU v2" 300 help 301 Fixed the deficiency of v1 - possible thrashing in memcpy scenario 302 when 2 D-TLB and 1 I-TLB entries index into same 2way set. 303 304config ARC_MMU_V3 305 bool "MMU v3" 306 depends on ARC_CPU_770 307 help 308 Introduced with ARC700 4.10: New Features 309 Variable Page size (1k-16k), var JTLB size 128 x (2 or 4) 310 Shared Address Spaces (SASID) 311 312endif 313 314config ARC_MMU_V4 315 bool "MMU v4" 316 depends on ISA_ARCV2 317 318endchoice 319 320 321choice 322 prompt "MMU Page Size" 323 default ARC_PAGE_SIZE_8K 324 325config ARC_PAGE_SIZE_8K 326 bool "8KB" 327 help 328 Choose between 8k vs 16k 329 330config ARC_PAGE_SIZE_16K 331 bool "16KB" 332 depends on ARC_MMU_V3 || ARC_MMU_V4 333 334config ARC_PAGE_SIZE_4K 335 bool "4KB" 336 depends on ARC_MMU_V3 || ARC_MMU_V4 337 338endchoice 339 340choice 341 prompt "MMU Super Page Size" 342 depends on ISA_ARCV2 && TRANSPARENT_HUGEPAGE 343 default ARC_HUGEPAGE_2M 344 345config ARC_HUGEPAGE_2M 346 bool "2MB" 347 348config ARC_HUGEPAGE_16M 349 bool "16MB" 350 351endchoice 352 353config NODES_SHIFT 354 int "Maximum NUMA Nodes (as a power of 2)" 355 default "0" if !DISCONTIGMEM 356 default "1" if DISCONTIGMEM 357 depends on NEED_MULTIPLE_NODES 358 help 359 Accessing memory beyond 1GB (with or w/o PAE) requires 2 memory 360 zones. 361 362config ARC_COMPACT_IRQ_LEVELS 363 depends on ISA_ARCOMPACT 364 bool "Setup Timer IRQ as high Priority" 365 # if SMP, LV2 enabled ONLY if ARC implementation has LV2 re-entrancy 366 depends on !SMP 367 368config ARC_FPU_SAVE_RESTORE 369 bool "Enable FPU state persistence across context switch" 370 help 371 ARCompact FPU has internal registers to assist with Double precision 372 Floating Point operations. There are control and stauts registers 373 for floating point exceptions and rounding modes. These are 374 preserved across task context switch when enabled. 375 376config ARC_CANT_LLSC 377 def_bool n 378 379config ARC_HAS_LLSC 380 bool "Insn: LLOCK/SCOND (efficient atomic ops)" 381 default y 382 depends on !ARC_CANT_LLSC 383 384config ARC_HAS_SWAPE 385 bool "Insn: SWAPE (endian-swap)" 386 default y 387 388if ISA_ARCV2 389 390config ARC_USE_UNALIGNED_MEM_ACCESS 391 bool "Enable unaligned access in HW" 392 default y 393 select HAVE_EFFICIENT_UNALIGNED_ACCESS 394 help 395 The ARC HS architecture supports unaligned memory access 396 which is disabled by default. Enable unaligned access in 397 hardware and use software to use it 398 399config ARC_HAS_LL64 400 bool "Insn: 64bit LDD/STD" 401 help 402 Enable gcc to generate 64-bit load/store instructions 403 ISA mandates even/odd registers to allow encoding of two 404 dest operands with 2 possible source operands. 405 default y 406 407config ARC_HAS_DIV_REM 408 bool "Insn: div, divu, rem, remu" 409 default y 410 411config ARC_HAS_ACCL_REGS 412 bool "Reg Pair ACCL:ACCH (FPU and/or MPY > 6 and/or DSP)" 413 default y 414 help 415 Depending on the configuration, CPU can contain accumulator reg-pair 416 (also referred to as r58:r59). These can also be used by gcc as GPR so 417 kernel needs to save/restore per process 418 419config ARC_DSP_HANDLED 420 def_bool n 421 422config ARC_DSP_SAVE_RESTORE_REGS 423 def_bool n 424 425choice 426 prompt "DSP support" 427 default ARC_DSP_NONE 428 help 429 Depending on the configuration, CPU can contain DSP registers 430 (ACC0_GLO, ACC0_GHI, DSP_BFLY0, DSP_CTRL, DSP_FFT_CTRL). 431 Bellow is options describing how to handle these registers in 432 interrupt entry / exit and in context switch. 433 434config ARC_DSP_NONE 435 bool "No DSP extension presence in HW" 436 help 437 No DSP extension presence in HW 438 439config ARC_DSP_KERNEL 440 bool "DSP extension in HW, no support for userspace" 441 select ARC_HAS_ACCL_REGS 442 select ARC_DSP_HANDLED 443 help 444 DSP extension presence in HW, no support for DSP-enabled userspace 445 applications. We don't save / restore DSP registers and only do 446 some minimal preparations so userspace won't be able to break kernel 447 448config ARC_DSP_USERSPACE 449 bool "Support DSP for userspace apps" 450 select ARC_HAS_ACCL_REGS 451 select ARC_DSP_HANDLED 452 select ARC_DSP_SAVE_RESTORE_REGS 453 help 454 DSP extension presence in HW, support save / restore DSP registers to 455 run DSP-enabled userspace applications 456 457config ARC_DSP_AGU_USERSPACE 458 bool "Support DSP with AGU for userspace apps" 459 select ARC_HAS_ACCL_REGS 460 select ARC_DSP_HANDLED 461 select ARC_DSP_SAVE_RESTORE_REGS 462 help 463 DSP and AGU extensions presence in HW, support save / restore DSP 464 and AGU registers to run DSP-enabled userspace applications 465endchoice 466 467config ARC_IRQ_NO_AUTOSAVE 468 bool "Disable hardware autosave regfile on interrupts" 469 default n 470 help 471 On HS cores, taken interrupt auto saves the regfile on stack. 472 This is programmable and can be optionally disabled in which case 473 software INTERRUPT_PROLOGUE/EPILGUE do the needed work 474 475config ARC_LPB_DISABLE 476 bool "Disable loop buffer (LPB)" 477 help 478 On HS cores, loop buffer (LPB) is programmable in runtime and can 479 be optionally disabled. 480 481endif # ISA_ARCV2 482 483endmenu # "ARC CPU Configuration" 484 485config LINUX_LINK_BASE 486 hex "Kernel link address" 487 default "0x80000000" 488 help 489 ARC700 divides the 32 bit phy address space into two equal halves 490 -Lower 2G (0 - 0x7FFF_FFFF ) is user virtual, translated by MMU 491 -Upper 2G (0x8000_0000 onwards) is untranslated, for kernel 492 Typically Linux kernel is linked at the start of untransalted addr, 493 hence the default value of 0x8zs. 494 However some customers have peripherals mapped at this addr, so 495 Linux needs to be scooted a bit. 496 If you don't know what the above means, leave this setting alone. 497 This needs to match memory start address specified in Device Tree 498 499config LINUX_RAM_BASE 500 hex "RAM base address" 501 default LINUX_LINK_BASE 502 help 503 By default Linux is linked at base of RAM. However in some special 504 cases (such as HSDK), Linux can't be linked at start of DDR, hence 505 this option. 506 507config HIGHMEM 508 bool "High Memory Support" 509 select HAVE_ARCH_PFN_VALID 510 select KMAP_LOCAL 511 help 512 With ARC 2G:2G address split, only upper 2G is directly addressable by 513 kernel. Enable this to potentially allow access to rest of 2G and PAE 514 in future 515 516config ARC_HAS_PAE40 517 bool "Support for the 40-bit Physical Address Extension" 518 depends on ISA_ARCV2 519 select HIGHMEM 520 select PHYS_ADDR_T_64BIT 521 help 522 Enable access to physical memory beyond 4G, only supported on 523 ARC cores with 40 bit Physical Addressing support 524 525config ARC_KVADDR_SIZE 526 int "Kernel Virtual Address Space size (MB)" 527 range 0 512 528 default "256" 529 help 530 The kernel address space is carved out of 256MB of translated address 531 space for catering to vmalloc, modules, pkmap, fixmap. This however may 532 not suffice vmalloc requirements of a 4K CPU EZChip system. So allow 533 this to be stretched to 512 MB (by extending into the reserved 534 kernel-user gutter) 535 536config ARC_CURR_IN_REG 537 bool "Dedicate Register r25 for current_task pointer" 538 default y 539 help 540 This reserved Register R25 to point to Current Task in 541 kernel mode. This saves memory access for each such access 542 543 544config ARC_EMUL_UNALIGNED 545 bool "Emulate unaligned memory access (userspace only)" 546 select SYSCTL_ARCH_UNALIGN_NO_WARN 547 select SYSCTL_ARCH_UNALIGN_ALLOW 548 depends on ISA_ARCOMPACT 549 help 550 This enables misaligned 16 & 32 bit memory access from user space. 551 Use ONLY-IF-ABS-NECESSARY as it will be very slow and also can hide 552 potential bugs in code 553 554config HZ 555 int "Timer Frequency" 556 default 100 557 558config ARC_METAWARE_HLINK 559 bool "Support for Metaware debugger assisted Host access" 560 help 561 This options allows a Linux userland apps to directly access 562 host file system (open/creat/read/write etc) with help from 563 Metaware Debugger. This can come in handy for Linux-host communication 564 when there is no real usable peripheral such as EMAC. 565 566menuconfig ARC_DBG 567 bool "ARC debugging" 568 default y 569 570if ARC_DBG 571 572config ARC_DW2_UNWIND 573 bool "Enable DWARF specific kernel stack unwind" 574 default y 575 select KALLSYMS 576 help 577 Compiles the kernel with DWARF unwind information and can be used 578 to get stack backtraces. 579 580 If you say Y here the resulting kernel image will be slightly larger 581 but not slower, and it will give very useful debugging information. 582 If you don't debug the kernel, you can say N, but we may not be able 583 to solve problems without frame unwind information 584 585config ARC_DBG_TLB_PARANOIA 586 bool "Paranoia Checks in Low Level TLB Handlers" 587 588config ARC_DBG_JUMP_LABEL 589 bool "Paranoid checks in Static Keys (jump labels) code" 590 depends on JUMP_LABEL 591 default y if STATIC_KEYS_SELFTEST 592 help 593 Enable paranoid checks and self-test of both ARC-specific and generic 594 part of static keys (jump labels) related code. 595endif 596 597config ARC_BUILTIN_DTB_NAME 598 string "Built in DTB" 599 help 600 Set the name of the DTB to embed in the vmlinux binary 601 Leaving it blank selects the minimal "skeleton" dtb 602 603endmenu # "ARC Architecture Configuration" 604 605config FORCE_MAX_ZONEORDER 606 int "Maximum zone order" 607 default "12" if ARC_HUGEPAGE_16M 608 default "11" 609 610source "kernel/power/Kconfig" 611