1# SPDX-License-Identifier: GPL-2.0-only 2# 3# Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com) 4# 5 6config ARC 7 def_bool y 8 select ARC_TIMERS 9 select ARCH_HAS_CACHE_LINE_SIZE 10 select ARCH_HAS_DEBUG_VM_PGTABLE 11 select ARCH_HAS_DMA_PREP_COHERENT 12 select ARCH_HAS_PTE_SPECIAL 13 select ARCH_HAS_SETUP_DMA_OPS 14 select ARCH_HAS_SYNC_DMA_FOR_CPU 15 select ARCH_HAS_SYNC_DMA_FOR_DEVICE 16 select ARCH_SUPPORTS_ATOMIC_RMW if ARC_HAS_LLSC 17 select ARCH_32BIT_OFF_T 18 select BUILDTIME_TABLE_SORT 19 select CLONE_BACKWARDS 20 select COMMON_CLK 21 select DMA_DIRECT_REMAP 22 select GENERIC_ATOMIC64 if !ISA_ARCV2 || !(ARC_HAS_LL64 && ARC_HAS_LLSC) 23 select GENERIC_FIND_FIRST_BIT 24 # for now, we don't need GENERIC_IRQ_PROBE, CONFIG_GENERIC_IRQ_CHIP 25 select GENERIC_IRQ_SHOW 26 select GENERIC_PCI_IOMAP 27 select GENERIC_PENDING_IRQ if SMP 28 select GENERIC_SCHED_CLOCK 29 select GENERIC_SMP_IDLE_THREAD 30 select GENERIC_STRNCPY_FROM_USER 31 select GENERIC_STRNLEN_USER 32 select HAVE_ARCH_KGDB 33 select HAVE_ARCH_TRACEHOOK 34 select HAVE_ARCH_TRANSPARENT_HUGEPAGE if ARC_MMU_V4 35 select HAVE_DEBUG_STACKOVERFLOW 36 select HAVE_DEBUG_KMEMLEAK 37 select HAVE_FUTEX_CMPXCHG if FUTEX 38 select HAVE_IOREMAP_PROT 39 select HAVE_KERNEL_GZIP 40 select HAVE_KERNEL_LZMA 41 select HAVE_KPROBES 42 select HAVE_KRETPROBES 43 select HAVE_MOD_ARCH_SPECIFIC 44 select HAVE_PERF_EVENTS 45 select HANDLE_DOMAIN_IRQ 46 select IRQ_DOMAIN 47 select MODULES_USE_ELF_RELA 48 select OF 49 select OF_EARLY_FLATTREE 50 select PCI_SYSCALL if PCI 51 select PERF_USE_VMALLOC if ARC_CACHE_VIPT_ALIASING 52 select HAVE_ARCH_JUMP_LABEL if ISA_ARCV2 && !CPU_ENDIAN_BE32 53 select SET_FS 54 55config TRACE_IRQFLAGS_SUPPORT 56 def_bool y 57 58config LOCKDEP_SUPPORT 59 def_bool y 60 61config SCHED_OMIT_FRAME_POINTER 62 def_bool y 63 64config GENERIC_CSUM 65 def_bool y 66 67config ARCH_FLATMEM_ENABLE 68 def_bool y 69 70config MMU 71 def_bool y 72 73config NO_IOPORT_MAP 74 def_bool y 75 76config GENERIC_CALIBRATE_DELAY 77 def_bool y 78 79config GENERIC_HWEIGHT 80 def_bool y 81 82config STACKTRACE_SUPPORT 83 def_bool y 84 select STACKTRACE 85 86menu "ARC Architecture Configuration" 87 88menu "ARC Platform/SoC/Board" 89 90source "arch/arc/plat-tb10x/Kconfig" 91source "arch/arc/plat-axs10x/Kconfig" 92source "arch/arc/plat-hsdk/Kconfig" 93 94endmenu 95 96choice 97 prompt "ARC Instruction Set" 98 default ISA_ARCV2 99 100config ISA_ARCOMPACT 101 bool "ARCompact ISA" 102 select CPU_NO_EFFICIENT_FFS 103 help 104 The original ARC ISA of ARC600/700 cores 105 106config ISA_ARCV2 107 bool "ARC ISA v2" 108 select ARC_TIMERS_64BIT 109 help 110 ISA for the Next Generation ARC-HS cores 111 112endchoice 113 114menu "ARC CPU Configuration" 115 116choice 117 prompt "ARC Core" 118 default ARC_CPU_770 if ISA_ARCOMPACT 119 default ARC_CPU_HS if ISA_ARCV2 120 121if ISA_ARCOMPACT 122 123config ARC_CPU_750D 124 bool "ARC750D" 125 select ARC_CANT_LLSC 126 help 127 Support for ARC750 core 128 129config ARC_CPU_770 130 bool "ARC770" 131 select ARC_HAS_SWAPE 132 help 133 Support for ARC770 core introduced with Rel 4.10 (Summer 2011) 134 This core has a bunch of cool new features: 135 -MMU-v3: Variable Page Sz (4k, 8k, 16k), bigger J-TLB (128x4) 136 Shared Address Spaces (for sharing TLB entries in MMU) 137 -Caches: New Prog Model, Region Flush 138 -Insns: endian swap, load-locked/store-conditional, time-stamp-ctr 139 140endif #ISA_ARCOMPACT 141 142config ARC_CPU_HS 143 bool "ARC-HS" 144 depends on ISA_ARCV2 145 help 146 Support for ARC HS38x Cores based on ARCv2 ISA 147 The notable features are: 148 - SMP configurations of up to 4 cores with coherency 149 - Optional L2 Cache and IO-Coherency 150 - Revised Interrupt Architecture (multiple priorites, reg banks, 151 auto stack switch, auto regfile save/restore) 152 - MMUv4 (PIPT dcache, Huge Pages) 153 - Instructions for 154 * 64bit load/store: LDD, STD 155 * Hardware assisted divide/remainder: DIV, REM 156 * Function prologue/epilogue: ENTER_S, LEAVE_S 157 * IRQ enable/disable: CLRI, SETI 158 * pop count: FFS, FLS 159 * SETcc, BMSKN, XBFU... 160 161endchoice 162 163config ARC_TUNE_MCPU 164 string "Override default -mcpu compiler flag" 165 default "" 166 help 167 Override default -mcpu=xxx compiler flag (which is set depending on 168 the ISA version) with the specified value. 169 NOTE: If specified flag isn't supported by current compiler the 170 ISA default value will be used as a fallback. 171 172config CPU_BIG_ENDIAN 173 bool "Enable Big Endian Mode" 174 help 175 Build kernel for Big Endian Mode of ARC CPU 176 177config SMP 178 bool "Symmetric Multi-Processing" 179 select ARC_MCIP if ISA_ARCV2 180 help 181 This enables support for systems with more than one CPU. 182 183if SMP 184 185config NR_CPUS 186 int "Maximum number of CPUs (2-4096)" 187 range 2 4096 188 default "4" 189 190config ARC_SMP_HALT_ON_RESET 191 bool "Enable Halt-on-reset boot mode" 192 help 193 In SMP configuration cores can be configured as Halt-on-reset 194 or they could all start at same time. For Halt-on-reset, non 195 masters are parked until Master kicks them so they can start off 196 at designated entry point. For other case, all jump to common 197 entry point and spin wait for Master's signal. 198 199endif #SMP 200 201config ARC_MCIP 202 bool "ARConnect Multicore IP (MCIP) Support " 203 depends on ISA_ARCV2 204 default y if SMP 205 help 206 This IP block enables SMP in ARC-HS38 cores. 207 It provides for cross-core interrupts, multi-core debug 208 hardware semaphores, shared memory,.... 209 210menuconfig ARC_CACHE 211 bool "Enable Cache Support" 212 default y 213 214if ARC_CACHE 215 216config ARC_CACHE_LINE_SHIFT 217 int "Cache Line Length (as power of 2)" 218 range 5 7 219 default "6" 220 help 221 Starting with ARC700 4.9, Cache line length is configurable, 222 This option specifies "N", with Line-len = 2 power N 223 So line lengths of 32, 64, 128 are specified by 5,6,7, respectively 224 Linux only supports same line lengths for I and D caches. 225 226config ARC_HAS_ICACHE 227 bool "Use Instruction Cache" 228 default y 229 230config ARC_HAS_DCACHE 231 bool "Use Data Cache" 232 default y 233 234config ARC_CACHE_PAGES 235 bool "Per Page Cache Control" 236 default y 237 depends on ARC_HAS_ICACHE || ARC_HAS_DCACHE 238 help 239 This can be used to over-ride the global I/D Cache Enable on a 240 per-page basis (but only for pages accessed via MMU such as 241 Kernel Virtual address or User Virtual Address) 242 TLB entries have a per-page Cache Enable Bit. 243 Note that Global I/D ENABLE + Per Page DISABLE works but corollary 244 Global DISABLE + Per Page ENABLE won't work 245 246config ARC_CACHE_VIPT_ALIASING 247 bool "Support VIPT Aliasing D$" 248 depends on ARC_HAS_DCACHE && ISA_ARCOMPACT 249 250endif #ARC_CACHE 251 252config ARC_HAS_ICCM 253 bool "Use ICCM" 254 help 255 Single Cycle RAMS to store Fast Path Code 256 257config ARC_ICCM_SZ 258 int "ICCM Size in KB" 259 default "64" 260 depends on ARC_HAS_ICCM 261 262config ARC_HAS_DCCM 263 bool "Use DCCM" 264 help 265 Single Cycle RAMS to store Fast Path Data 266 267config ARC_DCCM_SZ 268 int "DCCM Size in KB" 269 default "64" 270 depends on ARC_HAS_DCCM 271 272config ARC_DCCM_BASE 273 hex "DCCM map address" 274 default "0xA0000000" 275 depends on ARC_HAS_DCCM 276 277choice 278 prompt "MMU Version" 279 default ARC_MMU_V3 if ARC_CPU_770 280 default ARC_MMU_V2 if ARC_CPU_750D 281 default ARC_MMU_V4 if ARC_CPU_HS 282 283if ISA_ARCOMPACT 284 285config ARC_MMU_V1 286 bool "MMU v1" 287 help 288 Orig ARC700 MMU 289 290config ARC_MMU_V2 291 bool "MMU v2" 292 help 293 Fixed the deficiency of v1 - possible thrashing in memcpy scenario 294 when 2 D-TLB and 1 I-TLB entries index into same 2way set. 295 296config ARC_MMU_V3 297 bool "MMU v3" 298 depends on ARC_CPU_770 299 help 300 Introduced with ARC700 4.10: New Features 301 Variable Page size (1k-16k), var JTLB size 128 x (2 or 4) 302 Shared Address Spaces (SASID) 303 304endif 305 306config ARC_MMU_V4 307 bool "MMU v4" 308 depends on ISA_ARCV2 309 310endchoice 311 312 313choice 314 prompt "MMU Page Size" 315 default ARC_PAGE_SIZE_8K 316 317config ARC_PAGE_SIZE_8K 318 bool "8KB" 319 help 320 Choose between 8k vs 16k 321 322config ARC_PAGE_SIZE_16K 323 bool "16KB" 324 depends on ARC_MMU_V3 || ARC_MMU_V4 325 326config ARC_PAGE_SIZE_4K 327 bool "4KB" 328 depends on ARC_MMU_V3 || ARC_MMU_V4 329 330endchoice 331 332choice 333 prompt "MMU Super Page Size" 334 depends on ISA_ARCV2 && TRANSPARENT_HUGEPAGE 335 default ARC_HUGEPAGE_2M 336 337config ARC_HUGEPAGE_2M 338 bool "2MB" 339 340config ARC_HUGEPAGE_16M 341 bool "16MB" 342 343endchoice 344 345config ARC_COMPACT_IRQ_LEVELS 346 depends on ISA_ARCOMPACT 347 bool "Setup Timer IRQ as high Priority" 348 # if SMP, LV2 enabled ONLY if ARC implementation has LV2 re-entrancy 349 depends on !SMP 350 351config ARC_FPU_SAVE_RESTORE 352 bool "Enable FPU state persistence across context switch" 353 help 354 ARCompact FPU has internal registers to assist with Double precision 355 Floating Point operations. There are control and stauts registers 356 for floating point exceptions and rounding modes. These are 357 preserved across task context switch when enabled. 358 359config ARC_CANT_LLSC 360 def_bool n 361 362config ARC_HAS_LLSC 363 bool "Insn: LLOCK/SCOND (efficient atomic ops)" 364 default y 365 depends on !ARC_CANT_LLSC 366 367config ARC_HAS_SWAPE 368 bool "Insn: SWAPE (endian-swap)" 369 default y 370 371if ISA_ARCV2 372 373config ARC_USE_UNALIGNED_MEM_ACCESS 374 bool "Enable unaligned access in HW" 375 default y 376 select HAVE_EFFICIENT_UNALIGNED_ACCESS 377 help 378 The ARC HS architecture supports unaligned memory access 379 which is disabled by default. Enable unaligned access in 380 hardware and use software to use it 381 382config ARC_HAS_LL64 383 bool "Insn: 64bit LDD/STD" 384 help 385 Enable gcc to generate 64-bit load/store instructions 386 ISA mandates even/odd registers to allow encoding of two 387 dest operands with 2 possible source operands. 388 default y 389 390config ARC_HAS_DIV_REM 391 bool "Insn: div, divu, rem, remu" 392 default y 393 394config ARC_HAS_ACCL_REGS 395 bool "Reg Pair ACCL:ACCH (FPU and/or MPY > 6 and/or DSP)" 396 default y 397 help 398 Depending on the configuration, CPU can contain accumulator reg-pair 399 (also referred to as r58:r59). These can also be used by gcc as GPR so 400 kernel needs to save/restore per process 401 402config ARC_DSP_HANDLED 403 def_bool n 404 405config ARC_DSP_SAVE_RESTORE_REGS 406 def_bool n 407 408choice 409 prompt "DSP support" 410 default ARC_DSP_NONE 411 help 412 Depending on the configuration, CPU can contain DSP registers 413 (ACC0_GLO, ACC0_GHI, DSP_BFLY0, DSP_CTRL, DSP_FFT_CTRL). 414 Bellow is options describing how to handle these registers in 415 interrupt entry / exit and in context switch. 416 417config ARC_DSP_NONE 418 bool "No DSP extension presence in HW" 419 help 420 No DSP extension presence in HW 421 422config ARC_DSP_KERNEL 423 bool "DSP extension in HW, no support for userspace" 424 select ARC_HAS_ACCL_REGS 425 select ARC_DSP_HANDLED 426 help 427 DSP extension presence in HW, no support for DSP-enabled userspace 428 applications. We don't save / restore DSP registers and only do 429 some minimal preparations so userspace won't be able to break kernel 430 431config ARC_DSP_USERSPACE 432 bool "Support DSP for userspace apps" 433 select ARC_HAS_ACCL_REGS 434 select ARC_DSP_HANDLED 435 select ARC_DSP_SAVE_RESTORE_REGS 436 help 437 DSP extension presence in HW, support save / restore DSP registers to 438 run DSP-enabled userspace applications 439 440config ARC_DSP_AGU_USERSPACE 441 bool "Support DSP with AGU for userspace apps" 442 select ARC_HAS_ACCL_REGS 443 select ARC_DSP_HANDLED 444 select ARC_DSP_SAVE_RESTORE_REGS 445 help 446 DSP and AGU extensions presence in HW, support save / restore DSP 447 and AGU registers to run DSP-enabled userspace applications 448endchoice 449 450config ARC_IRQ_NO_AUTOSAVE 451 bool "Disable hardware autosave regfile on interrupts" 452 default n 453 help 454 On HS cores, taken interrupt auto saves the regfile on stack. 455 This is programmable and can be optionally disabled in which case 456 software INTERRUPT_PROLOGUE/EPILGUE do the needed work 457 458config ARC_LPB_DISABLE 459 bool "Disable loop buffer (LPB)" 460 help 461 On HS cores, loop buffer (LPB) is programmable in runtime and can 462 be optionally disabled. 463 464endif # ISA_ARCV2 465 466endmenu # "ARC CPU Configuration" 467 468config LINUX_LINK_BASE 469 hex "Kernel link address" 470 default "0x80000000" 471 help 472 ARC700 divides the 32 bit phy address space into two equal halves 473 -Lower 2G (0 - 0x7FFF_FFFF ) is user virtual, translated by MMU 474 -Upper 2G (0x8000_0000 onwards) is untranslated, for kernel 475 Typically Linux kernel is linked at the start of untransalted addr, 476 hence the default value of 0x8zs. 477 However some customers have peripherals mapped at this addr, so 478 Linux needs to be scooted a bit. 479 If you don't know what the above means, leave this setting alone. 480 This needs to match memory start address specified in Device Tree 481 482config LINUX_RAM_BASE 483 hex "RAM base address" 484 default LINUX_LINK_BASE 485 help 486 By default Linux is linked at base of RAM. However in some special 487 cases (such as HSDK), Linux can't be linked at start of DDR, hence 488 this option. 489 490config HIGHMEM 491 bool "High Memory Support" 492 select HAVE_ARCH_PFN_VALID 493 select KMAP_LOCAL 494 help 495 With ARC 2G:2G address split, only upper 2G is directly addressable by 496 kernel. Enable this to potentially allow access to rest of 2G and PAE 497 in future 498 499config ARC_HAS_PAE40 500 bool "Support for the 40-bit Physical Address Extension" 501 depends on ISA_ARCV2 502 select HIGHMEM 503 select PHYS_ADDR_T_64BIT 504 help 505 Enable access to physical memory beyond 4G, only supported on 506 ARC cores with 40 bit Physical Addressing support 507 508config ARC_KVADDR_SIZE 509 int "Kernel Virtual Address Space size (MB)" 510 range 0 512 511 default "256" 512 help 513 The kernel address space is carved out of 256MB of translated address 514 space for catering to vmalloc, modules, pkmap, fixmap. This however may 515 not suffice vmalloc requirements of a 4K CPU EZChip system. So allow 516 this to be stretched to 512 MB (by extending into the reserved 517 kernel-user gutter) 518 519config ARC_CURR_IN_REG 520 bool "Dedicate Register r25 for current_task pointer" 521 default y 522 help 523 This reserved Register R25 to point to Current Task in 524 kernel mode. This saves memory access for each such access 525 526 527config ARC_EMUL_UNALIGNED 528 bool "Emulate unaligned memory access (userspace only)" 529 select SYSCTL_ARCH_UNALIGN_NO_WARN 530 select SYSCTL_ARCH_UNALIGN_ALLOW 531 depends on ISA_ARCOMPACT 532 help 533 This enables misaligned 16 & 32 bit memory access from user space. 534 Use ONLY-IF-ABS-NECESSARY as it will be very slow and also can hide 535 potential bugs in code 536 537config HZ 538 int "Timer Frequency" 539 default 100 540 541config ARC_METAWARE_HLINK 542 bool "Support for Metaware debugger assisted Host access" 543 help 544 This options allows a Linux userland apps to directly access 545 host file system (open/creat/read/write etc) with help from 546 Metaware Debugger. This can come in handy for Linux-host communication 547 when there is no real usable peripheral such as EMAC. 548 549menuconfig ARC_DBG 550 bool "ARC debugging" 551 default y 552 553if ARC_DBG 554 555config ARC_DW2_UNWIND 556 bool "Enable DWARF specific kernel stack unwind" 557 default y 558 select KALLSYMS 559 help 560 Compiles the kernel with DWARF unwind information and can be used 561 to get stack backtraces. 562 563 If you say Y here the resulting kernel image will be slightly larger 564 but not slower, and it will give very useful debugging information. 565 If you don't debug the kernel, you can say N, but we may not be able 566 to solve problems without frame unwind information 567 568config ARC_DBG_TLB_PARANOIA 569 bool "Paranoia Checks in Low Level TLB Handlers" 570 571config ARC_DBG_JUMP_LABEL 572 bool "Paranoid checks in Static Keys (jump labels) code" 573 depends on JUMP_LABEL 574 default y if STATIC_KEYS_SELFTEST 575 help 576 Enable paranoid checks and self-test of both ARC-specific and generic 577 part of static keys (jump labels) related code. 578endif 579 580config ARC_BUILTIN_DTB_NAME 581 string "Built in DTB" 582 help 583 Set the name of the DTB to embed in the vmlinux binary 584 Leaving it blank selects the minimal "skeleton" dtb 585 586endmenu # "ARC Architecture Configuration" 587 588config FORCE_MAX_ZONEORDER 589 int "Maximum zone order" 590 default "12" if ARC_HUGEPAGE_16M 591 default "11" 592 593source "kernel/power/Kconfig" 594