1# SPDX-License-Identifier: GPL-2.0-only 2# 3# Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com) 4# 5 6config ARC 7 def_bool y 8 select ARC_TIMERS 9 select ARCH_HAS_DEBUG_VM_PGTABLE 10 select ARCH_HAS_DMA_PREP_COHERENT 11 select ARCH_HAS_PTE_SPECIAL 12 select ARCH_HAS_SETUP_DMA_OPS 13 select ARCH_HAS_SYNC_DMA_FOR_CPU 14 select ARCH_HAS_SYNC_DMA_FOR_DEVICE 15 select ARCH_SUPPORTS_ATOMIC_RMW if ARC_HAS_LLSC 16 select ARCH_32BIT_OFF_T 17 select BUILDTIME_TABLE_SORT 18 select CLONE_BACKWARDS 19 select COMMON_CLK 20 select DMA_DIRECT_REMAP 21 select GENERIC_ATOMIC64 if !ISA_ARCV2 || !(ARC_HAS_LL64 && ARC_HAS_LLSC) 22 select GENERIC_FIND_FIRST_BIT 23 # for now, we don't need GENERIC_IRQ_PROBE, CONFIG_GENERIC_IRQ_CHIP 24 select GENERIC_IRQ_SHOW 25 select GENERIC_PCI_IOMAP 26 select GENERIC_PENDING_IRQ if SMP 27 select GENERIC_SCHED_CLOCK 28 select GENERIC_SMP_IDLE_THREAD 29 select HAVE_ARCH_KGDB 30 select HAVE_ARCH_TRACEHOOK 31 select HAVE_DEBUG_STACKOVERFLOW 32 select HAVE_DEBUG_KMEMLEAK 33 select HAVE_FUTEX_CMPXCHG if FUTEX 34 select HAVE_IOREMAP_PROT 35 select HAVE_KERNEL_GZIP 36 select HAVE_KERNEL_LZMA 37 select HAVE_KPROBES 38 select HAVE_KRETPROBES 39 select HAVE_MOD_ARCH_SPECIFIC 40 select HAVE_OPROFILE 41 select HAVE_PERF_EVENTS 42 select HANDLE_DOMAIN_IRQ 43 select IRQ_DOMAIN 44 select MODULES_USE_ELF_RELA 45 select OF 46 select OF_EARLY_FLATTREE 47 select PCI_SYSCALL if PCI 48 select PERF_USE_VMALLOC if ARC_CACHE_VIPT_ALIASING 49 select HAVE_ARCH_JUMP_LABEL if ISA_ARCV2 && !CPU_ENDIAN_BE32 50 select SET_FS 51 52config ARCH_HAS_CACHE_LINE_SIZE 53 def_bool y 54 55config TRACE_IRQFLAGS_SUPPORT 56 def_bool y 57 58config LOCKDEP_SUPPORT 59 def_bool y 60 61config SCHED_OMIT_FRAME_POINTER 62 def_bool y 63 64config GENERIC_CSUM 65 def_bool y 66 67config ARCH_DISCONTIGMEM_ENABLE 68 def_bool n 69 70config ARCH_FLATMEM_ENABLE 71 def_bool y 72 73config MMU 74 def_bool y 75 76config NO_IOPORT_MAP 77 def_bool y 78 79config GENERIC_CALIBRATE_DELAY 80 def_bool y 81 82config GENERIC_HWEIGHT 83 def_bool y 84 85config STACKTRACE_SUPPORT 86 def_bool y 87 select STACKTRACE 88 89config HAVE_ARCH_TRANSPARENT_HUGEPAGE 90 def_bool y 91 depends on ARC_MMU_V4 92 93menu "ARC Architecture Configuration" 94 95menu "ARC Platform/SoC/Board" 96 97source "arch/arc/plat-tb10x/Kconfig" 98source "arch/arc/plat-axs10x/Kconfig" 99source "arch/arc/plat-hsdk/Kconfig" 100 101endmenu 102 103choice 104 prompt "ARC Instruction Set" 105 default ISA_ARCV2 106 107config ISA_ARCOMPACT 108 bool "ARCompact ISA" 109 select CPU_NO_EFFICIENT_FFS 110 help 111 The original ARC ISA of ARC600/700 cores 112 113config ISA_ARCV2 114 bool "ARC ISA v2" 115 select ARC_TIMERS_64BIT 116 help 117 ISA for the Next Generation ARC-HS cores 118 119endchoice 120 121menu "ARC CPU Configuration" 122 123choice 124 prompt "ARC Core" 125 default ARC_CPU_770 if ISA_ARCOMPACT 126 default ARC_CPU_HS if ISA_ARCV2 127 128if ISA_ARCOMPACT 129 130config ARC_CPU_750D 131 bool "ARC750D" 132 select ARC_CANT_LLSC 133 help 134 Support for ARC750 core 135 136config ARC_CPU_770 137 bool "ARC770" 138 select ARC_HAS_SWAPE 139 help 140 Support for ARC770 core introduced with Rel 4.10 (Summer 2011) 141 This core has a bunch of cool new features: 142 -MMU-v3: Variable Page Sz (4k, 8k, 16k), bigger J-TLB (128x4) 143 Shared Address Spaces (for sharing TLB entries in MMU) 144 -Caches: New Prog Model, Region Flush 145 -Insns: endian swap, load-locked/store-conditional, time-stamp-ctr 146 147endif #ISA_ARCOMPACT 148 149config ARC_CPU_HS 150 bool "ARC-HS" 151 depends on ISA_ARCV2 152 help 153 Support for ARC HS38x Cores based on ARCv2 ISA 154 The notable features are: 155 - SMP configurations of up to 4 cores with coherency 156 - Optional L2 Cache and IO-Coherency 157 - Revised Interrupt Architecture (multiple priorites, reg banks, 158 auto stack switch, auto regfile save/restore) 159 - MMUv4 (PIPT dcache, Huge Pages) 160 - Instructions for 161 * 64bit load/store: LDD, STD 162 * Hardware assisted divide/remainder: DIV, REM 163 * Function prologue/epilogue: ENTER_S, LEAVE_S 164 * IRQ enable/disable: CLRI, SETI 165 * pop count: FFS, FLS 166 * SETcc, BMSKN, XBFU... 167 168endchoice 169 170config ARC_TUNE_MCPU 171 string "Override default -mcpu compiler flag" 172 default "" 173 help 174 Override default -mcpu=xxx compiler flag (which is set depending on 175 the ISA version) with the specified value. 176 NOTE: If specified flag isn't supported by current compiler the 177 ISA default value will be used as a fallback. 178 179config CPU_BIG_ENDIAN 180 bool "Enable Big Endian Mode" 181 help 182 Build kernel for Big Endian Mode of ARC CPU 183 184config SMP 185 bool "Symmetric Multi-Processing" 186 select ARC_MCIP if ISA_ARCV2 187 help 188 This enables support for systems with more than one CPU. 189 190if SMP 191 192config NR_CPUS 193 int "Maximum number of CPUs (2-4096)" 194 range 2 4096 195 default "4" 196 197config ARC_SMP_HALT_ON_RESET 198 bool "Enable Halt-on-reset boot mode" 199 help 200 In SMP configuration cores can be configured as Halt-on-reset 201 or they could all start at same time. For Halt-on-reset, non 202 masters are parked until Master kicks them so they can start off 203 at designated entry point. For other case, all jump to common 204 entry point and spin wait for Master's signal. 205 206endif #SMP 207 208config ARC_MCIP 209 bool "ARConnect Multicore IP (MCIP) Support " 210 depends on ISA_ARCV2 211 default y if SMP 212 help 213 This IP block enables SMP in ARC-HS38 cores. 214 It provides for cross-core interrupts, multi-core debug 215 hardware semaphores, shared memory,.... 216 217menuconfig ARC_CACHE 218 bool "Enable Cache Support" 219 default y 220 221if ARC_CACHE 222 223config ARC_CACHE_LINE_SHIFT 224 int "Cache Line Length (as power of 2)" 225 range 5 7 226 default "6" 227 help 228 Starting with ARC700 4.9, Cache line length is configurable, 229 This option specifies "N", with Line-len = 2 power N 230 So line lengths of 32, 64, 128 are specified by 5,6,7, respectively 231 Linux only supports same line lengths for I and D caches. 232 233config ARC_HAS_ICACHE 234 bool "Use Instruction Cache" 235 default y 236 237config ARC_HAS_DCACHE 238 bool "Use Data Cache" 239 default y 240 241config ARC_CACHE_PAGES 242 bool "Per Page Cache Control" 243 default y 244 depends on ARC_HAS_ICACHE || ARC_HAS_DCACHE 245 help 246 This can be used to over-ride the global I/D Cache Enable on a 247 per-page basis (but only for pages accessed via MMU such as 248 Kernel Virtual address or User Virtual Address) 249 TLB entries have a per-page Cache Enable Bit. 250 Note that Global I/D ENABLE + Per Page DISABLE works but corollary 251 Global DISABLE + Per Page ENABLE won't work 252 253config ARC_CACHE_VIPT_ALIASING 254 bool "Support VIPT Aliasing D$" 255 depends on ARC_HAS_DCACHE && ISA_ARCOMPACT 256 257endif #ARC_CACHE 258 259config ARC_HAS_ICCM 260 bool "Use ICCM" 261 help 262 Single Cycle RAMS to store Fast Path Code 263 264config ARC_ICCM_SZ 265 int "ICCM Size in KB" 266 default "64" 267 depends on ARC_HAS_ICCM 268 269config ARC_HAS_DCCM 270 bool "Use DCCM" 271 help 272 Single Cycle RAMS to store Fast Path Data 273 274config ARC_DCCM_SZ 275 int "DCCM Size in KB" 276 default "64" 277 depends on ARC_HAS_DCCM 278 279config ARC_DCCM_BASE 280 hex "DCCM map address" 281 default "0xA0000000" 282 depends on ARC_HAS_DCCM 283 284choice 285 prompt "MMU Version" 286 default ARC_MMU_V3 if ARC_CPU_770 287 default ARC_MMU_V2 if ARC_CPU_750D 288 default ARC_MMU_V4 if ARC_CPU_HS 289 290if ISA_ARCOMPACT 291 292config ARC_MMU_V1 293 bool "MMU v1" 294 help 295 Orig ARC700 MMU 296 297config ARC_MMU_V2 298 bool "MMU v2" 299 help 300 Fixed the deficiency of v1 - possible thrashing in memcpy scenario 301 when 2 D-TLB and 1 I-TLB entries index into same 2way set. 302 303config ARC_MMU_V3 304 bool "MMU v3" 305 depends on ARC_CPU_770 306 help 307 Introduced with ARC700 4.10: New Features 308 Variable Page size (1k-16k), var JTLB size 128 x (2 or 4) 309 Shared Address Spaces (SASID) 310 311endif 312 313config ARC_MMU_V4 314 bool "MMU v4" 315 depends on ISA_ARCV2 316 317endchoice 318 319 320choice 321 prompt "MMU Page Size" 322 default ARC_PAGE_SIZE_8K 323 324config ARC_PAGE_SIZE_8K 325 bool "8KB" 326 help 327 Choose between 8k vs 16k 328 329config ARC_PAGE_SIZE_16K 330 bool "16KB" 331 depends on ARC_MMU_V3 || ARC_MMU_V4 332 333config ARC_PAGE_SIZE_4K 334 bool "4KB" 335 depends on ARC_MMU_V3 || ARC_MMU_V4 336 337endchoice 338 339choice 340 prompt "MMU Super Page Size" 341 depends on ISA_ARCV2 && TRANSPARENT_HUGEPAGE 342 default ARC_HUGEPAGE_2M 343 344config ARC_HUGEPAGE_2M 345 bool "2MB" 346 347config ARC_HUGEPAGE_16M 348 bool "16MB" 349 350endchoice 351 352config NODES_SHIFT 353 int "Maximum NUMA Nodes (as a power of 2)" 354 default "0" if !DISCONTIGMEM 355 default "1" if DISCONTIGMEM 356 depends on NEED_MULTIPLE_NODES 357 help 358 Accessing memory beyond 1GB (with or w/o PAE) requires 2 memory 359 zones. 360 361config ARC_COMPACT_IRQ_LEVELS 362 depends on ISA_ARCOMPACT 363 bool "Setup Timer IRQ as high Priority" 364 # if SMP, LV2 enabled ONLY if ARC implementation has LV2 re-entrancy 365 depends on !SMP 366 367config ARC_FPU_SAVE_RESTORE 368 bool "Enable FPU state persistence across context switch" 369 help 370 ARCompact FPU has internal registers to assist with Double precision 371 Floating Point operations. There are control and stauts registers 372 for floating point exceptions and rounding modes. These are 373 preserved across task context switch when enabled. 374 375config ARC_CANT_LLSC 376 def_bool n 377 378config ARC_HAS_LLSC 379 bool "Insn: LLOCK/SCOND (efficient atomic ops)" 380 default y 381 depends on !ARC_CANT_LLSC 382 383config ARC_HAS_SWAPE 384 bool "Insn: SWAPE (endian-swap)" 385 default y 386 387if ISA_ARCV2 388 389config ARC_USE_UNALIGNED_MEM_ACCESS 390 bool "Enable unaligned access in HW" 391 default y 392 select HAVE_EFFICIENT_UNALIGNED_ACCESS 393 help 394 The ARC HS architecture supports unaligned memory access 395 which is disabled by default. Enable unaligned access in 396 hardware and use software to use it 397 398config ARC_HAS_LL64 399 bool "Insn: 64bit LDD/STD" 400 help 401 Enable gcc to generate 64-bit load/store instructions 402 ISA mandates even/odd registers to allow encoding of two 403 dest operands with 2 possible source operands. 404 default y 405 406config ARC_HAS_DIV_REM 407 bool "Insn: div, divu, rem, remu" 408 default y 409 410config ARC_HAS_ACCL_REGS 411 bool "Reg Pair ACCL:ACCH (FPU and/or MPY > 6 and/or DSP)" 412 default y 413 help 414 Depending on the configuration, CPU can contain accumulator reg-pair 415 (also referred to as r58:r59). These can also be used by gcc as GPR so 416 kernel needs to save/restore per process 417 418config ARC_DSP_HANDLED 419 def_bool n 420 421config ARC_DSP_SAVE_RESTORE_REGS 422 def_bool n 423 424choice 425 prompt "DSP support" 426 default ARC_DSP_NONE 427 help 428 Depending on the configuration, CPU can contain DSP registers 429 (ACC0_GLO, ACC0_GHI, DSP_BFLY0, DSP_CTRL, DSP_FFT_CTRL). 430 Bellow is options describing how to handle these registers in 431 interrupt entry / exit and in context switch. 432 433config ARC_DSP_NONE 434 bool "No DSP extension presence in HW" 435 help 436 No DSP extension presence in HW 437 438config ARC_DSP_KERNEL 439 bool "DSP extension in HW, no support for userspace" 440 select ARC_HAS_ACCL_REGS 441 select ARC_DSP_HANDLED 442 help 443 DSP extension presence in HW, no support for DSP-enabled userspace 444 applications. We don't save / restore DSP registers and only do 445 some minimal preparations so userspace won't be able to break kernel 446 447config ARC_DSP_USERSPACE 448 bool "Support DSP for userspace apps" 449 select ARC_HAS_ACCL_REGS 450 select ARC_DSP_HANDLED 451 select ARC_DSP_SAVE_RESTORE_REGS 452 help 453 DSP extension presence in HW, support save / restore DSP registers to 454 run DSP-enabled userspace applications 455 456config ARC_DSP_AGU_USERSPACE 457 bool "Support DSP with AGU for userspace apps" 458 select ARC_HAS_ACCL_REGS 459 select ARC_DSP_HANDLED 460 select ARC_DSP_SAVE_RESTORE_REGS 461 help 462 DSP and AGU extensions presence in HW, support save / restore DSP 463 and AGU registers to run DSP-enabled userspace applications 464endchoice 465 466config ARC_IRQ_NO_AUTOSAVE 467 bool "Disable hardware autosave regfile on interrupts" 468 default n 469 help 470 On HS cores, taken interrupt auto saves the regfile on stack. 471 This is programmable and can be optionally disabled in which case 472 software INTERRUPT_PROLOGUE/EPILGUE do the needed work 473 474config ARC_LPB_DISABLE 475 bool "Disable loop buffer (LPB)" 476 help 477 On HS cores, loop buffer (LPB) is programmable in runtime and can 478 be optionally disabled. 479 480endif # ISA_ARCV2 481 482endmenu # "ARC CPU Configuration" 483 484config LINUX_LINK_BASE 485 hex "Kernel link address" 486 default "0x80000000" 487 help 488 ARC700 divides the 32 bit phy address space into two equal halves 489 -Lower 2G (0 - 0x7FFF_FFFF ) is user virtual, translated by MMU 490 -Upper 2G (0x8000_0000 onwards) is untranslated, for kernel 491 Typically Linux kernel is linked at the start of untransalted addr, 492 hence the default value of 0x8zs. 493 However some customers have peripherals mapped at this addr, so 494 Linux needs to be scooted a bit. 495 If you don't know what the above means, leave this setting alone. 496 This needs to match memory start address specified in Device Tree 497 498config LINUX_RAM_BASE 499 hex "RAM base address" 500 default LINUX_LINK_BASE 501 help 502 By default Linux is linked at base of RAM. However in some special 503 cases (such as HSDK), Linux can't be linked at start of DDR, hence 504 this option. 505 506config HIGHMEM 507 bool "High Memory Support" 508 select ARCH_DISCONTIGMEM_ENABLE 509 help 510 With ARC 2G:2G address split, only upper 2G is directly addressable by 511 kernel. Enable this to potentially allow access to rest of 2G and PAE 512 in future 513 514config ARC_HAS_PAE40 515 bool "Support for the 40-bit Physical Address Extension" 516 depends on ISA_ARCV2 517 select HIGHMEM 518 select PHYS_ADDR_T_64BIT 519 help 520 Enable access to physical memory beyond 4G, only supported on 521 ARC cores with 40 bit Physical Addressing support 522 523config ARC_KVADDR_SIZE 524 int "Kernel Virtual Address Space size (MB)" 525 range 0 512 526 default "256" 527 help 528 The kernel address space is carved out of 256MB of translated address 529 space for catering to vmalloc, modules, pkmap, fixmap. This however may 530 not suffice vmalloc requirements of a 4K CPU EZChip system. So allow 531 this to be stretched to 512 MB (by extending into the reserved 532 kernel-user gutter) 533 534config ARC_CURR_IN_REG 535 bool "Dedicate Register r25 for current_task pointer" 536 default y 537 help 538 This reserved Register R25 to point to Current Task in 539 kernel mode. This saves memory access for each such access 540 541 542config ARC_EMUL_UNALIGNED 543 bool "Emulate unaligned memory access (userspace only)" 544 select SYSCTL_ARCH_UNALIGN_NO_WARN 545 select SYSCTL_ARCH_UNALIGN_ALLOW 546 depends on ISA_ARCOMPACT 547 help 548 This enables misaligned 16 & 32 bit memory access from user space. 549 Use ONLY-IF-ABS-NECESSARY as it will be very slow and also can hide 550 potential bugs in code 551 552config HZ 553 int "Timer Frequency" 554 default 100 555 556config ARC_METAWARE_HLINK 557 bool "Support for Metaware debugger assisted Host access" 558 help 559 This options allows a Linux userland apps to directly access 560 host file system (open/creat/read/write etc) with help from 561 Metaware Debugger. This can come in handy for Linux-host communication 562 when there is no real usable peripheral such as EMAC. 563 564menuconfig ARC_DBG 565 bool "ARC debugging" 566 default y 567 568if ARC_DBG 569 570config ARC_DW2_UNWIND 571 bool "Enable DWARF specific kernel stack unwind" 572 default y 573 select KALLSYMS 574 help 575 Compiles the kernel with DWARF unwind information and can be used 576 to get stack backtraces. 577 578 If you say Y here the resulting kernel image will be slightly larger 579 but not slower, and it will give very useful debugging information. 580 If you don't debug the kernel, you can say N, but we may not be able 581 to solve problems without frame unwind information 582 583config ARC_DBG_TLB_PARANOIA 584 bool "Paranoia Checks in Low Level TLB Handlers" 585 586config ARC_DBG_JUMP_LABEL 587 bool "Paranoid checks in Static Keys (jump labels) code" 588 depends on JUMP_LABEL 589 default y if STATIC_KEYS_SELFTEST 590 help 591 Enable paranoid checks and self-test of both ARC-specific and generic 592 part of static keys (jump labels) related code. 593endif 594 595config ARC_BUILTIN_DTB_NAME 596 string "Built in DTB" 597 help 598 Set the name of the DTB to embed in the vmlinux binary 599 Leaving it blank selects the minimal "skeleton" dtb 600 601endmenu # "ARC Architecture Configuration" 602 603config FORCE_MAX_ZONEORDER 604 int "Maximum zone order" 605 default "12" if ARC_HUGEPAGE_16M 606 default "11" 607 608source "kernel/power/Kconfig" 609