1# SPDX-License-Identifier: GPL-2.0-only 2# 3# Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com) 4# 5 6config ARC 7 def_bool y 8 select ARC_TIMERS 9 select ARCH_HAS_CPU_CACHE_ALIASING 10 select ARCH_HAS_CACHE_LINE_SIZE 11 select ARCH_HAS_DEBUG_VM_PGTABLE 12 select ARCH_HAS_DMA_PREP_COHERENT 13 select ARCH_HAS_PTE_SPECIAL 14 select ARCH_HAS_SETUP_DMA_OPS 15 select ARCH_HAS_SYNC_DMA_FOR_CPU 16 select ARCH_HAS_SYNC_DMA_FOR_DEVICE 17 select ARCH_NEED_CMPXCHG_1_EMU 18 select ARCH_SUPPORTS_ATOMIC_RMW if ARC_HAS_LLSC 19 select ARCH_32BIT_OFF_T 20 select BUILDTIME_TABLE_SORT 21 select GENERIC_BUILTIN_DTB 22 select CLONE_BACKWARDS 23 select COMMON_CLK 24 select DMA_DIRECT_REMAP 25 select GENERIC_ATOMIC64 if !ISA_ARCV2 || !(ARC_HAS_LL64 && ARC_HAS_LLSC) 26 # for now, we don't need GENERIC_IRQ_PROBE, CONFIG_GENERIC_IRQ_CHIP 27 select GENERIC_IRQ_SHOW 28 select GENERIC_PCI_IOMAP 29 select GENERIC_PENDING_IRQ if SMP 30 select GENERIC_SCHED_CLOCK 31 select GENERIC_SMP_IDLE_THREAD 32 select GENERIC_IOREMAP 33 select GENERIC_STRNCPY_FROM_USER if MMU 34 select GENERIC_STRNLEN_USER if MMU 35 select HAVE_ARCH_KGDB 36 select HAVE_ARCH_TRACEHOOK 37 select HAVE_ARCH_TRANSPARENT_HUGEPAGE if ARC_MMU_V4 38 select HAVE_DEBUG_STACKOVERFLOW 39 select HAVE_DEBUG_KMEMLEAK 40 select HAVE_IOREMAP_PROT 41 select HAVE_KERNEL_GZIP 42 select HAVE_KERNEL_LZMA 43 select HAVE_KPROBES 44 select HAVE_KRETPROBES 45 select HAVE_REGS_AND_STACK_ACCESS_API 46 select HAVE_MOD_ARCH_SPECIFIC 47 select HAVE_PERF_EVENTS 48 select HAVE_SYSCALL_TRACEPOINTS 49 select IRQ_DOMAIN 50 select LOCK_MM_AND_FIND_VMA 51 select MODULES_USE_ELF_RELA 52 select OF 53 select OF_EARLY_FLATTREE 54 select PCI_SYSCALL if PCI 55 select HAVE_ARCH_JUMP_LABEL if ISA_ARCV2 && !CPU_ENDIAN_BE32 56 select TRACE_IRQFLAGS_SUPPORT 57 select HAVE_EBPF_JIT if ISA_ARCV2 58 59config LOCKDEP_SUPPORT 60 def_bool y 61 62config SCHED_OMIT_FRAME_POINTER 63 def_bool y 64 65config GENERIC_CSUM 66 def_bool y 67 68config ARCH_FLATMEM_ENABLE 69 def_bool y 70 71config MMU 72 def_bool y 73 74config NO_IOPORT_MAP 75 def_bool y 76 77config GENERIC_CALIBRATE_DELAY 78 def_bool y 79 80config GENERIC_HWEIGHT 81 def_bool y 82 83config STACKTRACE_SUPPORT 84 def_bool y 85 select STACKTRACE 86 87menu "ARC Architecture Configuration" 88 89menu "ARC Platform/SoC/Board" 90 91source "arch/arc/plat-tb10x/Kconfig" 92source "arch/arc/plat-axs10x/Kconfig" 93source "arch/arc/plat-hsdk/Kconfig" 94 95endmenu 96 97choice 98 prompt "ARC Instruction Set" 99 default ISA_ARCV2 100 101config ISA_ARCOMPACT 102 bool "ARCompact ISA" 103 select CPU_NO_EFFICIENT_FFS 104 help 105 The original ARC ISA of ARC600/700 cores 106 107config ISA_ARCV2 108 bool "ARC ISA v2" 109 select ARC_TIMERS_64BIT 110 help 111 ISA for the Next Generation ARC-HS cores 112 113endchoice 114 115menu "ARC CPU Configuration" 116 117choice 118 prompt "ARC Core" 119 default ARC_CPU_770 if ISA_ARCOMPACT 120 default ARC_CPU_HS if ISA_ARCV2 121 122config ARC_CPU_770 123 bool "ARC770" 124 depends on ISA_ARCOMPACT 125 select ARC_HAS_SWAPE 126 help 127 Support for ARC770 core introduced with Rel 4.10 (Summer 2011) 128 This core has a bunch of cool new features: 129 -MMU-v3: Variable Page Sz (4k, 8k, 16k), bigger J-TLB (128x4) 130 Shared Address Spaces (for sharing TLB entries in MMU) 131 -Caches: New Prog Model, Region Flush 132 -Insns: endian swap, load-locked/store-conditional, time-stamp-ctr 133 134config ARC_CPU_HS 135 bool "ARC-HS" 136 depends on ISA_ARCV2 137 help 138 Support for ARC HS38x Cores based on ARCv2 ISA 139 The notable features are: 140 - SMP configurations of up to 4 cores with coherency 141 - Optional L2 Cache and IO-Coherency 142 - Revised Interrupt Architecture (multiple priorites, reg banks, 143 auto stack switch, auto regfile save/restore) 144 - MMUv4 (PIPT dcache, Huge Pages) 145 - Instructions for 146 * 64bit load/store: LDD, STD 147 * Hardware assisted divide/remainder: DIV, REM 148 * Function prologue/epilogue: ENTER_S, LEAVE_S 149 * IRQ enable/disable: CLRI, SETI 150 * pop count: FFS, FLS 151 * SETcc, BMSKN, XBFU... 152 153endchoice 154 155config ARC_TUNE_MCPU 156 string "Override default -mcpu compiler flag" 157 default "" 158 help 159 Override default -mcpu=xxx compiler flag (which is set depending on 160 the ISA version) with the specified value. 161 NOTE: If specified flag isn't supported by current compiler the 162 ISA default value will be used as a fallback. 163 164config CPU_BIG_ENDIAN 165 bool "Enable Big Endian Mode" 166 help 167 Build kernel for Big Endian Mode of ARC CPU 168 169config SMP 170 bool "Symmetric Multi-Processing" 171 select ARC_MCIP if ISA_ARCV2 172 help 173 This enables support for systems with more than one CPU. 174 175if SMP 176 177config NR_CPUS 178 int "Maximum number of CPUs (2-4096)" 179 range 2 4096 180 default "4" 181 182config ARC_SMP_HALT_ON_RESET 183 bool "Enable Halt-on-reset boot mode" 184 help 185 In SMP configuration cores can be configured as Halt-on-reset 186 or they could all start at same time. For Halt-on-reset, non 187 masters are parked until Master kicks them so they can start off 188 at designated entry point. For other case, all jump to common 189 entry point and spin wait for Master's signal. 190 191endif #SMP 192 193config ARC_MCIP 194 bool "ARConnect Multicore IP (MCIP) Support " 195 depends on ISA_ARCV2 196 default y if SMP 197 help 198 This IP block enables SMP in ARC-HS38 cores. 199 It provides for cross-core interrupts, multi-core debug 200 hardware semaphores, shared memory,.... 201 202menuconfig ARC_CACHE 203 bool "Enable Cache Support" 204 default y 205 206if ARC_CACHE 207 208config ARC_CACHE_LINE_SHIFT 209 int "Cache Line Length (as power of 2)" 210 range 5 7 211 default "6" 212 help 213 Starting with ARC700 4.9, Cache line length is configurable, 214 This option specifies "N", with Line-len = 2 power N 215 So line lengths of 32, 64, 128 are specified by 5,6,7, respectively 216 Linux only supports same line lengths for I and D caches. 217 218config ARC_HAS_ICACHE 219 bool "Use Instruction Cache" 220 default y 221 222config ARC_HAS_DCACHE 223 bool "Use Data Cache" 224 default y 225 226config ARC_CACHE_PAGES 227 bool "Per Page Cache Control" 228 default y 229 depends on ARC_HAS_ICACHE || ARC_HAS_DCACHE 230 help 231 This can be used to over-ride the global I/D Cache Enable on a 232 per-page basis (but only for pages accessed via MMU such as 233 Kernel Virtual address or User Virtual Address) 234 TLB entries have a per-page Cache Enable Bit. 235 Note that Global I/D ENABLE + Per Page DISABLE works but corollary 236 Global DISABLE + Per Page ENABLE won't work 237 238endif #ARC_CACHE 239 240config ARC_HAS_ICCM 241 bool "Use ICCM" 242 help 243 Single Cycle RAMS to store Fast Path Code 244 245config ARC_ICCM_SZ 246 int "ICCM Size in KB" 247 default "64" 248 depends on ARC_HAS_ICCM 249 250config ARC_HAS_DCCM 251 bool "Use DCCM" 252 help 253 Single Cycle RAMS to store Fast Path Data 254 255config ARC_DCCM_SZ 256 int "DCCM Size in KB" 257 default "64" 258 depends on ARC_HAS_DCCM 259 260config ARC_DCCM_BASE 261 hex "DCCM map address" 262 default "0xA0000000" 263 depends on ARC_HAS_DCCM 264 265choice 266 prompt "MMU Version" 267 default ARC_MMU_V3 if ISA_ARCOMPACT 268 default ARC_MMU_V4 if ISA_ARCV2 269 270config ARC_MMU_V3 271 bool "MMU v3" 272 depends on ISA_ARCOMPACT 273 help 274 Introduced with ARC700 4.10: New Features 275 Variable Page size (1k-16k), var JTLB size 128 x (2 or 4) 276 Shared Address Spaces (SASID) 277 278config ARC_MMU_V4 279 bool "MMU v4" 280 depends on ISA_ARCV2 281 282endchoice 283 284 285choice 286 prompt "MMU Page Size" 287 default ARC_PAGE_SIZE_8K 288 289config ARC_PAGE_SIZE_8K 290 bool "8KB" 291 select HAVE_PAGE_SIZE_8KB 292 help 293 Choose between 8k vs 16k 294 295config ARC_PAGE_SIZE_16K 296 select HAVE_PAGE_SIZE_16KB 297 bool "16KB" 298 299config ARC_PAGE_SIZE_4K 300 bool "4KB" 301 select HAVE_PAGE_SIZE_4KB 302 303endchoice 304 305choice 306 prompt "MMU Super Page Size" 307 depends on ISA_ARCV2 && TRANSPARENT_HUGEPAGE 308 default ARC_HUGEPAGE_2M 309 310config ARC_HUGEPAGE_2M 311 bool "2MB" 312 313config ARC_HUGEPAGE_16M 314 bool "16MB" 315 316endchoice 317 318config PGTABLE_LEVELS 319 int "Number of Page table levels" 320 default 2 321 322config ARC_COMPACT_IRQ_LEVELS 323 depends on ISA_ARCOMPACT 324 bool "Setup Timer IRQ as high Priority" 325 # if SMP, LV2 enabled ONLY if ARC implementation has LV2 re-entrancy 326 depends on !SMP 327 328config ARC_FPU_SAVE_RESTORE 329 bool "Enable FPU state persistence across context switch" 330 help 331 ARCompact FPU has internal registers to assist with Double precision 332 Floating Point operations. There are control and stauts registers 333 for floating point exceptions and rounding modes. These are 334 preserved across task context switch when enabled. 335 336config ARC_CANT_LLSC 337 def_bool n 338 339config ARC_HAS_LLSC 340 bool "Insn: LLOCK/SCOND (efficient atomic ops)" 341 default y 342 depends on !ARC_CANT_LLSC 343 344config ARC_HAS_SWAPE 345 bool "Insn: SWAPE (endian-swap)" 346 default y 347 348if ISA_ARCV2 349 350config ARC_USE_UNALIGNED_MEM_ACCESS 351 bool "Enable unaligned access in HW" 352 default y 353 select HAVE_EFFICIENT_UNALIGNED_ACCESS 354 help 355 The ARC HS architecture supports unaligned memory access 356 which is disabled by default. Enable unaligned access in 357 hardware and use software to use it 358 359config ARC_HAS_LL64 360 bool "Insn: 64bit LDD/STD" 361 help 362 Enable gcc to generate 64-bit load/store instructions 363 ISA mandates even/odd registers to allow encoding of two 364 dest operands with 2 possible source operands. 365 default y 366 367config ARC_HAS_DIV_REM 368 bool "Insn: div, divu, rem, remu" 369 default y 370 371config ARC_HAS_ACCL_REGS 372 bool "Reg Pair ACCL:ACCH (FPU and/or MPY > 6 and/or DSP)" 373 default y 374 help 375 Depending on the configuration, CPU can contain accumulator reg-pair 376 (also referred to as r58:r59). These can also be used by gcc as GPR so 377 kernel needs to save/restore per process 378 379config ARC_DSP_HANDLED 380 def_bool n 381 382config ARC_DSP_SAVE_RESTORE_REGS 383 def_bool n 384 385choice 386 prompt "DSP support" 387 default ARC_DSP_NONE 388 help 389 Depending on the configuration, CPU can contain DSP registers 390 (ACC0_GLO, ACC0_GHI, DSP_BFLY0, DSP_CTRL, DSP_FFT_CTRL). 391 Below are options describing how to handle these registers in 392 interrupt entry / exit and in context switch. 393 394config ARC_DSP_NONE 395 bool "No DSP extension presence in HW" 396 help 397 No DSP extension presence in HW 398 399config ARC_DSP_KERNEL 400 bool "DSP extension in HW, no support for userspace" 401 select ARC_HAS_ACCL_REGS 402 select ARC_DSP_HANDLED 403 help 404 DSP extension presence in HW, no support for DSP-enabled userspace 405 applications. We don't save / restore DSP registers and only do 406 some minimal preparations so userspace won't be able to break kernel 407 408config ARC_DSP_USERSPACE 409 bool "Support DSP for userspace apps" 410 select ARC_HAS_ACCL_REGS 411 select ARC_DSP_HANDLED 412 select ARC_DSP_SAVE_RESTORE_REGS 413 help 414 DSP extension presence in HW, support save / restore DSP registers to 415 run DSP-enabled userspace applications 416 417config ARC_DSP_AGU_USERSPACE 418 bool "Support DSP with AGU for userspace apps" 419 select ARC_HAS_ACCL_REGS 420 select ARC_DSP_HANDLED 421 select ARC_DSP_SAVE_RESTORE_REGS 422 help 423 DSP and AGU extensions presence in HW, support save / restore DSP 424 and AGU registers to run DSP-enabled userspace applications 425endchoice 426 427config ARC_IRQ_NO_AUTOSAVE 428 bool "Disable hardware autosave regfile on interrupts" 429 default n 430 help 431 On HS cores, taken interrupt auto saves the regfile on stack. 432 This is programmable and can be optionally disabled in which case 433 software INTERRUPT_PROLOGUE/EPILGUE do the needed work 434 435config ARC_LPB_DISABLE 436 bool "Disable loop buffer (LPB)" 437 help 438 On HS cores, loop buffer (LPB) is programmable in runtime and can 439 be optionally disabled. 440 441endif # ISA_ARCV2 442 443endmenu # "ARC CPU Configuration" 444 445config LINUX_LINK_BASE 446 hex "Kernel link address" 447 default "0x80000000" 448 help 449 ARC700 divides the 32 bit phy address space into two equal halves 450 -Lower 2G (0 - 0x7FFF_FFFF ) is user virtual, translated by MMU 451 -Upper 2G (0x8000_0000 onwards) is untranslated, for kernel 452 Typically Linux kernel is linked at the start of untransalted addr, 453 hence the default value of 0x8zs. 454 However some customers have peripherals mapped at this addr, so 455 Linux needs to be scooted a bit. 456 If you don't know what the above means, leave this setting alone. 457 This needs to match memory start address specified in Device Tree 458 459config LINUX_RAM_BASE 460 hex "RAM base address" 461 default LINUX_LINK_BASE 462 help 463 By default Linux is linked at base of RAM. However in some special 464 cases (such as HSDK), Linux can't be linked at start of DDR, hence 465 this option. 466 467config HIGHMEM 468 bool "High Memory Support" 469 select HAVE_ARCH_PFN_VALID 470 select KMAP_LOCAL 471 help 472 With ARC 2G:2G address split, only upper 2G is directly addressable by 473 kernel. Enable this to potentially allow access to rest of 2G and PAE 474 in future 475 476config ARC_HAS_PAE40 477 bool "Support for the 40-bit Physical Address Extension" 478 depends on ARC_MMU_V4 479 depends on !ARC_PAGE_SIZE_4K 480 select HIGHMEM 481 select PHYS_ADDR_T_64BIT 482 help 483 Enable access to physical memory beyond 4G, only supported on 484 ARC cores with 40 bit Physical Addressing support 485 486config ARC_KVADDR_SIZE 487 int "Kernel Virtual Address Space size (MB)" 488 range 0 512 489 default "256" 490 help 491 The kernel address space is carved out of 256MB of translated address 492 space for catering to vmalloc, modules, pkmap, fixmap. This however may 493 not suffice vmalloc requirements of a 4K CPU EZChip system. So allow 494 this to be stretched to 512 MB (by extending into the reserved 495 kernel-user gutter) 496 497config ARC_CURR_IN_REG 498 bool "cache current task pointer in gp" 499 default y 500 help 501 This reserves gp register to point to Current Task in 502 kernel mode eliding memory access for each access 503 504 505config ARC_EMUL_UNALIGNED 506 bool "Emulate unaligned memory access (userspace only)" 507 select SYSCTL_ARCH_UNALIGN_NO_WARN 508 select SYSCTL_ARCH_UNALIGN_ALLOW 509 depends on ISA_ARCOMPACT 510 help 511 This enables misaligned 16 & 32 bit memory access from user space. 512 Use ONLY-IF-ABS-NECESSARY as it will be very slow and also can hide 513 potential bugs in code 514 515config HZ 516 int "Timer Frequency" 517 default 100 518 519config ARC_METAWARE_HLINK 520 bool "Support for Metaware debugger assisted Host access" 521 help 522 This options allows a Linux userland apps to directly access 523 host file system (open/creat/read/write etc) with help from 524 Metaware Debugger. This can come in handy for Linux-host communication 525 when there is no real usable peripheral such as EMAC. 526 527menuconfig ARC_DBG 528 bool "ARC debugging" 529 default y 530 531if ARC_DBG 532 533config ARC_DW2_UNWIND 534 bool "Enable DWARF specific kernel stack unwind" 535 default y 536 select KALLSYMS 537 help 538 Compiles the kernel with DWARF unwind information and can be used 539 to get stack backtraces. 540 541 If you say Y here the resulting kernel image will be slightly larger 542 but not slower, and it will give very useful debugging information. 543 If you don't debug the kernel, you can say N, but we may not be able 544 to solve problems without frame unwind information 545 546config ARC_DBG_JUMP_LABEL 547 bool "Paranoid checks in Static Keys (jump labels) code" 548 depends on JUMP_LABEL 549 default y if STATIC_KEYS_SELFTEST 550 help 551 Enable paranoid checks and self-test of both ARC-specific and generic 552 part of static keys (jump labels) related code. 553endif 554 555config BUILTIN_DTB_NAME 556 string "Built in DTB" 557 default "nsim_700" 558 help 559 Set the name of the DTB to embed in the vmlinux binary. 560 561endmenu # "ARC Architecture Configuration" 562 563config ARCH_FORCE_MAX_ORDER 564 int "Maximum zone order" 565 default "11" if ARC_HUGEPAGE_16M 566 default "10" 567 568source "kernel/power/Kconfig" 569