1 /* 2 * linux/arch/alpha/kernel/time.c 3 * 4 * Copyright (C) 1991, 1992, 1995, 1999, 2000 Linus Torvalds 5 * 6 * This file contains the PC-specific time handling details: 7 * reading the RTC at bootup, etc.. 8 * 1994-07-02 Alan Modra 9 * fixed set_rtc_mmss, fixed time.year for >= 2000, new mktime 10 * 1995-03-26 Markus Kuhn 11 * fixed 500 ms bug at call to set_rtc_mmss, fixed DS12887 12 * precision CMOS clock update 13 * 1997-09-10 Updated NTP code according to technical memorandum Jan '96 14 * "A Kernel Model for Precision Timekeeping" by Dave Mills 15 * 1997-01-09 Adrian Sun 16 * use interval timer if CONFIG_RTC=y 17 * 1997-10-29 John Bowman (bowman@math.ualberta.ca) 18 * fixed tick loss calculation in timer_interrupt 19 * (round system clock to nearest tick instead of truncating) 20 * fixed algorithm in time_init for getting time from CMOS clock 21 * 1999-04-16 Thorsten Kranzkowski (dl8bcu@gmx.net) 22 * fixed algorithm in do_gettimeofday() for calculating the precise time 23 * from processor cycle counter (now taking lost_ticks into account) 24 * 2000-08-13 Jan-Benedict Glaw <jbglaw@lug-owl.de> 25 * Fixed time_init to be aware of epoches != 1900. This prevents 26 * booting up in 2048 for me;) Code is stolen from rtc.c. 27 * 2003-06-03 R. Scott Bailey <scott.bailey@eds.com> 28 * Tighten sanity in time_init from 1% (10,000 PPM) to 250 PPM 29 */ 30 #include <linux/config.h> 31 #include <linux/errno.h> 32 #include <linux/module.h> 33 #include <linux/sched.h> 34 #include <linux/kernel.h> 35 #include <linux/param.h> 36 #include <linux/string.h> 37 #include <linux/mm.h> 38 #include <linux/delay.h> 39 #include <linux/ioport.h> 40 #include <linux/irq.h> 41 #include <linux/interrupt.h> 42 #include <linux/init.h> 43 #include <linux/bcd.h> 44 #include <linux/profile.h> 45 46 #include <asm/uaccess.h> 47 #include <asm/io.h> 48 #include <asm/hwrpb.h> 49 #include <asm/8253pit.h> 50 51 #include <linux/mc146818rtc.h> 52 #include <linux/time.h> 53 #include <linux/timex.h> 54 55 #include "proto.h" 56 #include "irq_impl.h" 57 58 extern unsigned long wall_jiffies; /* kernel/timer.c */ 59 60 static int set_rtc_mmss(unsigned long); 61 62 DEFINE_SPINLOCK(rtc_lock); 63 64 #define TICK_SIZE (tick_nsec / 1000) 65 66 /* 67 * Shift amount by which scaled_ticks_per_cycle is scaled. Shifting 68 * by 48 gives us 16 bits for HZ while keeping the accuracy good even 69 * for large CPU clock rates. 70 */ 71 #define FIX_SHIFT 48 72 73 /* lump static variables together for more efficient access: */ 74 static struct { 75 /* cycle counter last time it got invoked */ 76 __u32 last_time; 77 /* ticks/cycle * 2^48 */ 78 unsigned long scaled_ticks_per_cycle; 79 /* last time the CMOS clock got updated */ 80 time_t last_rtc_update; 81 /* partial unused tick */ 82 unsigned long partial_tick; 83 } state; 84 85 unsigned long est_cycle_freq; 86 87 88 static inline __u32 rpcc(void) 89 { 90 __u32 result; 91 asm volatile ("rpcc %0" : "=r"(result)); 92 return result; 93 } 94 95 /* 96 * Scheduler clock - returns current time in nanosec units. 97 * 98 * Copied from ARM code for expediency... ;-} 99 */ 100 unsigned long long sched_clock(void) 101 { 102 return (unsigned long long)jiffies * (1000000000 / HZ); 103 } 104 105 106 /* 107 * timer_interrupt() needs to keep up the real-time clock, 108 * as well as call the "do_timer()" routine every clocktick 109 */ 110 irqreturn_t timer_interrupt(int irq, void *dev, struct pt_regs * regs) 111 { 112 unsigned long delta; 113 __u32 now; 114 long nticks; 115 116 #ifndef CONFIG_SMP 117 /* Not SMP, do kernel PC profiling here. */ 118 profile_tick(CPU_PROFILING, regs); 119 #endif 120 121 write_seqlock(&xtime_lock); 122 123 /* 124 * Calculate how many ticks have passed since the last update, 125 * including any previous partial leftover. Save any resulting 126 * fraction for the next pass. 127 */ 128 now = rpcc(); 129 delta = now - state.last_time; 130 state.last_time = now; 131 delta = delta * state.scaled_ticks_per_cycle + state.partial_tick; 132 state.partial_tick = delta & ((1UL << FIX_SHIFT) - 1); 133 nticks = delta >> FIX_SHIFT; 134 135 while (nticks > 0) { 136 do_timer(regs); 137 #ifndef CONFIG_SMP 138 update_process_times(user_mode(regs)); 139 #endif 140 nticks--; 141 } 142 143 /* 144 * If we have an externally synchronized Linux clock, then update 145 * CMOS clock accordingly every ~11 minutes. Set_rtc_mmss() has to be 146 * called as close as possible to 500 ms before the new second starts. 147 */ 148 if (ntp_synced() 149 && xtime.tv_sec > state.last_rtc_update + 660 150 && xtime.tv_nsec >= 500000 - ((unsigned) TICK_SIZE) / 2 151 && xtime.tv_nsec <= 500000 + ((unsigned) TICK_SIZE) / 2) { 152 int tmp = set_rtc_mmss(xtime.tv_sec); 153 state.last_rtc_update = xtime.tv_sec - (tmp ? 600 : 0); 154 } 155 156 write_sequnlock(&xtime_lock); 157 return IRQ_HANDLED; 158 } 159 160 void 161 common_init_rtc(void) 162 { 163 unsigned char x; 164 165 /* Reset periodic interrupt frequency. */ 166 x = CMOS_READ(RTC_FREQ_SELECT) & 0x3f; 167 /* Test includes known working values on various platforms 168 where 0x26 is wrong; we refuse to change those. */ 169 if (x != 0x26 && x != 0x25 && x != 0x19 && x != 0x06) { 170 printk("Setting RTC_FREQ to 1024 Hz (%x)\n", x); 171 CMOS_WRITE(0x26, RTC_FREQ_SELECT); 172 } 173 174 /* Turn on periodic interrupts. */ 175 x = CMOS_READ(RTC_CONTROL); 176 if (!(x & RTC_PIE)) { 177 printk("Turning on RTC interrupts.\n"); 178 x |= RTC_PIE; 179 x &= ~(RTC_AIE | RTC_UIE); 180 CMOS_WRITE(x, RTC_CONTROL); 181 } 182 (void) CMOS_READ(RTC_INTR_FLAGS); 183 184 outb(0x36, 0x43); /* pit counter 0: system timer */ 185 outb(0x00, 0x40); 186 outb(0x00, 0x40); 187 188 outb(0xb6, 0x43); /* pit counter 2: speaker */ 189 outb(0x31, 0x42); 190 outb(0x13, 0x42); 191 192 init_rtc_irq(); 193 } 194 195 196 /* Validate a computed cycle counter result against the known bounds for 197 the given processor core. There's too much brokenness in the way of 198 timing hardware for any one method to work everywhere. :-( 199 200 Return 0 if the result cannot be trusted, otherwise return the argument. */ 201 202 static unsigned long __init 203 validate_cc_value(unsigned long cc) 204 { 205 static struct bounds { 206 unsigned int min, max; 207 } cpu_hz[] __initdata = { 208 [EV3_CPU] = { 50000000, 200000000 }, /* guess */ 209 [EV4_CPU] = { 100000000, 300000000 }, 210 [LCA4_CPU] = { 100000000, 300000000 }, /* guess */ 211 [EV45_CPU] = { 200000000, 300000000 }, 212 [EV5_CPU] = { 250000000, 433000000 }, 213 [EV56_CPU] = { 333000000, 667000000 }, 214 [PCA56_CPU] = { 400000000, 600000000 }, /* guess */ 215 [PCA57_CPU] = { 500000000, 600000000 }, /* guess */ 216 [EV6_CPU] = { 466000000, 600000000 }, 217 [EV67_CPU] = { 600000000, 750000000 }, 218 [EV68AL_CPU] = { 750000000, 940000000 }, 219 [EV68CB_CPU] = { 1000000000, 1333333333 }, 220 /* None of the following are shipping as of 2001-11-01. */ 221 [EV68CX_CPU] = { 1000000000, 1700000000 }, /* guess */ 222 [EV69_CPU] = { 1000000000, 1700000000 }, /* guess */ 223 [EV7_CPU] = { 800000000, 1400000000 }, /* guess */ 224 [EV79_CPU] = { 1000000000, 2000000000 }, /* guess */ 225 }; 226 227 /* Allow for some drift in the crystal. 10MHz is more than enough. */ 228 const unsigned int deviation = 10000000; 229 230 struct percpu_struct *cpu; 231 unsigned int index; 232 233 cpu = (struct percpu_struct *)((char*)hwrpb + hwrpb->processor_offset); 234 index = cpu->type & 0xffffffff; 235 236 /* If index out of bounds, no way to validate. */ 237 if (index >= sizeof(cpu_hz)/sizeof(cpu_hz[0])) 238 return cc; 239 240 /* If index contains no data, no way to validate. */ 241 if (cpu_hz[index].max == 0) 242 return cc; 243 244 if (cc < cpu_hz[index].min - deviation 245 || cc > cpu_hz[index].max + deviation) 246 return 0; 247 248 return cc; 249 } 250 251 252 /* 253 * Calibrate CPU clock using legacy 8254 timer/counter. Stolen from 254 * arch/i386/time.c. 255 */ 256 257 #define CALIBRATE_LATCH 0xffff 258 #define TIMEOUT_COUNT 0x100000 259 260 static unsigned long __init 261 calibrate_cc_with_pit(void) 262 { 263 int cc, count = 0; 264 265 /* Set the Gate high, disable speaker */ 266 outb((inb(0x61) & ~0x02) | 0x01, 0x61); 267 268 /* 269 * Now let's take care of CTC channel 2 270 * 271 * Set the Gate high, program CTC channel 2 for mode 0, 272 * (interrupt on terminal count mode), binary count, 273 * load 5 * LATCH count, (LSB and MSB) to begin countdown. 274 */ 275 outb(0xb0, 0x43); /* binary, mode 0, LSB/MSB, Ch 2 */ 276 outb(CALIBRATE_LATCH & 0xff, 0x42); /* LSB of count */ 277 outb(CALIBRATE_LATCH >> 8, 0x42); /* MSB of count */ 278 279 cc = rpcc(); 280 do { 281 count++; 282 } while ((inb(0x61) & 0x20) == 0 && count < TIMEOUT_COUNT); 283 cc = rpcc() - cc; 284 285 /* Error: ECTCNEVERSET or ECPUTOOFAST. */ 286 if (count <= 1 || count == TIMEOUT_COUNT) 287 return 0; 288 289 return ((long)cc * PIT_TICK_RATE) / (CALIBRATE_LATCH + 1); 290 } 291 292 /* The Linux interpretation of the CMOS clock register contents: 293 When the Update-In-Progress (UIP) flag goes from 1 to 0, the 294 RTC registers show the second which has precisely just started. 295 Let's hope other operating systems interpret the RTC the same way. */ 296 297 static unsigned long __init 298 rpcc_after_update_in_progress(void) 299 { 300 do { } while (!(CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP)); 301 do { } while (CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP); 302 303 return rpcc(); 304 } 305 306 void __init 307 time_init(void) 308 { 309 unsigned int year, mon, day, hour, min, sec, cc1, cc2, epoch; 310 unsigned long cycle_freq, tolerance; 311 long diff; 312 313 /* Calibrate CPU clock -- attempt #1. */ 314 if (!est_cycle_freq) 315 est_cycle_freq = validate_cc_value(calibrate_cc_with_pit()); 316 317 cc1 = rpcc(); 318 319 /* Calibrate CPU clock -- attempt #2. */ 320 if (!est_cycle_freq) { 321 cc1 = rpcc_after_update_in_progress(); 322 cc2 = rpcc_after_update_in_progress(); 323 est_cycle_freq = validate_cc_value(cc2 - cc1); 324 cc1 = cc2; 325 } 326 327 cycle_freq = hwrpb->cycle_freq; 328 if (est_cycle_freq) { 329 /* If the given value is within 250 PPM of what we calculated, 330 accept it. Otherwise, use what we found. */ 331 tolerance = cycle_freq / 4000; 332 diff = cycle_freq - est_cycle_freq; 333 if (diff < 0) 334 diff = -diff; 335 if ((unsigned long)diff > tolerance) { 336 cycle_freq = est_cycle_freq; 337 printk("HWRPB cycle frequency bogus. " 338 "Estimated %lu Hz\n", cycle_freq); 339 } else { 340 est_cycle_freq = 0; 341 } 342 } else if (! validate_cc_value (cycle_freq)) { 343 printk("HWRPB cycle frequency bogus, " 344 "and unable to estimate a proper value!\n"); 345 } 346 347 /* From John Bowman <bowman@math.ualberta.ca>: allow the values 348 to settle, as the Update-In-Progress bit going low isn't good 349 enough on some hardware. 2ms is our guess; we haven't found 350 bogomips yet, but this is close on a 500Mhz box. */ 351 __delay(1000000); 352 353 sec = CMOS_READ(RTC_SECONDS); 354 min = CMOS_READ(RTC_MINUTES); 355 hour = CMOS_READ(RTC_HOURS); 356 day = CMOS_READ(RTC_DAY_OF_MONTH); 357 mon = CMOS_READ(RTC_MONTH); 358 year = CMOS_READ(RTC_YEAR); 359 360 if (!(CMOS_READ(RTC_CONTROL) & RTC_DM_BINARY) || RTC_ALWAYS_BCD) { 361 BCD_TO_BIN(sec); 362 BCD_TO_BIN(min); 363 BCD_TO_BIN(hour); 364 BCD_TO_BIN(day); 365 BCD_TO_BIN(mon); 366 BCD_TO_BIN(year); 367 } 368 369 /* PC-like is standard; used for year >= 70 */ 370 epoch = 1900; 371 if (year < 20) 372 epoch = 2000; 373 else if (year >= 20 && year < 48) 374 /* NT epoch */ 375 epoch = 1980; 376 else if (year >= 48 && year < 70) 377 /* Digital UNIX epoch */ 378 epoch = 1952; 379 380 printk(KERN_INFO "Using epoch = %d\n", epoch); 381 382 if ((year += epoch) < 1970) 383 year += 100; 384 385 xtime.tv_sec = mktime(year, mon, day, hour, min, sec); 386 xtime.tv_nsec = 0; 387 388 wall_to_monotonic.tv_sec -= xtime.tv_sec; 389 wall_to_monotonic.tv_nsec = 0; 390 391 if (HZ > (1<<16)) { 392 extern void __you_loose (void); 393 __you_loose(); 394 } 395 396 state.last_time = cc1; 397 state.scaled_ticks_per_cycle 398 = ((unsigned long) HZ << FIX_SHIFT) / cycle_freq; 399 state.last_rtc_update = 0; 400 state.partial_tick = 0L; 401 402 /* Startup the timer source. */ 403 alpha_mv.init_rtc(); 404 } 405 406 /* 407 * Use the cycle counter to estimate an displacement from the last time 408 * tick. Unfortunately the Alpha designers made only the low 32-bits of 409 * the cycle counter active, so we overflow on 8.2 seconds on a 500MHz 410 * part. So we can't do the "find absolute time in terms of cycles" thing 411 * that the other ports do. 412 */ 413 void 414 do_gettimeofday(struct timeval *tv) 415 { 416 unsigned long flags; 417 unsigned long sec, usec, lost, seq; 418 unsigned long delta_cycles, delta_usec, partial_tick; 419 420 do { 421 seq = read_seqbegin_irqsave(&xtime_lock, flags); 422 423 delta_cycles = rpcc() - state.last_time; 424 sec = xtime.tv_sec; 425 usec = (xtime.tv_nsec / 1000); 426 partial_tick = state.partial_tick; 427 lost = jiffies - wall_jiffies; 428 429 } while (read_seqretry_irqrestore(&xtime_lock, seq, flags)); 430 431 #ifdef CONFIG_SMP 432 /* Until and unless we figure out how to get cpu cycle counters 433 in sync and keep them there, we can't use the rpcc tricks. */ 434 delta_usec = lost * (1000000 / HZ); 435 #else 436 /* 437 * usec = cycles * ticks_per_cycle * 2**48 * 1e6 / (2**48 * ticks) 438 * = cycles * (s_t_p_c) * 1e6 / (2**48 * ticks) 439 * = cycles * (s_t_p_c) * 15625 / (2**42 * ticks) 440 * 441 * which, given a 600MHz cycle and a 1024Hz tick, has a 442 * dynamic range of about 1.7e17, which is less than the 443 * 1.8e19 in an unsigned long, so we are safe from overflow. 444 * 445 * Round, but with .5 up always, since .5 to even is harder 446 * with no clear gain. 447 */ 448 449 delta_usec = (delta_cycles * state.scaled_ticks_per_cycle 450 + partial_tick 451 + (lost << FIX_SHIFT)) * 15625; 452 delta_usec = ((delta_usec / ((1UL << (FIX_SHIFT-6-1)) * HZ)) + 1) / 2; 453 #endif 454 455 usec += delta_usec; 456 if (usec >= 1000000) { 457 sec += 1; 458 usec -= 1000000; 459 } 460 461 tv->tv_sec = sec; 462 tv->tv_usec = usec; 463 } 464 465 EXPORT_SYMBOL(do_gettimeofday); 466 467 int 468 do_settimeofday(struct timespec *tv) 469 { 470 time_t wtm_sec, sec = tv->tv_sec; 471 long wtm_nsec, nsec = tv->tv_nsec; 472 unsigned long delta_nsec; 473 474 if ((unsigned long)tv->tv_nsec >= NSEC_PER_SEC) 475 return -EINVAL; 476 477 write_seqlock_irq(&xtime_lock); 478 479 /* The offset that is added into time in do_gettimeofday above 480 must be subtracted out here to keep a coherent view of the 481 time. Without this, a full-tick error is possible. */ 482 483 #ifdef CONFIG_SMP 484 delta_nsec = (jiffies - wall_jiffies) * (NSEC_PER_SEC / HZ); 485 #else 486 delta_nsec = rpcc() - state.last_time; 487 delta_nsec = (delta_nsec * state.scaled_ticks_per_cycle 488 + state.partial_tick 489 + ((jiffies - wall_jiffies) << FIX_SHIFT)) * 15625; 490 delta_nsec = ((delta_nsec / ((1UL << (FIX_SHIFT-6-1)) * HZ)) + 1) / 2; 491 delta_nsec *= 1000; 492 #endif 493 494 nsec -= delta_nsec; 495 496 wtm_sec = wall_to_monotonic.tv_sec + (xtime.tv_sec - sec); 497 wtm_nsec = wall_to_monotonic.tv_nsec + (xtime.tv_nsec - nsec); 498 499 set_normalized_timespec(&xtime, sec, nsec); 500 set_normalized_timespec(&wall_to_monotonic, wtm_sec, wtm_nsec); 501 502 ntp_clear(); 503 504 write_sequnlock_irq(&xtime_lock); 505 clock_was_set(); 506 return 0; 507 } 508 509 EXPORT_SYMBOL(do_settimeofday); 510 511 512 /* 513 * In order to set the CMOS clock precisely, set_rtc_mmss has to be 514 * called 500 ms after the second nowtime has started, because when 515 * nowtime is written into the registers of the CMOS clock, it will 516 * jump to the next second precisely 500 ms later. Check the Motorola 517 * MC146818A or Dallas DS12887 data sheet for details. 518 * 519 * BUG: This routine does not handle hour overflow properly; it just 520 * sets the minutes. Usually you won't notice until after reboot! 521 */ 522 523 524 static int 525 set_rtc_mmss(unsigned long nowtime) 526 { 527 int retval = 0; 528 int real_seconds, real_minutes, cmos_minutes; 529 unsigned char save_control, save_freq_select; 530 531 /* irq are locally disabled here */ 532 spin_lock(&rtc_lock); 533 /* Tell the clock it's being set */ 534 save_control = CMOS_READ(RTC_CONTROL); 535 CMOS_WRITE((save_control|RTC_SET), RTC_CONTROL); 536 537 /* Stop and reset prescaler */ 538 save_freq_select = CMOS_READ(RTC_FREQ_SELECT); 539 CMOS_WRITE((save_freq_select|RTC_DIV_RESET2), RTC_FREQ_SELECT); 540 541 cmos_minutes = CMOS_READ(RTC_MINUTES); 542 if (!(save_control & RTC_DM_BINARY) || RTC_ALWAYS_BCD) 543 BCD_TO_BIN(cmos_minutes); 544 545 /* 546 * since we're only adjusting minutes and seconds, 547 * don't interfere with hour overflow. This avoids 548 * messing with unknown time zones but requires your 549 * RTC not to be off by more than 15 minutes 550 */ 551 real_seconds = nowtime % 60; 552 real_minutes = nowtime / 60; 553 if (((abs(real_minutes - cmos_minutes) + 15)/30) & 1) { 554 /* correct for half hour time zone */ 555 real_minutes += 30; 556 } 557 real_minutes %= 60; 558 559 if (abs(real_minutes - cmos_minutes) < 30) { 560 if (!(save_control & RTC_DM_BINARY) || RTC_ALWAYS_BCD) { 561 BIN_TO_BCD(real_seconds); 562 BIN_TO_BCD(real_minutes); 563 } 564 CMOS_WRITE(real_seconds,RTC_SECONDS); 565 CMOS_WRITE(real_minutes,RTC_MINUTES); 566 } else { 567 printk(KERN_WARNING 568 "set_rtc_mmss: can't update from %d to %d\n", 569 cmos_minutes, real_minutes); 570 retval = -1; 571 } 572 573 /* The following flags have to be released exactly in this order, 574 * otherwise the DS12887 (popular MC146818A clone with integrated 575 * battery and quartz) will not reset the oscillator and will not 576 * update precisely 500 ms later. You won't find this mentioned in 577 * the Dallas Semiconductor data sheets, but who believes data 578 * sheets anyway ... -- Markus Kuhn 579 */ 580 CMOS_WRITE(save_control, RTC_CONTROL); 581 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT); 582 spin_unlock(&rtc_lock); 583 584 return retval; 585 } 586