xref: /linux/arch/alpha/kernel/time.c (revision 979f867191f80e74713394cf8c0a3c1b3662b648) 
1 /*
2  *  linux/arch/alpha/kernel/time.c
3  *
4  *  Copyright (C) 1991, 1992, 1995, 1999, 2000  Linus Torvalds
5  *
6  * This file contains the PC-specific time handling details:
7  * reading the RTC at bootup, etc..
8  * 1994-07-02    Alan Modra
9  *	fixed set_rtc_mmss, fixed time.year for >= 2000, new mktime
10  * 1995-03-26    Markus Kuhn
11  *      fixed 500 ms bug at call to set_rtc_mmss, fixed DS12887
12  *      precision CMOS clock update
13  * 1997-09-10	Updated NTP code according to technical memorandum Jan '96
14  *		"A Kernel Model for Precision Timekeeping" by Dave Mills
15  * 1997-01-09    Adrian Sun
16  *      use interval timer if CONFIG_RTC=y
17  * 1997-10-29    John Bowman (bowman@math.ualberta.ca)
18  *      fixed tick loss calculation in timer_interrupt
19  *      (round system clock to nearest tick instead of truncating)
20  *      fixed algorithm in time_init for getting time from CMOS clock
21  * 1999-04-16	Thorsten Kranzkowski (dl8bcu@gmx.net)
22  *	fixed algorithm in do_gettimeofday() for calculating the precise time
23  *	from processor cycle counter (now taking lost_ticks into account)
24  * 2000-08-13	Jan-Benedict Glaw <jbglaw@lug-owl.de>
25  * 	Fixed time_init to be aware of epoches != 1900. This prevents
26  * 	booting up in 2048 for me;) Code is stolen from rtc.c.
27  * 2003-06-03	R. Scott Bailey <scott.bailey@eds.com>
28  *	Tighten sanity in time_init from 1% (10,000 PPM) to 250 PPM
29  */
30 #include <linux/errno.h>
31 #include <linux/module.h>
32 #include <linux/sched.h>
33 #include <linux/kernel.h>
34 #include <linux/param.h>
35 #include <linux/string.h>
36 #include <linux/mm.h>
37 #include <linux/delay.h>
38 #include <linux/ioport.h>
39 #include <linux/irq.h>
40 #include <linux/interrupt.h>
41 #include <linux/init.h>
42 #include <linux/bcd.h>
43 #include <linux/profile.h>
44 #include <linux/perf_event.h>
45 
46 #include <asm/uaccess.h>
47 #include <asm/io.h>
48 #include <asm/hwrpb.h>
49 #include <asm/8253pit.h>
50 #include <asm/rtc.h>
51 
52 #include <linux/mc146818rtc.h>
53 #include <linux/time.h>
54 #include <linux/timex.h>
55 #include <linux/clocksource.h>
56 
57 #include "proto.h"
58 #include "irq_impl.h"
59 
60 static int set_rtc_mmss(unsigned long);
61 
62 DEFINE_SPINLOCK(rtc_lock);
63 EXPORT_SYMBOL(rtc_lock);
64 
65 #define TICK_SIZE (tick_nsec / 1000)
66 
67 /*
68  * Shift amount by which scaled_ticks_per_cycle is scaled.  Shifting
69  * by 48 gives us 16 bits for HZ while keeping the accuracy good even
70  * for large CPU clock rates.
71  */
72 #define FIX_SHIFT	48
73 
74 /* lump static variables together for more efficient access: */
75 static struct {
76 	/* cycle counter last time it got invoked */
77 	__u32 last_time;
78 	/* ticks/cycle * 2^48 */
79 	unsigned long scaled_ticks_per_cycle;
80 	/* partial unused tick */
81 	unsigned long partial_tick;
82 } state;
83 
84 unsigned long est_cycle_freq;
85 
86 #ifdef CONFIG_PERF_EVENTS
87 
88 DEFINE_PER_CPU(u8, perf_event_pending);
89 
90 #define set_perf_event_pending_flag()  __get_cpu_var(perf_event_pending) = 1
91 #define test_perf_event_pending()      __get_cpu_var(perf_event_pending)
92 #define clear_perf_event_pending()     __get_cpu_var(perf_event_pending) = 0
93 
94 void set_perf_event_pending(void)
95 {
96 	set_perf_event_pending_flag();
97 }
98 
99 #else  /* CONFIG_PERF_EVENTS */
100 
101 #define test_perf_event_pending()      0
102 #define clear_perf_event_pending()
103 
104 #endif /* CONFIG_PERF_EVENTS */
105 
106 
107 static inline __u32 rpcc(void)
108 {
109     __u32 result;
110     asm volatile ("rpcc %0" : "=r"(result));
111     return result;
112 }
113 
114 int update_persistent_clock(struct timespec now)
115 {
116 	return set_rtc_mmss(now.tv_sec);
117 }
118 
119 void read_persistent_clock(struct timespec *ts)
120 {
121 	unsigned int year, mon, day, hour, min, sec, epoch;
122 
123 	sec = CMOS_READ(RTC_SECONDS);
124 	min = CMOS_READ(RTC_MINUTES);
125 	hour = CMOS_READ(RTC_HOURS);
126 	day = CMOS_READ(RTC_DAY_OF_MONTH);
127 	mon = CMOS_READ(RTC_MONTH);
128 	year = CMOS_READ(RTC_YEAR);
129 
130 	if (!(CMOS_READ(RTC_CONTROL) & RTC_DM_BINARY) || RTC_ALWAYS_BCD) {
131 		sec = bcd2bin(sec);
132 		min = bcd2bin(min);
133 		hour = bcd2bin(hour);
134 		day = bcd2bin(day);
135 		mon = bcd2bin(mon);
136 		year = bcd2bin(year);
137 	}
138 
139 	/* PC-like is standard; used for year >= 70 */
140 	epoch = 1900;
141 	if (year < 20)
142 		epoch = 2000;
143 	else if (year >= 20 && year < 48)
144 		/* NT epoch */
145 		epoch = 1980;
146 	else if (year >= 48 && year < 70)
147 		/* Digital UNIX epoch */
148 		epoch = 1952;
149 
150 	printk(KERN_INFO "Using epoch = %d\n", epoch);
151 
152 	if ((year += epoch) < 1970)
153 		year += 100;
154 
155 	ts->tv_sec = mktime(year, mon, day, hour, min, sec);
156 }
157 
158 
159 
160 /*
161  * timer_interrupt() needs to keep up the real-time clock,
162  * as well as call the "do_timer()" routine every clocktick
163  */
164 irqreturn_t timer_interrupt(int irq, void *dev)
165 {
166 	unsigned long delta;
167 	__u32 now;
168 	long nticks;
169 
170 #ifndef CONFIG_SMP
171 	/* Not SMP, do kernel PC profiling here.  */
172 	profile_tick(CPU_PROFILING);
173 #endif
174 
175 	write_seqlock(&xtime_lock);
176 
177 	/*
178 	 * Calculate how many ticks have passed since the last update,
179 	 * including any previous partial leftover.  Save any resulting
180 	 * fraction for the next pass.
181 	 */
182 	now = rpcc();
183 	delta = now - state.last_time;
184 	state.last_time = now;
185 	delta = delta * state.scaled_ticks_per_cycle + state.partial_tick;
186 	state.partial_tick = delta & ((1UL << FIX_SHIFT) - 1);
187 	nticks = delta >> FIX_SHIFT;
188 
189 	if (nticks)
190 		do_timer(nticks);
191 
192 	write_sequnlock(&xtime_lock);
193 
194 #ifndef CONFIG_SMP
195 	while (nticks--)
196 		update_process_times(user_mode(get_irq_regs()));
197 #endif
198 
199 	if (test_perf_event_pending()) {
200 		clear_perf_event_pending();
201 		perf_event_do_pending();
202 	}
203 
204 	return IRQ_HANDLED;
205 }
206 
207 void __init
208 common_init_rtc(void)
209 {
210 	unsigned char x;
211 
212 	/* Reset periodic interrupt frequency.  */
213 	x = CMOS_READ(RTC_FREQ_SELECT) & 0x3f;
214         /* Test includes known working values on various platforms
215            where 0x26 is wrong; we refuse to change those. */
216 	if (x != 0x26 && x != 0x25 && x != 0x19 && x != 0x06) {
217 		printk("Setting RTC_FREQ to 1024 Hz (%x)\n", x);
218 		CMOS_WRITE(0x26, RTC_FREQ_SELECT);
219 	}
220 
221 	/* Turn on periodic interrupts.  */
222 	x = CMOS_READ(RTC_CONTROL);
223 	if (!(x & RTC_PIE)) {
224 		printk("Turning on RTC interrupts.\n");
225 		x |= RTC_PIE;
226 		x &= ~(RTC_AIE | RTC_UIE);
227 		CMOS_WRITE(x, RTC_CONTROL);
228 	}
229 	(void) CMOS_READ(RTC_INTR_FLAGS);
230 
231 	outb(0x36, 0x43);	/* pit counter 0: system timer */
232 	outb(0x00, 0x40);
233 	outb(0x00, 0x40);
234 
235 	outb(0xb6, 0x43);	/* pit counter 2: speaker */
236 	outb(0x31, 0x42);
237 	outb(0x13, 0x42);
238 
239 	init_rtc_irq();
240 }
241 
242 unsigned int common_get_rtc_time(struct rtc_time *time)
243 {
244 	return __get_rtc_time(time);
245 }
246 
247 int common_set_rtc_time(struct rtc_time *time)
248 {
249 	return __set_rtc_time(time);
250 }
251 
252 /* Validate a computed cycle counter result against the known bounds for
253    the given processor core.  There's too much brokenness in the way of
254    timing hardware for any one method to work everywhere.  :-(
255 
256    Return 0 if the result cannot be trusted, otherwise return the argument.  */
257 
258 static unsigned long __init
259 validate_cc_value(unsigned long cc)
260 {
261 	static struct bounds {
262 		unsigned int min, max;
263 	} cpu_hz[] __initdata = {
264 		[EV3_CPU]    = {   50000000,  200000000 },	/* guess */
265 		[EV4_CPU]    = {  100000000,  300000000 },
266 		[LCA4_CPU]   = {  100000000,  300000000 },	/* guess */
267 		[EV45_CPU]   = {  200000000,  300000000 },
268 		[EV5_CPU]    = {  250000000,  433000000 },
269 		[EV56_CPU]   = {  333000000,  667000000 },
270 		[PCA56_CPU]  = {  400000000,  600000000 },	/* guess */
271 		[PCA57_CPU]  = {  500000000,  600000000 },	/* guess */
272 		[EV6_CPU]    = {  466000000,  600000000 },
273 		[EV67_CPU]   = {  600000000,  750000000 },
274 		[EV68AL_CPU] = {  750000000,  940000000 },
275 		[EV68CB_CPU] = { 1000000000, 1333333333 },
276 		/* None of the following are shipping as of 2001-11-01.  */
277 		[EV68CX_CPU] = { 1000000000, 1700000000 },	/* guess */
278 		[EV69_CPU]   = { 1000000000, 1700000000 },	/* guess */
279 		[EV7_CPU]    = {  800000000, 1400000000 },	/* guess */
280 		[EV79_CPU]   = { 1000000000, 2000000000 },	/* guess */
281 	};
282 
283 	/* Allow for some drift in the crystal.  10MHz is more than enough.  */
284 	const unsigned int deviation = 10000000;
285 
286 	struct percpu_struct *cpu;
287 	unsigned int index;
288 
289 	cpu = (struct percpu_struct *)((char*)hwrpb + hwrpb->processor_offset);
290 	index = cpu->type & 0xffffffff;
291 
292 	/* If index out of bounds, no way to validate.  */
293 	if (index >= ARRAY_SIZE(cpu_hz))
294 		return cc;
295 
296 	/* If index contains no data, no way to validate.  */
297 	if (cpu_hz[index].max == 0)
298 		return cc;
299 
300 	if (cc < cpu_hz[index].min - deviation
301 	    || cc > cpu_hz[index].max + deviation)
302 		return 0;
303 
304 	return cc;
305 }
306 
307 
308 /*
309  * Calibrate CPU clock using legacy 8254 timer/counter. Stolen from
310  * arch/i386/time.c.
311  */
312 
313 #define CALIBRATE_LATCH	0xffff
314 #define TIMEOUT_COUNT	0x100000
315 
316 static unsigned long __init
317 calibrate_cc_with_pit(void)
318 {
319 	int cc, count = 0;
320 
321 	/* Set the Gate high, disable speaker */
322 	outb((inb(0x61) & ~0x02) | 0x01, 0x61);
323 
324 	/*
325 	 * Now let's take care of CTC channel 2
326 	 *
327 	 * Set the Gate high, program CTC channel 2 for mode 0,
328 	 * (interrupt on terminal count mode), binary count,
329 	 * load 5 * LATCH count, (LSB and MSB) to begin countdown.
330 	 */
331 	outb(0xb0, 0x43);		/* binary, mode 0, LSB/MSB, Ch 2 */
332 	outb(CALIBRATE_LATCH & 0xff, 0x42);	/* LSB of count */
333 	outb(CALIBRATE_LATCH >> 8, 0x42);	/* MSB of count */
334 
335 	cc = rpcc();
336 	do {
337 		count++;
338 	} while ((inb(0x61) & 0x20) == 0 && count < TIMEOUT_COUNT);
339 	cc = rpcc() - cc;
340 
341 	/* Error: ECTCNEVERSET or ECPUTOOFAST.  */
342 	if (count <= 1 || count == TIMEOUT_COUNT)
343 		return 0;
344 
345 	return ((long)cc * PIT_TICK_RATE) / (CALIBRATE_LATCH + 1);
346 }
347 
348 /* The Linux interpretation of the CMOS clock register contents:
349    When the Update-In-Progress (UIP) flag goes from 1 to 0, the
350    RTC registers show the second which has precisely just started.
351    Let's hope other operating systems interpret the RTC the same way.  */
352 
353 static unsigned long __init
354 rpcc_after_update_in_progress(void)
355 {
356 	do { } while (!(CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP));
357 	do { } while (CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP);
358 
359 	return rpcc();
360 }
361 
362 #ifndef CONFIG_SMP
363 /* Until and unless we figure out how to get cpu cycle counters
364    in sync and keep them there, we can't use the rpcc.  */
365 static cycle_t read_rpcc(struct clocksource *cs)
366 {
367 	cycle_t ret = (cycle_t)rpcc();
368 	return ret;
369 }
370 
371 static struct clocksource clocksource_rpcc = {
372 	.name                   = "rpcc",
373 	.rating                 = 300,
374 	.read                   = read_rpcc,
375 	.mask                   = CLOCKSOURCE_MASK(32),
376 	.flags                  = CLOCK_SOURCE_IS_CONTINUOUS
377 };
378 
379 static inline void register_rpcc_clocksource(long cycle_freq)
380 {
381 	clocksource_calc_mult_shift(&clocksource_rpcc, cycle_freq, 4);
382 	clocksource_register(&clocksource_rpcc);
383 }
384 #else /* !CONFIG_SMP */
385 static inline void register_rpcc_clocksource(long cycle_freq)
386 {
387 }
388 #endif /* !CONFIG_SMP */
389 
390 void __init
391 time_init(void)
392 {
393 	unsigned int cc1, cc2;
394 	unsigned long cycle_freq, tolerance;
395 	long diff;
396 
397 	/* Calibrate CPU clock -- attempt #1.  */
398 	if (!est_cycle_freq)
399 		est_cycle_freq = validate_cc_value(calibrate_cc_with_pit());
400 
401 	cc1 = rpcc();
402 
403 	/* Calibrate CPU clock -- attempt #2.  */
404 	if (!est_cycle_freq) {
405 		cc1 = rpcc_after_update_in_progress();
406 		cc2 = rpcc_after_update_in_progress();
407 		est_cycle_freq = validate_cc_value(cc2 - cc1);
408 		cc1 = cc2;
409 	}
410 
411 	cycle_freq = hwrpb->cycle_freq;
412 	if (est_cycle_freq) {
413 		/* If the given value is within 250 PPM of what we calculated,
414 		   accept it.  Otherwise, use what we found.  */
415 		tolerance = cycle_freq / 4000;
416 		diff = cycle_freq - est_cycle_freq;
417 		if (diff < 0)
418 			diff = -diff;
419 		if ((unsigned long)diff > tolerance) {
420 			cycle_freq = est_cycle_freq;
421 			printk("HWRPB cycle frequency bogus.  "
422 			       "Estimated %lu Hz\n", cycle_freq);
423 		} else {
424 			est_cycle_freq = 0;
425 		}
426 	} else if (! validate_cc_value (cycle_freq)) {
427 		printk("HWRPB cycle frequency bogus, "
428 		       "and unable to estimate a proper value!\n");
429 	}
430 
431 	/* From John Bowman <bowman@math.ualberta.ca>: allow the values
432 	   to settle, as the Update-In-Progress bit going low isn't good
433 	   enough on some hardware.  2ms is our guess; we haven't found
434 	   bogomips yet, but this is close on a 500Mhz box.  */
435 	__delay(1000000);
436 
437 
438 	if (HZ > (1<<16)) {
439 		extern void __you_loose (void);
440 		__you_loose();
441 	}
442 
443 	register_rpcc_clocksource(cycle_freq);
444 
445 	state.last_time = cc1;
446 	state.scaled_ticks_per_cycle
447 		= ((unsigned long) HZ << FIX_SHIFT) / cycle_freq;
448 	state.partial_tick = 0L;
449 
450 	/* Startup the timer source. */
451 	alpha_mv.init_rtc();
452 }
453 
454 /*
455  * In order to set the CMOS clock precisely, set_rtc_mmss has to be
456  * called 500 ms after the second nowtime has started, because when
457  * nowtime is written into the registers of the CMOS clock, it will
458  * jump to the next second precisely 500 ms later. Check the Motorola
459  * MC146818A or Dallas DS12887 data sheet for details.
460  *
461  * BUG: This routine does not handle hour overflow properly; it just
462  *      sets the minutes. Usually you won't notice until after reboot!
463  */
464 
465 
466 static int
467 set_rtc_mmss(unsigned long nowtime)
468 {
469 	int retval = 0;
470 	int real_seconds, real_minutes, cmos_minutes;
471 	unsigned char save_control, save_freq_select;
472 
473 	/* irq are locally disabled here */
474 	spin_lock(&rtc_lock);
475 	/* Tell the clock it's being set */
476 	save_control = CMOS_READ(RTC_CONTROL);
477 	CMOS_WRITE((save_control|RTC_SET), RTC_CONTROL);
478 
479 	/* Stop and reset prescaler */
480 	save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
481 	CMOS_WRITE((save_freq_select|RTC_DIV_RESET2), RTC_FREQ_SELECT);
482 
483 	cmos_minutes = CMOS_READ(RTC_MINUTES);
484 	if (!(save_control & RTC_DM_BINARY) || RTC_ALWAYS_BCD)
485 		cmos_minutes = bcd2bin(cmos_minutes);
486 
487 	/*
488 	 * since we're only adjusting minutes and seconds,
489 	 * don't interfere with hour overflow. This avoids
490 	 * messing with unknown time zones but requires your
491 	 * RTC not to be off by more than 15 minutes
492 	 */
493 	real_seconds = nowtime % 60;
494 	real_minutes = nowtime / 60;
495 	if (((abs(real_minutes - cmos_minutes) + 15)/30) & 1) {
496 		/* correct for half hour time zone */
497 		real_minutes += 30;
498 	}
499 	real_minutes %= 60;
500 
501 	if (abs(real_minutes - cmos_minutes) < 30) {
502 		if (!(save_control & RTC_DM_BINARY) || RTC_ALWAYS_BCD) {
503 			real_seconds = bin2bcd(real_seconds);
504 			real_minutes = bin2bcd(real_minutes);
505 		}
506 		CMOS_WRITE(real_seconds,RTC_SECONDS);
507 		CMOS_WRITE(real_minutes,RTC_MINUTES);
508 	} else {
509 		printk(KERN_WARNING
510 		       "set_rtc_mmss: can't update from %d to %d\n",
511 		       cmos_minutes, real_minutes);
512  		retval = -1;
513 	}
514 
515 	/* The following flags have to be released exactly in this order,
516 	 * otherwise the DS12887 (popular MC146818A clone with integrated
517 	 * battery and quartz) will not reset the oscillator and will not
518 	 * update precisely 500 ms later. You won't find this mentioned in
519 	 * the Dallas Semiconductor data sheets, but who believes data
520 	 * sheets anyway ...                           -- Markus Kuhn
521 	 */
522 	CMOS_WRITE(save_control, RTC_CONTROL);
523 	CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
524 	spin_unlock(&rtc_lock);
525 
526 	return retval;
527 }
528