xref: /linux/arch/alpha/kernel/time.c (revision 11e4afb49b7fa1fc8e1ffd850c1806dd86a08204) 
1 /*
2  *  linux/arch/alpha/kernel/time.c
3  *
4  *  Copyright (C) 1991, 1992, 1995, 1999, 2000  Linus Torvalds
5  *
6  * This file contains the PC-specific time handling details:
7  * reading the RTC at bootup, etc..
8  * 1994-07-02    Alan Modra
9  *	fixed set_rtc_mmss, fixed time.year for >= 2000, new mktime
10  * 1995-03-26    Markus Kuhn
11  *      fixed 500 ms bug at call to set_rtc_mmss, fixed DS12887
12  *      precision CMOS clock update
13  * 1997-09-10	Updated NTP code according to technical memorandum Jan '96
14  *		"A Kernel Model for Precision Timekeeping" by Dave Mills
15  * 1997-01-09    Adrian Sun
16  *      use interval timer if CONFIG_RTC=y
17  * 1997-10-29    John Bowman (bowman@math.ualberta.ca)
18  *      fixed tick loss calculation in timer_interrupt
19  *      (round system clock to nearest tick instead of truncating)
20  *      fixed algorithm in time_init for getting time from CMOS clock
21  * 1999-04-16	Thorsten Kranzkowski (dl8bcu@gmx.net)
22  *	fixed algorithm in do_gettimeofday() for calculating the precise time
23  *	from processor cycle counter (now taking lost_ticks into account)
24  * 2000-08-13	Jan-Benedict Glaw <jbglaw@lug-owl.de>
25  * 	Fixed time_init to be aware of epoches != 1900. This prevents
26  * 	booting up in 2048 for me;) Code is stolen from rtc.c.
27  * 2003-06-03	R. Scott Bailey <scott.bailey@eds.com>
28  *	Tighten sanity in time_init from 1% (10,000 PPM) to 250 PPM
29  */
30 #include <linux/errno.h>
31 #include <linux/module.h>
32 #include <linux/sched.h>
33 #include <linux/kernel.h>
34 #include <linux/param.h>
35 #include <linux/string.h>
36 #include <linux/mm.h>
37 #include <linux/delay.h>
38 #include <linux/ioport.h>
39 #include <linux/irq.h>
40 #include <linux/interrupt.h>
41 #include <linux/init.h>
42 #include <linux/bcd.h>
43 #include <linux/profile.h>
44 
45 #include <asm/uaccess.h>
46 #include <asm/io.h>
47 #include <asm/hwrpb.h>
48 #include <asm/8253pit.h>
49 #include <asm/rtc.h>
50 
51 #include <linux/mc146818rtc.h>
52 #include <linux/time.h>
53 #include <linux/timex.h>
54 #include <linux/clocksource.h>
55 
56 #include "proto.h"
57 #include "irq_impl.h"
58 
59 static int set_rtc_mmss(unsigned long);
60 
61 DEFINE_SPINLOCK(rtc_lock);
62 EXPORT_SYMBOL(rtc_lock);
63 
64 #define TICK_SIZE (tick_nsec / 1000)
65 
66 /*
67  * Shift amount by which scaled_ticks_per_cycle is scaled.  Shifting
68  * by 48 gives us 16 bits for HZ while keeping the accuracy good even
69  * for large CPU clock rates.
70  */
71 #define FIX_SHIFT	48
72 
73 /* lump static variables together for more efficient access: */
74 static struct {
75 	/* cycle counter last time it got invoked */
76 	__u32 last_time;
77 	/* ticks/cycle * 2^48 */
78 	unsigned long scaled_ticks_per_cycle;
79 	/* partial unused tick */
80 	unsigned long partial_tick;
81 } state;
82 
83 unsigned long est_cycle_freq;
84 
85 
86 static inline __u32 rpcc(void)
87 {
88     __u32 result;
89     asm volatile ("rpcc %0" : "=r"(result));
90     return result;
91 }
92 
93 int update_persistent_clock(struct timespec now)
94 {
95 	return set_rtc_mmss(now.tv_sec);
96 }
97 
98 void read_persistent_clock(struct timespec *ts)
99 {
100 	unsigned int year, mon, day, hour, min, sec, epoch;
101 
102 	sec = CMOS_READ(RTC_SECONDS);
103 	min = CMOS_READ(RTC_MINUTES);
104 	hour = CMOS_READ(RTC_HOURS);
105 	day = CMOS_READ(RTC_DAY_OF_MONTH);
106 	mon = CMOS_READ(RTC_MONTH);
107 	year = CMOS_READ(RTC_YEAR);
108 
109 	if (!(CMOS_READ(RTC_CONTROL) & RTC_DM_BINARY) || RTC_ALWAYS_BCD) {
110 		sec = bcd2bin(sec);
111 		min = bcd2bin(min);
112 		hour = bcd2bin(hour);
113 		day = bcd2bin(day);
114 		mon = bcd2bin(mon);
115 		year = bcd2bin(year);
116 	}
117 
118 	/* PC-like is standard; used for year >= 70 */
119 	epoch = 1900;
120 	if (year < 20)
121 		epoch = 2000;
122 	else if (year >= 20 && year < 48)
123 		/* NT epoch */
124 		epoch = 1980;
125 	else if (year >= 48 && year < 70)
126 		/* Digital UNIX epoch */
127 		epoch = 1952;
128 
129 	printk(KERN_INFO "Using epoch = %d\n", epoch);
130 
131 	if ((year += epoch) < 1970)
132 		year += 100;
133 
134 	ts->tv_sec = mktime(year, mon, day, hour, min, sec);
135 }
136 
137 
138 
139 /*
140  * timer_interrupt() needs to keep up the real-time clock,
141  * as well as call the "do_timer()" routine every clocktick
142  */
143 irqreturn_t timer_interrupt(int irq, void *dev)
144 {
145 	unsigned long delta;
146 	__u32 now;
147 	long nticks;
148 
149 #ifndef CONFIG_SMP
150 	/* Not SMP, do kernel PC profiling here.  */
151 	profile_tick(CPU_PROFILING);
152 #endif
153 
154 	write_seqlock(&xtime_lock);
155 
156 	/*
157 	 * Calculate how many ticks have passed since the last update,
158 	 * including any previous partial leftover.  Save any resulting
159 	 * fraction for the next pass.
160 	 */
161 	now = rpcc();
162 	delta = now - state.last_time;
163 	state.last_time = now;
164 	delta = delta * state.scaled_ticks_per_cycle + state.partial_tick;
165 	state.partial_tick = delta & ((1UL << FIX_SHIFT) - 1);
166 	nticks = delta >> FIX_SHIFT;
167 
168 	if (nticks)
169 		do_timer(nticks);
170 
171 	write_sequnlock(&xtime_lock);
172 
173 #ifndef CONFIG_SMP
174 	while (nticks--)
175 		update_process_times(user_mode(get_irq_regs()));
176 #endif
177 
178 	return IRQ_HANDLED;
179 }
180 
181 void __init
182 common_init_rtc(void)
183 {
184 	unsigned char x;
185 
186 	/* Reset periodic interrupt frequency.  */
187 	x = CMOS_READ(RTC_FREQ_SELECT) & 0x3f;
188         /* Test includes known working values on various platforms
189            where 0x26 is wrong; we refuse to change those. */
190 	if (x != 0x26 && x != 0x25 && x != 0x19 && x != 0x06) {
191 		printk("Setting RTC_FREQ to 1024 Hz (%x)\n", x);
192 		CMOS_WRITE(0x26, RTC_FREQ_SELECT);
193 	}
194 
195 	/* Turn on periodic interrupts.  */
196 	x = CMOS_READ(RTC_CONTROL);
197 	if (!(x & RTC_PIE)) {
198 		printk("Turning on RTC interrupts.\n");
199 		x |= RTC_PIE;
200 		x &= ~(RTC_AIE | RTC_UIE);
201 		CMOS_WRITE(x, RTC_CONTROL);
202 	}
203 	(void) CMOS_READ(RTC_INTR_FLAGS);
204 
205 	outb(0x36, 0x43);	/* pit counter 0: system timer */
206 	outb(0x00, 0x40);
207 	outb(0x00, 0x40);
208 
209 	outb(0xb6, 0x43);	/* pit counter 2: speaker */
210 	outb(0x31, 0x42);
211 	outb(0x13, 0x42);
212 
213 	init_rtc_irq();
214 }
215 
216 unsigned int common_get_rtc_time(struct rtc_time *time)
217 {
218 	return __get_rtc_time(time);
219 }
220 
221 int common_set_rtc_time(struct rtc_time *time)
222 {
223 	return __set_rtc_time(time);
224 }
225 
226 /* Validate a computed cycle counter result against the known bounds for
227    the given processor core.  There's too much brokenness in the way of
228    timing hardware for any one method to work everywhere.  :-(
229 
230    Return 0 if the result cannot be trusted, otherwise return the argument.  */
231 
232 static unsigned long __init
233 validate_cc_value(unsigned long cc)
234 {
235 	static struct bounds {
236 		unsigned int min, max;
237 	} cpu_hz[] __initdata = {
238 		[EV3_CPU]    = {   50000000,  200000000 },	/* guess */
239 		[EV4_CPU]    = {  100000000,  300000000 },
240 		[LCA4_CPU]   = {  100000000,  300000000 },	/* guess */
241 		[EV45_CPU]   = {  200000000,  300000000 },
242 		[EV5_CPU]    = {  250000000,  433000000 },
243 		[EV56_CPU]   = {  333000000,  667000000 },
244 		[PCA56_CPU]  = {  400000000,  600000000 },	/* guess */
245 		[PCA57_CPU]  = {  500000000,  600000000 },	/* guess */
246 		[EV6_CPU]    = {  466000000,  600000000 },
247 		[EV67_CPU]   = {  600000000,  750000000 },
248 		[EV68AL_CPU] = {  750000000,  940000000 },
249 		[EV68CB_CPU] = { 1000000000, 1333333333 },
250 		/* None of the following are shipping as of 2001-11-01.  */
251 		[EV68CX_CPU] = { 1000000000, 1700000000 },	/* guess */
252 		[EV69_CPU]   = { 1000000000, 1700000000 },	/* guess */
253 		[EV7_CPU]    = {  800000000, 1400000000 },	/* guess */
254 		[EV79_CPU]   = { 1000000000, 2000000000 },	/* guess */
255 	};
256 
257 	/* Allow for some drift in the crystal.  10MHz is more than enough.  */
258 	const unsigned int deviation = 10000000;
259 
260 	struct percpu_struct *cpu;
261 	unsigned int index;
262 
263 	cpu = (struct percpu_struct *)((char*)hwrpb + hwrpb->processor_offset);
264 	index = cpu->type & 0xffffffff;
265 
266 	/* If index out of bounds, no way to validate.  */
267 	if (index >= ARRAY_SIZE(cpu_hz))
268 		return cc;
269 
270 	/* If index contains no data, no way to validate.  */
271 	if (cpu_hz[index].max == 0)
272 		return cc;
273 
274 	if (cc < cpu_hz[index].min - deviation
275 	    || cc > cpu_hz[index].max + deviation)
276 		return 0;
277 
278 	return cc;
279 }
280 
281 
282 /*
283  * Calibrate CPU clock using legacy 8254 timer/counter. Stolen from
284  * arch/i386/time.c.
285  */
286 
287 #define CALIBRATE_LATCH	0xffff
288 #define TIMEOUT_COUNT	0x100000
289 
290 static unsigned long __init
291 calibrate_cc_with_pit(void)
292 {
293 	int cc, count = 0;
294 
295 	/* Set the Gate high, disable speaker */
296 	outb((inb(0x61) & ~0x02) | 0x01, 0x61);
297 
298 	/*
299 	 * Now let's take care of CTC channel 2
300 	 *
301 	 * Set the Gate high, program CTC channel 2 for mode 0,
302 	 * (interrupt on terminal count mode), binary count,
303 	 * load 5 * LATCH count, (LSB and MSB) to begin countdown.
304 	 */
305 	outb(0xb0, 0x43);		/* binary, mode 0, LSB/MSB, Ch 2 */
306 	outb(CALIBRATE_LATCH & 0xff, 0x42);	/* LSB of count */
307 	outb(CALIBRATE_LATCH >> 8, 0x42);	/* MSB of count */
308 
309 	cc = rpcc();
310 	do {
311 		count++;
312 	} while ((inb(0x61) & 0x20) == 0 && count < TIMEOUT_COUNT);
313 	cc = rpcc() - cc;
314 
315 	/* Error: ECTCNEVERSET or ECPUTOOFAST.  */
316 	if (count <= 1 || count == TIMEOUT_COUNT)
317 		return 0;
318 
319 	return ((long)cc * PIT_TICK_RATE) / (CALIBRATE_LATCH + 1);
320 }
321 
322 /* The Linux interpretation of the CMOS clock register contents:
323    When the Update-In-Progress (UIP) flag goes from 1 to 0, the
324    RTC registers show the second which has precisely just started.
325    Let's hope other operating systems interpret the RTC the same way.  */
326 
327 static unsigned long __init
328 rpcc_after_update_in_progress(void)
329 {
330 	do { } while (!(CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP));
331 	do { } while (CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP);
332 
333 	return rpcc();
334 }
335 
336 #ifndef CONFIG_SMP
337 /* Until and unless we figure out how to get cpu cycle counters
338    in sync and keep them there, we can't use the rpcc.  */
339 static cycle_t read_rpcc(struct clocksource *cs)
340 {
341 	cycle_t ret = (cycle_t)rpcc();
342 	return ret;
343 }
344 
345 static struct clocksource clocksource_rpcc = {
346 	.name                   = "rpcc",
347 	.rating                 = 300,
348 	.read                   = read_rpcc,
349 	.mask                   = CLOCKSOURCE_MASK(32),
350 	.flags                  = CLOCK_SOURCE_IS_CONTINUOUS
351 };
352 
353 static inline void register_rpcc_clocksource(long cycle_freq)
354 {
355 	clocksource_calc_mult_shift(&clocksource_rpcc, cycle_freq, 4);
356 	clocksource_register(&clocksource_rpcc);
357 }
358 #else /* !CONFIG_SMP */
359 static inline void register_rpcc_clocksource(long cycle_freq)
360 {
361 }
362 #endif /* !CONFIG_SMP */
363 
364 void __init
365 time_init(void)
366 {
367 	unsigned int cc1, cc2;
368 	unsigned long cycle_freq, tolerance;
369 	long diff;
370 
371 	/* Calibrate CPU clock -- attempt #1.  */
372 	if (!est_cycle_freq)
373 		est_cycle_freq = validate_cc_value(calibrate_cc_with_pit());
374 
375 	cc1 = rpcc();
376 
377 	/* Calibrate CPU clock -- attempt #2.  */
378 	if (!est_cycle_freq) {
379 		cc1 = rpcc_after_update_in_progress();
380 		cc2 = rpcc_after_update_in_progress();
381 		est_cycle_freq = validate_cc_value(cc2 - cc1);
382 		cc1 = cc2;
383 	}
384 
385 	cycle_freq = hwrpb->cycle_freq;
386 	if (est_cycle_freq) {
387 		/* If the given value is within 250 PPM of what we calculated,
388 		   accept it.  Otherwise, use what we found.  */
389 		tolerance = cycle_freq / 4000;
390 		diff = cycle_freq - est_cycle_freq;
391 		if (diff < 0)
392 			diff = -diff;
393 		if ((unsigned long)diff > tolerance) {
394 			cycle_freq = est_cycle_freq;
395 			printk("HWRPB cycle frequency bogus.  "
396 			       "Estimated %lu Hz\n", cycle_freq);
397 		} else {
398 			est_cycle_freq = 0;
399 		}
400 	} else if (! validate_cc_value (cycle_freq)) {
401 		printk("HWRPB cycle frequency bogus, "
402 		       "and unable to estimate a proper value!\n");
403 	}
404 
405 	/* From John Bowman <bowman@math.ualberta.ca>: allow the values
406 	   to settle, as the Update-In-Progress bit going low isn't good
407 	   enough on some hardware.  2ms is our guess; we haven't found
408 	   bogomips yet, but this is close on a 500Mhz box.  */
409 	__delay(1000000);
410 
411 
412 	if (HZ > (1<<16)) {
413 		extern void __you_loose (void);
414 		__you_loose();
415 	}
416 
417 	register_rpcc_clocksource(cycle_freq);
418 
419 	state.last_time = cc1;
420 	state.scaled_ticks_per_cycle
421 		= ((unsigned long) HZ << FIX_SHIFT) / cycle_freq;
422 	state.partial_tick = 0L;
423 
424 	/* Startup the timer source. */
425 	alpha_mv.init_rtc();
426 }
427 
428 /*
429  * In order to set the CMOS clock precisely, set_rtc_mmss has to be
430  * called 500 ms after the second nowtime has started, because when
431  * nowtime is written into the registers of the CMOS clock, it will
432  * jump to the next second precisely 500 ms later. Check the Motorola
433  * MC146818A or Dallas DS12887 data sheet for details.
434  *
435  * BUG: This routine does not handle hour overflow properly; it just
436  *      sets the minutes. Usually you won't notice until after reboot!
437  */
438 
439 
440 static int
441 set_rtc_mmss(unsigned long nowtime)
442 {
443 	int retval = 0;
444 	int real_seconds, real_minutes, cmos_minutes;
445 	unsigned char save_control, save_freq_select;
446 
447 	/* irq are locally disabled here */
448 	spin_lock(&rtc_lock);
449 	/* Tell the clock it's being set */
450 	save_control = CMOS_READ(RTC_CONTROL);
451 	CMOS_WRITE((save_control|RTC_SET), RTC_CONTROL);
452 
453 	/* Stop and reset prescaler */
454 	save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
455 	CMOS_WRITE((save_freq_select|RTC_DIV_RESET2), RTC_FREQ_SELECT);
456 
457 	cmos_minutes = CMOS_READ(RTC_MINUTES);
458 	if (!(save_control & RTC_DM_BINARY) || RTC_ALWAYS_BCD)
459 		cmos_minutes = bcd2bin(cmos_minutes);
460 
461 	/*
462 	 * since we're only adjusting minutes and seconds,
463 	 * don't interfere with hour overflow. This avoids
464 	 * messing with unknown time zones but requires your
465 	 * RTC not to be off by more than 15 minutes
466 	 */
467 	real_seconds = nowtime % 60;
468 	real_minutes = nowtime / 60;
469 	if (((abs(real_minutes - cmos_minutes) + 15)/30) & 1) {
470 		/* correct for half hour time zone */
471 		real_minutes += 30;
472 	}
473 	real_minutes %= 60;
474 
475 	if (abs(real_minutes - cmos_minutes) < 30) {
476 		if (!(save_control & RTC_DM_BINARY) || RTC_ALWAYS_BCD) {
477 			real_seconds = bin2bcd(real_seconds);
478 			real_minutes = bin2bcd(real_minutes);
479 		}
480 		CMOS_WRITE(real_seconds,RTC_SECONDS);
481 		CMOS_WRITE(real_minutes,RTC_MINUTES);
482 	} else {
483 		printk(KERN_WARNING
484 		       "set_rtc_mmss: can't update from %d to %d\n",
485 		       cmos_minutes, real_minutes);
486  		retval = -1;
487 	}
488 
489 	/* The following flags have to be released exactly in this order,
490 	 * otherwise the DS12887 (popular MC146818A clone with integrated
491 	 * battery and quartz) will not reset the oscillator and will not
492 	 * update precisely 500 ms later. You won't find this mentioned in
493 	 * the Dallas Semiconductor data sheets, but who believes data
494 	 * sheets anyway ...                           -- Markus Kuhn
495 	 */
496 	CMOS_WRITE(save_control, RTC_CONTROL);
497 	CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
498 	spin_unlock(&rtc_lock);
499 
500 	return retval;
501 }
502