1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * linux/arch/alpha/kernel/sys_rawhide.c 4 * 5 * Copyright (C) 1995 David A Rusling 6 * Copyright (C) 1996 Jay A Estabrook 7 * Copyright (C) 1998, 1999 Richard Henderson 8 * 9 * Code supporting the RAWHIDE. 10 */ 11 12 #include <linux/kernel.h> 13 #include <linux/types.h> 14 #include <linux/mm.h> 15 #include <linux/sched.h> 16 #include <linux/pci.h> 17 #include <linux/init.h> 18 19 #include <asm/ptrace.h> 20 #include <asm/dma.h> 21 #include <asm/irq.h> 22 #include <asm/mmu_context.h> 23 #include <asm/io.h> 24 #include <asm/core_mcpcia.h> 25 #include <asm/tlbflush.h> 26 27 #include "proto.h" 28 #include "irq_impl.h" 29 #include "pci_impl.h" 30 #include "machvec_impl.h" 31 32 33 /* 34 * HACK ALERT! only the boot cpu is used for interrupts. 35 */ 36 37 38 /* Note mask bit is true for ENABLED irqs. */ 39 40 static unsigned int hose_irq_masks[4] = { 41 0xff0000, 0xfe0000, 0xff0000, 0xff0000 42 }; 43 static unsigned int cached_irq_masks[4]; 44 DEFINE_RAW_SPINLOCK(rawhide_irq_lock); 45 46 static inline void 47 rawhide_update_irq_hw(int hose, int mask) 48 { 49 *(vuip)MCPCIA_INT_MASK0(MCPCIA_HOSE2MID(hose)) = mask; 50 mb(); 51 *(vuip)MCPCIA_INT_MASK0(MCPCIA_HOSE2MID(hose)); 52 } 53 54 #define hose_exists(h) \ 55 (((h) < MCPCIA_MAX_HOSES) && (cached_irq_masks[(h)] != 0)) 56 57 static inline void 58 rawhide_enable_irq(struct irq_data *d) 59 { 60 unsigned int mask, hose; 61 unsigned int irq = d->irq; 62 unsigned long flags; 63 64 irq -= 16; 65 hose = irq / 24; 66 if (!hose_exists(hose)) /* if hose non-existent, exit */ 67 return; 68 69 irq -= hose * 24; 70 mask = 1 << irq; 71 72 raw_spin_lock_irqsave(&rawhide_irq_lock, flags); 73 mask |= cached_irq_masks[hose]; 74 cached_irq_masks[hose] = mask; 75 rawhide_update_irq_hw(hose, mask); 76 raw_spin_unlock_irqrestore(&rawhide_irq_lock, flags); 77 } 78 79 static void 80 rawhide_disable_irq(struct irq_data *d) 81 { 82 unsigned int mask, hose; 83 unsigned int irq = d->irq; 84 unsigned long flags; 85 86 irq -= 16; 87 hose = irq / 24; 88 if (!hose_exists(hose)) /* if hose non-existent, exit */ 89 return; 90 91 irq -= hose * 24; 92 mask = ~(1 << irq) | hose_irq_masks[hose]; 93 94 raw_spin_lock_irqsave(&rawhide_irq_lock, flags); 95 mask &= cached_irq_masks[hose]; 96 cached_irq_masks[hose] = mask; 97 rawhide_update_irq_hw(hose, mask); 98 raw_spin_unlock_irqrestore(&rawhide_irq_lock, flags); 99 } 100 101 static void 102 rawhide_mask_and_ack_irq(struct irq_data *d) 103 { 104 unsigned int mask, mask1, hose; 105 unsigned int irq = d->irq; 106 unsigned long flags; 107 108 irq -= 16; 109 hose = irq / 24; 110 if (!hose_exists(hose)) /* if hose non-existent, exit */ 111 return; 112 113 irq -= hose * 24; 114 mask1 = 1 << irq; 115 mask = ~mask1 | hose_irq_masks[hose]; 116 117 raw_spin_lock_irqsave(&rawhide_irq_lock, flags); 118 119 mask &= cached_irq_masks[hose]; 120 cached_irq_masks[hose] = mask; 121 rawhide_update_irq_hw(hose, mask); 122 123 /* Clear the interrupt. */ 124 *(vuip)MCPCIA_INT_REQ(MCPCIA_HOSE2MID(hose)) = mask1; 125 126 raw_spin_unlock_irqrestore(&rawhide_irq_lock, flags); 127 } 128 129 static struct irq_chip rawhide_irq_type = { 130 .name = "RAWHIDE", 131 .irq_unmask = rawhide_enable_irq, 132 .irq_mask = rawhide_disable_irq, 133 .irq_mask_ack = rawhide_mask_and_ack_irq, 134 }; 135 136 static void 137 rawhide_srm_device_interrupt(unsigned long vector) 138 { 139 int irq; 140 141 irq = (vector - 0x800) >> 4; 142 143 /* 144 * The RAWHIDE SRM console reports PCI interrupts with a vector 145 * 0x80 *higher* than one might expect, as PCI IRQ 0 (ie bit 0) 146 * shows up as IRQ 24, etc, etc. We adjust it down by 8 to have 147 * it line up with the actual bit numbers from the REQ registers, 148 * which is how we manage the interrupts/mask. Sigh... 149 * 150 * Also, PCI #1 interrupts are offset some more... :-( 151 */ 152 153 if (irq == 52) { 154 /* SCSI on PCI1 is special. */ 155 irq = 72; 156 } 157 158 /* Adjust by which hose it is from. */ 159 irq -= ((irq + 16) >> 2) & 0x38; 160 161 handle_irq(irq); 162 } 163 164 static void __init 165 rawhide_init_irq(void) 166 { 167 struct pci_controller *hose; 168 long i; 169 170 mcpcia_init_hoses(); 171 172 /* Clear them all; only hoses that exist will be non-zero. */ 173 for (i = 0; i < MCPCIA_MAX_HOSES; i++) cached_irq_masks[i] = 0; 174 175 for (hose = hose_head; hose; hose = hose->next) { 176 unsigned int h = hose->index; 177 unsigned int mask = hose_irq_masks[h]; 178 179 cached_irq_masks[h] = mask; 180 *(vuip)MCPCIA_INT_MASK0(MCPCIA_HOSE2MID(h)) = mask; 181 *(vuip)MCPCIA_INT_MASK1(MCPCIA_HOSE2MID(h)) = 0; 182 } 183 184 for (i = 16; i < 128; ++i) { 185 irq_set_chip_and_handler(i, &rawhide_irq_type, 186 handle_level_irq); 187 irq_set_status_flags(i, IRQ_LEVEL); 188 } 189 190 init_i8259a_irqs(); 191 common_init_isa_dma(); 192 } 193 194 /* 195 * PCI Fixup configuration. 196 * 197 * Summary @ MCPCIA_PCI0_INT_REQ: 198 * Bit Meaning 199 * 0 Interrupt Line A from slot 2 PCI0 200 * 1 Interrupt Line B from slot 2 PCI0 201 * 2 Interrupt Line C from slot 2 PCI0 202 * 3 Interrupt Line D from slot 2 PCI0 203 * 4 Interrupt Line A from slot 3 PCI0 204 * 5 Interrupt Line B from slot 3 PCI0 205 * 6 Interrupt Line C from slot 3 PCI0 206 * 7 Interrupt Line D from slot 3 PCI0 207 * 8 Interrupt Line A from slot 4 PCI0 208 * 9 Interrupt Line B from slot 4 PCI0 209 * 10 Interrupt Line C from slot 4 PCI0 210 * 11 Interrupt Line D from slot 4 PCI0 211 * 12 Interrupt Line A from slot 5 PCI0 212 * 13 Interrupt Line B from slot 5 PCI0 213 * 14 Interrupt Line C from slot 5 PCI0 214 * 15 Interrupt Line D from slot 5 PCI0 215 * 16 EISA interrupt (PCI 0) or SCSI interrupt (PCI 1) 216 * 17-23 NA 217 * 218 * IdSel 219 * 1 EISA bridge (PCI bus 0 only) 220 * 2 PCI option slot 2 221 * 3 PCI option slot 3 222 * 4 PCI option slot 4 223 * 5 PCI option slot 5 224 * 225 */ 226 227 static int 228 rawhide_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) 229 { 230 static char irq_tab[5][5] = { 231 /*INT INTA INTB INTC INTD */ 232 { 16+16, 16+16, 16+16, 16+16, 16+16}, /* IdSel 1 SCSI PCI 1 */ 233 { 16+ 0, 16+ 0, 16+ 1, 16+ 2, 16+ 3}, /* IdSel 2 slot 2 */ 234 { 16+ 4, 16+ 4, 16+ 5, 16+ 6, 16+ 7}, /* IdSel 3 slot 3 */ 235 { 16+ 8, 16+ 8, 16+ 9, 16+10, 16+11}, /* IdSel 4 slot 4 */ 236 { 16+12, 16+12, 16+13, 16+14, 16+15} /* IdSel 5 slot 5 */ 237 }; 238 const long min_idsel = 1, max_idsel = 5, irqs_per_slot = 5; 239 240 struct pci_controller *hose = dev->sysdata; 241 int irq = COMMON_TABLE_LOOKUP; 242 if (irq >= 0) 243 irq += 24 * hose->index; 244 return irq; 245 } 246 247 248 /* 249 * The System Vector 250 */ 251 252 struct alpha_machine_vector rawhide_mv __initmv = { 253 .vector_name = "Rawhide", 254 DO_EV5_MMU, 255 DO_DEFAULT_RTC, 256 DO_MCPCIA_IO, 257 .machine_check = mcpcia_machine_check, 258 .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS, 259 .min_io_address = DEFAULT_IO_BASE, 260 .min_mem_address = MCPCIA_DEFAULT_MEM_BASE, 261 .pci_dac_offset = MCPCIA_DAC_OFFSET, 262 263 .nr_irqs = 128, 264 .device_interrupt = rawhide_srm_device_interrupt, 265 266 .init_arch = mcpcia_init_arch, 267 .init_irq = rawhide_init_irq, 268 .init_rtc = common_init_rtc, 269 .init_pci = common_init_pci, 270 .kill_arch = NULL, 271 .pci_map_irq = rawhide_map_irq, 272 .pci_swizzle = common_swizzle, 273 }; 274 ALIAS_MV(rawhide) 275