1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * linux/arch/alpha/kernel/sys_noritake.c 4 * 5 * Copyright (C) 1995 David A Rusling 6 * Copyright (C) 1996 Jay A Estabrook 7 * Copyright (C) 1998, 1999 Richard Henderson 8 * 9 * Code supporting the NORITAKE (AlphaServer 1000A), 10 * CORELLE (AlphaServer 800), and ALCOR Primo (AlphaStation 600A). 11 */ 12 13 #include <linux/kernel.h> 14 #include <linux/types.h> 15 #include <linux/mm.h> 16 #include <linux/sched.h> 17 #include <linux/pci.h> 18 #include <linux/init.h> 19 #include <linux/bitops.h> 20 21 #include <asm/ptrace.h> 22 #include <asm/mce.h> 23 #include <asm/dma.h> 24 #include <asm/irq.h> 25 #include <asm/mmu_context.h> 26 #include <asm/io.h> 27 #include <asm/core_cia.h> 28 #include <asm/tlbflush.h> 29 30 #include "proto.h" 31 #include "irq_impl.h" 32 #include "pci_impl.h" 33 #include "machvec_impl.h" 34 35 /* Note mask bit is true for ENABLED irqs. */ 36 static int cached_irq_mask; 37 38 static inline void 39 noritake_update_irq_hw(int irq, int mask) 40 { 41 int port = 0x54a; 42 if (irq >= 32) { 43 mask >>= 16; 44 port = 0x54c; 45 } 46 outw(mask, port); 47 } 48 49 static void 50 noritake_enable_irq(struct irq_data *d) 51 { 52 noritake_update_irq_hw(d->irq, cached_irq_mask |= 1 << (d->irq - 16)); 53 } 54 55 static void 56 noritake_disable_irq(struct irq_data *d) 57 { 58 noritake_update_irq_hw(d->irq, cached_irq_mask &= ~(1 << (d->irq - 16))); 59 } 60 61 static struct irq_chip noritake_irq_type = { 62 .name = "NORITAKE", 63 .irq_unmask = noritake_enable_irq, 64 .irq_mask = noritake_disable_irq, 65 .irq_mask_ack = noritake_disable_irq, 66 }; 67 68 static void 69 noritake_device_interrupt(unsigned long vector) 70 { 71 unsigned long pld; 72 unsigned int i; 73 74 /* Read the interrupt summary registers of NORITAKE */ 75 pld = (((unsigned long) inw(0x54c) << 32) 76 | ((unsigned long) inw(0x54a) << 16) 77 | ((unsigned long) inb(0xa0) << 8) 78 | inb(0x20)); 79 80 /* 81 * Now for every possible bit set, work through them and call 82 * the appropriate interrupt handler. 83 */ 84 while (pld) { 85 i = ffz(~pld); 86 pld &= pld - 1; /* clear least bit set */ 87 if (i < 16) { 88 isa_device_interrupt(vector); 89 } else { 90 handle_irq(i); 91 } 92 } 93 } 94 95 static void 96 noritake_srm_device_interrupt(unsigned long vector) 97 { 98 int irq; 99 100 irq = (vector - 0x800) >> 4; 101 102 /* 103 * I really hate to do this, too, but the NORITAKE SRM console also 104 * reports PCI vectors *lower* than I expected from the bit numbers 105 * in the documentation. 106 * But I really don't want to change the fixup code for allocation 107 * of IRQs, nor the alpha_irq_mask maintenance stuff, both of which 108 * look nice and clean now. 109 * So, here's this additional grotty hack... :-( 110 */ 111 if (irq >= 16) 112 irq = irq + 1; 113 114 handle_irq(irq); 115 } 116 117 static void __init 118 noritake_init_irq(void) 119 { 120 long i; 121 122 if (alpha_using_srm) 123 alpha_mv.device_interrupt = noritake_srm_device_interrupt; 124 125 outw(0, 0x54a); 126 outw(0, 0x54c); 127 128 for (i = 16; i < 48; ++i) { 129 irq_set_chip_and_handler(i, &noritake_irq_type, 130 handle_level_irq); 131 irq_set_status_flags(i, IRQ_LEVEL); 132 } 133 134 init_i8259a_irqs(); 135 common_init_isa_dma(); 136 } 137 138 139 /* 140 * PCI Fixup configuration. 141 * 142 * Summary @ 0x542, summary register #1: 143 * Bit Meaning 144 * 0 All valid ints from summary regs 2 & 3 145 * 1 QLOGIC ISP1020A SCSI 146 * 2 Interrupt Line A from slot 0 147 * 3 Interrupt Line B from slot 0 148 * 4 Interrupt Line A from slot 1 149 * 5 Interrupt line B from slot 1 150 * 6 Interrupt Line A from slot 2 151 * 7 Interrupt Line B from slot 2 152 * 8 Interrupt Line A from slot 3 153 * 9 Interrupt Line B from slot 3 154 *10 Interrupt Line A from slot 4 155 *11 Interrupt Line B from slot 4 156 *12 Interrupt Line A from slot 5 157 *13 Interrupt Line B from slot 5 158 *14 Interrupt Line A from slot 6 159 *15 Interrupt Line B from slot 6 160 * 161 * Summary @ 0x544, summary register #2: 162 * Bit Meaning 163 * 0 OR of all unmasked ints in SR #2 164 * 1 OR of secondary bus ints 165 * 2 Interrupt Line C from slot 0 166 * 3 Interrupt Line D from slot 0 167 * 4 Interrupt Line C from slot 1 168 * 5 Interrupt line D from slot 1 169 * 6 Interrupt Line C from slot 2 170 * 7 Interrupt Line D from slot 2 171 * 8 Interrupt Line C from slot 3 172 * 9 Interrupt Line D from slot 3 173 *10 Interrupt Line C from slot 4 174 *11 Interrupt Line D from slot 4 175 *12 Interrupt Line C from slot 5 176 *13 Interrupt Line D from slot 5 177 *14 Interrupt Line C from slot 6 178 *15 Interrupt Line D from slot 6 179 * 180 * The device to slot mapping looks like: 181 * 182 * Slot Device 183 * 7 Intel PCI-EISA bridge chip 184 * 8 DEC PCI-PCI bridge chip 185 * 11 PCI on board slot 0 186 * 12 PCI on board slot 1 187 * 13 PCI on board slot 2 188 * 189 * 190 * This two layered interrupt approach means that we allocate IRQ 16 and 191 * above for PCI interrupts. The IRQ relates to which bit the interrupt 192 * comes in on. This makes interrupt processing much easier. 193 */ 194 195 static int 196 noritake_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) 197 { 198 static char irq_tab[15][5] = { 199 /*INT INTA INTB INTC INTD */ 200 /* note: IDSELs 16, 17, and 25 are CORELLE only */ 201 { 16+1, 16+1, 16+1, 16+1, 16+1}, /* IdSel 16, QLOGIC */ 202 { -1, -1, -1, -1, -1}, /* IdSel 17, S3 Trio64 */ 203 { -1, -1, -1, -1, -1}, /* IdSel 18, PCEB */ 204 { -1, -1, -1, -1, -1}, /* IdSel 19, PPB */ 205 { -1, -1, -1, -1, -1}, /* IdSel 20, ???? */ 206 { -1, -1, -1, -1, -1}, /* IdSel 21, ???? */ 207 { 16+2, 16+2, 16+3, 32+2, 32+3}, /* IdSel 22, slot 0 */ 208 { 16+4, 16+4, 16+5, 32+4, 32+5}, /* IdSel 23, slot 1 */ 209 { 16+6, 16+6, 16+7, 32+6, 32+7}, /* IdSel 24, slot 2 */ 210 { 16+8, 16+8, 16+9, 32+8, 32+9}, /* IdSel 25, slot 3 */ 211 /* The following 5 are actually on PCI bus 1, which is 212 across the built-in bridge of the NORITAKE only. */ 213 { 16+1, 16+1, 16+1, 16+1, 16+1}, /* IdSel 16, QLOGIC */ 214 { 16+8, 16+8, 16+9, 32+8, 32+9}, /* IdSel 17, slot 3 */ 215 {16+10, 16+10, 16+11, 32+10, 32+11}, /* IdSel 18, slot 4 */ 216 {16+12, 16+12, 16+13, 32+12, 32+13}, /* IdSel 19, slot 5 */ 217 {16+14, 16+14, 16+15, 32+14, 32+15}, /* IdSel 20, slot 6 */ 218 }; 219 const long min_idsel = 5, max_idsel = 19, irqs_per_slot = 5; 220 return COMMON_TABLE_LOOKUP; 221 } 222 223 static u8 224 noritake_swizzle(struct pci_dev *dev, u8 *pinp) 225 { 226 int slot, pin = *pinp; 227 228 if (dev->bus->number == 0) { 229 slot = PCI_SLOT(dev->devfn); 230 } 231 /* Check for the built-in bridge */ 232 else if (PCI_SLOT(dev->bus->self->devfn) == 8) { 233 slot = PCI_SLOT(dev->devfn) + 15; /* WAG! */ 234 } 235 else 236 { 237 /* Must be a card-based bridge. */ 238 do { 239 if (PCI_SLOT(dev->bus->self->devfn) == 8) { 240 slot = PCI_SLOT(dev->devfn) + 15; 241 break; 242 } 243 pin = pci_swizzle_interrupt_pin(dev, pin); 244 245 /* Move up the chain of bridges. */ 246 dev = dev->bus->self; 247 /* Slot of the next bridge. */ 248 slot = PCI_SLOT(dev->devfn); 249 } while (dev->bus->self); 250 } 251 *pinp = pin; 252 return slot; 253 } 254 255 struct alpha_machine_vector noritake_primo_mv __initmv = { 256 .vector_name = "Noritake-Primo", 257 DO_EV5_MMU, 258 DO_DEFAULT_RTC, 259 DO_CIA_IO, 260 .machine_check = cia_machine_check, 261 .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS, 262 .min_io_address = EISA_DEFAULT_IO_BASE, 263 .min_mem_address = CIA_DEFAULT_MEM_BASE, 264 265 .nr_irqs = 48, 266 .device_interrupt = noritake_device_interrupt, 267 268 .init_arch = cia_init_arch, 269 .init_irq = noritake_init_irq, 270 .init_rtc = common_init_rtc, 271 .init_pci = cia_init_pci, 272 .kill_arch = cia_kill_arch, 273 .pci_map_irq = noritake_map_irq, 274 .pci_swizzle = noritake_swizzle, 275 }; 276 ALIAS_MV(noritake_primo) 277