1*b2441318SGreg Kroah-Hartman // SPDX-License-Identifier: GPL-2.0 21da177e4SLinus Torvalds /* 31da177e4SLinus Torvalds * linux/arch/alpha/kernel/sys_noritake.c 41da177e4SLinus Torvalds * 51da177e4SLinus Torvalds * Copyright (C) 1995 David A Rusling 61da177e4SLinus Torvalds * Copyright (C) 1996 Jay A Estabrook 71da177e4SLinus Torvalds * Copyright (C) 1998, 1999 Richard Henderson 81da177e4SLinus Torvalds * 91da177e4SLinus Torvalds * Code supporting the NORITAKE (AlphaServer 1000A), 101da177e4SLinus Torvalds * CORELLE (AlphaServer 800), and ALCOR Primo (AlphaStation 600A). 111da177e4SLinus Torvalds */ 121da177e4SLinus Torvalds 131da177e4SLinus Torvalds #include <linux/kernel.h> 141da177e4SLinus Torvalds #include <linux/types.h> 151da177e4SLinus Torvalds #include <linux/mm.h> 161da177e4SLinus Torvalds #include <linux/sched.h> 171da177e4SLinus Torvalds #include <linux/pci.h> 181da177e4SLinus Torvalds #include <linux/init.h> 191da177e4SLinus Torvalds #include <linux/bitops.h> 201da177e4SLinus Torvalds 211da177e4SLinus Torvalds #include <asm/ptrace.h> 22ec221208SDavid Howells #include <asm/mce.h> 231da177e4SLinus Torvalds #include <asm/dma.h> 241da177e4SLinus Torvalds #include <asm/irq.h> 251da177e4SLinus Torvalds #include <asm/mmu_context.h> 261da177e4SLinus Torvalds #include <asm/io.h> 271da177e4SLinus Torvalds #include <asm/pgtable.h> 281da177e4SLinus Torvalds #include <asm/core_apecs.h> 291da177e4SLinus Torvalds #include <asm/core_cia.h> 301da177e4SLinus Torvalds #include <asm/tlbflush.h> 311da177e4SLinus Torvalds 321da177e4SLinus Torvalds #include "proto.h" 331da177e4SLinus Torvalds #include "irq_impl.h" 341da177e4SLinus Torvalds #include "pci_impl.h" 351da177e4SLinus Torvalds #include "machvec_impl.h" 361da177e4SLinus Torvalds 371da177e4SLinus Torvalds /* Note mask bit is true for ENABLED irqs. */ 381da177e4SLinus Torvalds static int cached_irq_mask; 391da177e4SLinus Torvalds 401da177e4SLinus Torvalds static inline void 411da177e4SLinus Torvalds noritake_update_irq_hw(int irq, int mask) 421da177e4SLinus Torvalds { 431da177e4SLinus Torvalds int port = 0x54a; 441da177e4SLinus Torvalds if (irq >= 32) { 451da177e4SLinus Torvalds mask >>= 16; 461da177e4SLinus Torvalds port = 0x54c; 471da177e4SLinus Torvalds } 481da177e4SLinus Torvalds outw(mask, port); 491da177e4SLinus Torvalds } 501da177e4SLinus Torvalds 511da177e4SLinus Torvalds static void 5276f4645fSThomas Gleixner noritake_enable_irq(struct irq_data *d) 531da177e4SLinus Torvalds { 5476f4645fSThomas Gleixner noritake_update_irq_hw(d->irq, cached_irq_mask |= 1 << (d->irq - 16)); 551da177e4SLinus Torvalds } 561da177e4SLinus Torvalds 571da177e4SLinus Torvalds static void 5876f4645fSThomas Gleixner noritake_disable_irq(struct irq_data *d) 591da177e4SLinus Torvalds { 6076f4645fSThomas Gleixner noritake_update_irq_hw(d->irq, cached_irq_mask &= ~(1 << (d->irq - 16))); 611da177e4SLinus Torvalds } 621da177e4SLinus Torvalds 6344377f62SThomas Gleixner static struct irq_chip noritake_irq_type = { 648ab1221cSThomas Gleixner .name = "NORITAKE", 6576f4645fSThomas Gleixner .irq_unmask = noritake_enable_irq, 6676f4645fSThomas Gleixner .irq_mask = noritake_disable_irq, 6776f4645fSThomas Gleixner .irq_mask_ack = noritake_disable_irq, 681da177e4SLinus Torvalds }; 691da177e4SLinus Torvalds 701da177e4SLinus Torvalds static void 717ca56053SAl Viro noritake_device_interrupt(unsigned long vector) 721da177e4SLinus Torvalds { 731da177e4SLinus Torvalds unsigned long pld; 741da177e4SLinus Torvalds unsigned int i; 751da177e4SLinus Torvalds 761da177e4SLinus Torvalds /* Read the interrupt summary registers of NORITAKE */ 771da177e4SLinus Torvalds pld = (((unsigned long) inw(0x54c) << 32) 781da177e4SLinus Torvalds | ((unsigned long) inw(0x54a) << 16) 791da177e4SLinus Torvalds | ((unsigned long) inb(0xa0) << 8) 801da177e4SLinus Torvalds | inb(0x20)); 811da177e4SLinus Torvalds 821da177e4SLinus Torvalds /* 831da177e4SLinus Torvalds * Now for every possible bit set, work through them and call 841da177e4SLinus Torvalds * the appropriate interrupt handler. 851da177e4SLinus Torvalds */ 861da177e4SLinus Torvalds while (pld) { 871da177e4SLinus Torvalds i = ffz(~pld); 881da177e4SLinus Torvalds pld &= pld - 1; /* clear least bit set */ 891da177e4SLinus Torvalds if (i < 16) { 907ca56053SAl Viro isa_device_interrupt(vector); 911da177e4SLinus Torvalds } else { 923dbb8c62SAl Viro handle_irq(i); 931da177e4SLinus Torvalds } 941da177e4SLinus Torvalds } 951da177e4SLinus Torvalds } 961da177e4SLinus Torvalds 971da177e4SLinus Torvalds static void 987ca56053SAl Viro noritake_srm_device_interrupt(unsigned long vector) 991da177e4SLinus Torvalds { 1001da177e4SLinus Torvalds int irq; 1011da177e4SLinus Torvalds 1021da177e4SLinus Torvalds irq = (vector - 0x800) >> 4; 1031da177e4SLinus Torvalds 1041da177e4SLinus Torvalds /* 1051da177e4SLinus Torvalds * I really hate to do this, too, but the NORITAKE SRM console also 1061da177e4SLinus Torvalds * reports PCI vectors *lower* than I expected from the bit numbers 1071da177e4SLinus Torvalds * in the documentation. 1081da177e4SLinus Torvalds * But I really don't want to change the fixup code for allocation 1091da177e4SLinus Torvalds * of IRQs, nor the alpha_irq_mask maintenance stuff, both of which 1101da177e4SLinus Torvalds * look nice and clean now. 1111da177e4SLinus Torvalds * So, here's this additional grotty hack... :-( 1121da177e4SLinus Torvalds */ 1131da177e4SLinus Torvalds if (irq >= 16) 1141da177e4SLinus Torvalds irq = irq + 1; 1151da177e4SLinus Torvalds 1163dbb8c62SAl Viro handle_irq(irq); 1171da177e4SLinus Torvalds } 1181da177e4SLinus Torvalds 1191da177e4SLinus Torvalds static void __init 1201da177e4SLinus Torvalds noritake_init_irq(void) 1211da177e4SLinus Torvalds { 1221da177e4SLinus Torvalds long i; 1231da177e4SLinus Torvalds 1241da177e4SLinus Torvalds if (alpha_using_srm) 1251da177e4SLinus Torvalds alpha_mv.device_interrupt = noritake_srm_device_interrupt; 1261da177e4SLinus Torvalds 1271da177e4SLinus Torvalds outw(0, 0x54a); 1281da177e4SLinus Torvalds outw(0, 0x54c); 1291da177e4SLinus Torvalds 1301da177e4SLinus Torvalds for (i = 16; i < 48; ++i) { 131a9eb076bSThomas Gleixner irq_set_chip_and_handler(i, &noritake_irq_type, 132a9eb076bSThomas Gleixner handle_level_irq); 13376f4645fSThomas Gleixner irq_set_status_flags(i, IRQ_LEVEL); 1341da177e4SLinus Torvalds } 1351da177e4SLinus Torvalds 1361da177e4SLinus Torvalds init_i8259a_irqs(); 1371da177e4SLinus Torvalds common_init_isa_dma(); 1381da177e4SLinus Torvalds } 1391da177e4SLinus Torvalds 1401da177e4SLinus Torvalds 1411da177e4SLinus Torvalds /* 1421da177e4SLinus Torvalds * PCI Fixup configuration. 1431da177e4SLinus Torvalds * 1441da177e4SLinus Torvalds * Summary @ 0x542, summary register #1: 1451da177e4SLinus Torvalds * Bit Meaning 1461da177e4SLinus Torvalds * 0 All valid ints from summary regs 2 & 3 1471da177e4SLinus Torvalds * 1 QLOGIC ISP1020A SCSI 1481da177e4SLinus Torvalds * 2 Interrupt Line A from slot 0 1491da177e4SLinus Torvalds * 3 Interrupt Line B from slot 0 1501da177e4SLinus Torvalds * 4 Interrupt Line A from slot 1 1511da177e4SLinus Torvalds * 5 Interrupt line B from slot 1 1521da177e4SLinus Torvalds * 6 Interrupt Line A from slot 2 1531da177e4SLinus Torvalds * 7 Interrupt Line B from slot 2 1541da177e4SLinus Torvalds * 8 Interrupt Line A from slot 3 1551da177e4SLinus Torvalds * 9 Interrupt Line B from slot 3 1561da177e4SLinus Torvalds *10 Interrupt Line A from slot 4 1571da177e4SLinus Torvalds *11 Interrupt Line B from slot 4 1581da177e4SLinus Torvalds *12 Interrupt Line A from slot 5 1591da177e4SLinus Torvalds *13 Interrupt Line B from slot 5 1601da177e4SLinus Torvalds *14 Interrupt Line A from slot 6 1611da177e4SLinus Torvalds *15 Interrupt Line B from slot 6 1621da177e4SLinus Torvalds * 1631da177e4SLinus Torvalds * Summary @ 0x544, summary register #2: 1641da177e4SLinus Torvalds * Bit Meaning 1651da177e4SLinus Torvalds * 0 OR of all unmasked ints in SR #2 1661da177e4SLinus Torvalds * 1 OR of secondary bus ints 1671da177e4SLinus Torvalds * 2 Interrupt Line C from slot 0 1681da177e4SLinus Torvalds * 3 Interrupt Line D from slot 0 1691da177e4SLinus Torvalds * 4 Interrupt Line C from slot 1 1701da177e4SLinus Torvalds * 5 Interrupt line D from slot 1 1711da177e4SLinus Torvalds * 6 Interrupt Line C from slot 2 1721da177e4SLinus Torvalds * 7 Interrupt Line D from slot 2 1731da177e4SLinus Torvalds * 8 Interrupt Line C from slot 3 1741da177e4SLinus Torvalds * 9 Interrupt Line D from slot 3 1751da177e4SLinus Torvalds *10 Interrupt Line C from slot 4 1761da177e4SLinus Torvalds *11 Interrupt Line D from slot 4 1771da177e4SLinus Torvalds *12 Interrupt Line C from slot 5 1781da177e4SLinus Torvalds *13 Interrupt Line D from slot 5 1791da177e4SLinus Torvalds *14 Interrupt Line C from slot 6 1801da177e4SLinus Torvalds *15 Interrupt Line D from slot 6 1811da177e4SLinus Torvalds * 1821da177e4SLinus Torvalds * The device to slot mapping looks like: 1831da177e4SLinus Torvalds * 1841da177e4SLinus Torvalds * Slot Device 1851da177e4SLinus Torvalds * 7 Intel PCI-EISA bridge chip 1861da177e4SLinus Torvalds * 8 DEC PCI-PCI bridge chip 1871da177e4SLinus Torvalds * 11 PCI on board slot 0 1881da177e4SLinus Torvalds * 12 PCI on board slot 1 1891da177e4SLinus Torvalds * 13 PCI on board slot 2 1901da177e4SLinus Torvalds * 1911da177e4SLinus Torvalds * 1921da177e4SLinus Torvalds * This two layered interrupt approach means that we allocate IRQ 16 and 1931da177e4SLinus Torvalds * above for PCI interrupts. The IRQ relates to which bit the interrupt 1941da177e4SLinus Torvalds * comes in on. This makes interrupt processing much easier. 1951da177e4SLinus Torvalds */ 1961da177e4SLinus Torvalds 1971da177e4SLinus Torvalds static int __init 198d5341942SRalf Baechle noritake_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) 1991da177e4SLinus Torvalds { 2001da177e4SLinus Torvalds static char irq_tab[15][5] __initdata = { 2011da177e4SLinus Torvalds /*INT INTA INTB INTC INTD */ 2021da177e4SLinus Torvalds /* note: IDSELs 16, 17, and 25 are CORELLE only */ 2031da177e4SLinus Torvalds { 16+1, 16+1, 16+1, 16+1, 16+1}, /* IdSel 16, QLOGIC */ 2041da177e4SLinus Torvalds { -1, -1, -1, -1, -1}, /* IdSel 17, S3 Trio64 */ 2051da177e4SLinus Torvalds { -1, -1, -1, -1, -1}, /* IdSel 18, PCEB */ 2061da177e4SLinus Torvalds { -1, -1, -1, -1, -1}, /* IdSel 19, PPB */ 2071da177e4SLinus Torvalds { -1, -1, -1, -1, -1}, /* IdSel 20, ???? */ 2081da177e4SLinus Torvalds { -1, -1, -1, -1, -1}, /* IdSel 21, ???? */ 2091da177e4SLinus Torvalds { 16+2, 16+2, 16+3, 32+2, 32+3}, /* IdSel 22, slot 0 */ 2101da177e4SLinus Torvalds { 16+4, 16+4, 16+5, 32+4, 32+5}, /* IdSel 23, slot 1 */ 2111da177e4SLinus Torvalds { 16+6, 16+6, 16+7, 32+6, 32+7}, /* IdSel 24, slot 2 */ 2121da177e4SLinus Torvalds { 16+8, 16+8, 16+9, 32+8, 32+9}, /* IdSel 25, slot 3 */ 2131da177e4SLinus Torvalds /* The following 5 are actually on PCI bus 1, which is 2141da177e4SLinus Torvalds across the built-in bridge of the NORITAKE only. */ 2151da177e4SLinus Torvalds { 16+1, 16+1, 16+1, 16+1, 16+1}, /* IdSel 16, QLOGIC */ 2161da177e4SLinus Torvalds { 16+8, 16+8, 16+9, 32+8, 32+9}, /* IdSel 17, slot 3 */ 2171da177e4SLinus Torvalds {16+10, 16+10, 16+11, 32+10, 32+11}, /* IdSel 18, slot 4 */ 2181da177e4SLinus Torvalds {16+12, 16+12, 16+13, 32+12, 32+13}, /* IdSel 19, slot 5 */ 2191da177e4SLinus Torvalds {16+14, 16+14, 16+15, 32+14, 32+15}, /* IdSel 20, slot 6 */ 2201da177e4SLinus Torvalds }; 2211da177e4SLinus Torvalds const long min_idsel = 5, max_idsel = 19, irqs_per_slot = 5; 2221da177e4SLinus Torvalds return COMMON_TABLE_LOOKUP; 2231da177e4SLinus Torvalds } 2241da177e4SLinus Torvalds 2251da177e4SLinus Torvalds static u8 __init 2261da177e4SLinus Torvalds noritake_swizzle(struct pci_dev *dev, u8 *pinp) 2271da177e4SLinus Torvalds { 2281da177e4SLinus Torvalds int slot, pin = *pinp; 2291da177e4SLinus Torvalds 2301da177e4SLinus Torvalds if (dev->bus->number == 0) { 2311da177e4SLinus Torvalds slot = PCI_SLOT(dev->devfn); 2321da177e4SLinus Torvalds } 2331da177e4SLinus Torvalds /* Check for the built-in bridge */ 2341da177e4SLinus Torvalds else if (PCI_SLOT(dev->bus->self->devfn) == 8) { 2351da177e4SLinus Torvalds slot = PCI_SLOT(dev->devfn) + 15; /* WAG! */ 2361da177e4SLinus Torvalds } 2371da177e4SLinus Torvalds else 2381da177e4SLinus Torvalds { 2391da177e4SLinus Torvalds /* Must be a card-based bridge. */ 2401da177e4SLinus Torvalds do { 2411da177e4SLinus Torvalds if (PCI_SLOT(dev->bus->self->devfn) == 8) { 2421da177e4SLinus Torvalds slot = PCI_SLOT(dev->devfn) + 15; 2431da177e4SLinus Torvalds break; 2441da177e4SLinus Torvalds } 2451be9baa0SBjorn Helgaas pin = pci_swizzle_interrupt_pin(dev, pin); 2461da177e4SLinus Torvalds 2471da177e4SLinus Torvalds /* Move up the chain of bridges. */ 2481da177e4SLinus Torvalds dev = dev->bus->self; 2491da177e4SLinus Torvalds /* Slot of the next bridge. */ 2501da177e4SLinus Torvalds slot = PCI_SLOT(dev->devfn); 2511da177e4SLinus Torvalds } while (dev->bus->self); 2521da177e4SLinus Torvalds } 2531da177e4SLinus Torvalds *pinp = pin; 2541da177e4SLinus Torvalds return slot; 2551da177e4SLinus Torvalds } 2561da177e4SLinus Torvalds 2571da177e4SLinus Torvalds #if defined(CONFIG_ALPHA_GENERIC) || !defined(CONFIG_ALPHA_PRIMO) 2581da177e4SLinus Torvalds static void 2594fa1970aSAl Viro noritake_apecs_machine_check(unsigned long vector, unsigned long la_ptr) 2601da177e4SLinus Torvalds { 2611da177e4SLinus Torvalds #define MCHK_NO_DEVSEL 0x205U 2621da177e4SLinus Torvalds #define MCHK_NO_TABT 0x204U 2631da177e4SLinus Torvalds 2641da177e4SLinus Torvalds struct el_common *mchk_header; 2651da177e4SLinus Torvalds unsigned int code; 2661da177e4SLinus Torvalds 2671da177e4SLinus Torvalds mchk_header = (struct el_common *)la_ptr; 2681da177e4SLinus Torvalds 2691da177e4SLinus Torvalds /* Clear the error before any reporting. */ 2701da177e4SLinus Torvalds mb(); 2711da177e4SLinus Torvalds mb(); /* magic */ 2721da177e4SLinus Torvalds draina(); 2731da177e4SLinus Torvalds apecs_pci_clr_err(); 2741da177e4SLinus Torvalds wrmces(0x7); 2751da177e4SLinus Torvalds mb(); 2761da177e4SLinus Torvalds 2771da177e4SLinus Torvalds code = mchk_header->code; 2784fa1970aSAl Viro process_mcheck_info(vector, la_ptr, "NORITAKE APECS", 2791da177e4SLinus Torvalds (mcheck_expected(0) 2801da177e4SLinus Torvalds && (code == MCHK_NO_DEVSEL 2811da177e4SLinus Torvalds || code == MCHK_NO_TABT))); 2821da177e4SLinus Torvalds } 2831da177e4SLinus Torvalds #endif 2841da177e4SLinus Torvalds 2851da177e4SLinus Torvalds 2861da177e4SLinus Torvalds /* 2871da177e4SLinus Torvalds * The System Vectors 2881da177e4SLinus Torvalds */ 2891da177e4SLinus Torvalds 2901da177e4SLinus Torvalds #if defined(CONFIG_ALPHA_GENERIC) || !defined(CONFIG_ALPHA_PRIMO) 2911da177e4SLinus Torvalds struct alpha_machine_vector noritake_mv __initmv = { 2921da177e4SLinus Torvalds .vector_name = "Noritake", 2931da177e4SLinus Torvalds DO_EV4_MMU, 2941da177e4SLinus Torvalds DO_DEFAULT_RTC, 2951da177e4SLinus Torvalds DO_APECS_IO, 2961da177e4SLinus Torvalds .machine_check = noritake_apecs_machine_check, 2971da177e4SLinus Torvalds .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS, 2981da177e4SLinus Torvalds .min_io_address = EISA_DEFAULT_IO_BASE, 2991da177e4SLinus Torvalds .min_mem_address = APECS_AND_LCA_DEFAULT_MEM_BASE, 3001da177e4SLinus Torvalds 3011da177e4SLinus Torvalds .nr_irqs = 48, 3021da177e4SLinus Torvalds .device_interrupt = noritake_device_interrupt, 3031da177e4SLinus Torvalds 3041da177e4SLinus Torvalds .init_arch = apecs_init_arch, 3051da177e4SLinus Torvalds .init_irq = noritake_init_irq, 3061da177e4SLinus Torvalds .init_rtc = common_init_rtc, 3071da177e4SLinus Torvalds .init_pci = common_init_pci, 3081da177e4SLinus Torvalds .pci_map_irq = noritake_map_irq, 3091da177e4SLinus Torvalds .pci_swizzle = noritake_swizzle, 3101da177e4SLinus Torvalds }; 3111da177e4SLinus Torvalds ALIAS_MV(noritake) 3121da177e4SLinus Torvalds #endif 3131da177e4SLinus Torvalds 3141da177e4SLinus Torvalds #if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_PRIMO) 3151da177e4SLinus Torvalds struct alpha_machine_vector noritake_primo_mv __initmv = { 3161da177e4SLinus Torvalds .vector_name = "Noritake-Primo", 3171da177e4SLinus Torvalds DO_EV5_MMU, 3181da177e4SLinus Torvalds DO_DEFAULT_RTC, 3191da177e4SLinus Torvalds DO_CIA_IO, 3201da177e4SLinus Torvalds .machine_check = cia_machine_check, 3211da177e4SLinus Torvalds .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS, 3221da177e4SLinus Torvalds .min_io_address = EISA_DEFAULT_IO_BASE, 3231da177e4SLinus Torvalds .min_mem_address = CIA_DEFAULT_MEM_BASE, 3241da177e4SLinus Torvalds 3251da177e4SLinus Torvalds .nr_irqs = 48, 3261da177e4SLinus Torvalds .device_interrupt = noritake_device_interrupt, 3271da177e4SLinus Torvalds 3281da177e4SLinus Torvalds .init_arch = cia_init_arch, 3291da177e4SLinus Torvalds .init_irq = noritake_init_irq, 3301da177e4SLinus Torvalds .init_rtc = common_init_rtc, 3311da177e4SLinus Torvalds .init_pci = cia_init_pci, 3321da177e4SLinus Torvalds .kill_arch = cia_kill_arch, 3331da177e4SLinus Torvalds .pci_map_irq = noritake_map_irq, 3341da177e4SLinus Torvalds .pci_swizzle = noritake_swizzle, 3351da177e4SLinus Torvalds }; 3361da177e4SLinus Torvalds ALIAS_MV(noritake_primo) 3371da177e4SLinus Torvalds #endif 338