1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef _ALPHA_PGTABLE_H 3 #define _ALPHA_PGTABLE_H 4 5 #include <asm-generic/pgtable-nopud.h> 6 7 /* 8 * This file contains the functions and defines necessary to modify and use 9 * the Alpha page table tree. 10 * 11 * This hopefully works with any standard Alpha page-size, as defined 12 * in <asm/page.h> (currently 8192). 13 */ 14 #include <linux/mmzone.h> 15 16 #include <asm/page.h> 17 #include <asm/processor.h> /* For TASK_SIZE */ 18 #include <asm/machvec.h> 19 #include <asm/setup.h> 20 #include <linux/page_table_check.h> 21 22 struct mm_struct; 23 struct vm_area_struct; 24 25 /* Certain architectures need to do special things when PTEs 26 * within a page table are directly modified. Thus, the following 27 * hook is made available. 28 */ 29 #define set_pte(pteptr, pteval) ((*(pteptr)) = (pteval)) 30 31 /* PMD_SHIFT determines the size of the area a second-level page table can map */ 32 #define PMD_SHIFT (PAGE_SHIFT + (PAGE_SHIFT-3)) 33 #define PMD_SIZE (1UL << PMD_SHIFT) 34 #define PMD_MASK (~(PMD_SIZE-1)) 35 36 /* PGDIR_SHIFT determines what a third-level page table entry can map */ 37 #define PGDIR_SHIFT (PAGE_SHIFT + 2*(PAGE_SHIFT-3)) 38 #define PGDIR_SIZE (1UL << PGDIR_SHIFT) 39 #define PGDIR_MASK (~(PGDIR_SIZE-1)) 40 41 /* 42 * Entries per page directory level: the Alpha is three-level, with 43 * all levels having a one-page page table. 44 */ 45 #define PTRS_PER_PTE (1UL << (PAGE_SHIFT-3)) 46 #define PTRS_PER_PMD (1UL << (PAGE_SHIFT-3)) 47 #define PTRS_PER_PGD (1UL << (PAGE_SHIFT-3)) 48 #define USER_PTRS_PER_PGD (TASK_SIZE / PGDIR_SIZE) 49 50 /* Number of pointers that fit on a page: this will go away. */ 51 #define PTRS_PER_PAGE (1UL << (PAGE_SHIFT-3)) 52 53 #ifdef CONFIG_ALPHA_LARGE_VMALLOC 54 #define VMALLOC_START 0xfffffe0000000000 55 #else 56 #define VMALLOC_START (-2*PGDIR_SIZE) 57 #endif 58 #define VMALLOC_END (-PGDIR_SIZE) 59 60 /* 61 * OSF/1 PAL-code-imposed page table bits 62 */ 63 #define _PAGE_VALID 0x0001 64 #define _PAGE_FOR 0x0002 /* used for page protection (fault on read) */ 65 #define _PAGE_FOW 0x0004 /* used for page protection (fault on write) */ 66 #define _PAGE_FOE 0x0008 /* used for page protection (fault on exec) */ 67 #define _PAGE_ASM 0x0010 68 #define _PAGE_GH_MASK 0x0060 /* granularity hint, PTE<6:5> */ 69 #define _PAGE_GH_SHIFT 5 70 #define _PAGE_KRE 0x0100 /* kernel read enable, in __ACCESS_BITS */ 71 #define _PAGE_URE 0x0200 /* user read enable, in __ACCESS_BITS */ 72 #define _PAGE_KWE 0x1000 /* kernel write enable, in __DIRTY_BITS */ 73 #define _PAGE_UWE 0x2000 /* user write enable, in __DIRTY_BITS */ 74 75 /* .. and these are ours ... */ 76 #define _PAGE_DIRTY 0x20000 77 #define _PAGE_ACCESSED 0x40000 78 #define _PAGE_SPECIAL 0x80000 79 80 /* We borrow bit 39 to store the exclusive marker in swap PTEs. */ 81 #define _PAGE_SWP_EXCLUSIVE 0x8000000000UL 82 83 /* 84 * NOTE! The "accessed" bit isn't necessarily exact: it can be kept exactly 85 * by software (use the KRE/URE/KWE/UWE bits appropriately), but I'll fake it. 86 * Under Linux/AXP, the "accessed" bit just means "read", and I'll just use 87 * the KRE/URE bits to watch for it. That way we don't need to overload the 88 * KWE/UWE bits with both handling dirty and accessed. 89 * 90 * Note that the kernel uses the accessed bit just to check whether to page 91 * out a page or not, so it doesn't have to be exact anyway. 92 */ 93 94 #define __DIRTY_BITS (_PAGE_DIRTY | _PAGE_KWE | _PAGE_UWE) 95 #define __ACCESS_BITS (_PAGE_ACCESSED | _PAGE_KRE | _PAGE_URE) 96 97 #define _PFN_MASK 0xFFFFFFFF00000000UL 98 99 #define _PAGE_TABLE (_PAGE_VALID | __DIRTY_BITS | __ACCESS_BITS) 100 /* 101 * pte_modify() must preserve the granularity hint, or 102 * hugetlb_change_protection() would turn a block into single-page PTEs. 103 */ 104 #define _PAGE_CHG_MASK (_PFN_MASK | __DIRTY_BITS | __ACCESS_BITS | \ 105 _PAGE_GH_MASK | _PAGE_SPECIAL) 106 107 /* 108 * Granularity hints. A PTE with hint order N is one of a block of 8^N 109 * physically contiguous pages, naturally aligned both virtually and 110 * physically, that the TB may map with a single entry. With 8KB pages the 111 * four encodings give 8KB, 64KB, 512KB and 4MB. 112 * 113 * Every PTE of a block must still carry the PFN of its own page, and all of 114 * them must agree in bits <15:0>: the protection, fault, hint and valid bits. 115 * __ACCESS_BITS and __DIRTY_BITS reach into that range, so young and dirty 116 * updates have to be applied to the whole block too. 117 * 118 * The hint is advisory: an implementation that ignores it still translates 119 * correctly through the individual PTEs, so it is safe to set on any Alpha. 120 */ 121 #define GH_ORDER_MAX 4 /* hint orders 0..3 */ 122 123 #define gh_cont_shift(order) (PAGE_SHIFT + 3 * (order)) 124 #define gh_cont_size(order) (1UL << gh_cont_shift(order)) 125 #define gh_cont_mask(order) (~(gh_cont_size(order) - 1)) 126 #define gh_pte_num(order) (1UL << (3 * (order))) 127 128 #define for_each_gh_order(order) \ 129 for ((order) = 1; (order) < GH_ORDER_MAX; (order)++) 130 131 /* 132 * All the normal masks have the "page accessed" bits on, as any time they are used, 133 * the page is accessed. They are cleared only by the page-out routines 134 */ 135 #define PAGE_NONE __pgprot(_PAGE_VALID | __ACCESS_BITS | _PAGE_FOR | _PAGE_FOW | _PAGE_FOE) 136 #define PAGE_SHARED __pgprot(_PAGE_VALID | __ACCESS_BITS) 137 #define PAGE_COPY __pgprot(_PAGE_VALID | __ACCESS_BITS | _PAGE_FOW) 138 #define PAGE_READONLY __pgprot(_PAGE_VALID | __ACCESS_BITS | _PAGE_FOW) 139 #define PAGE_KERNEL __pgprot(_PAGE_VALID | _PAGE_ASM | _PAGE_KRE | _PAGE_KWE) 140 141 #define _PAGE_NORMAL(x) __pgprot(_PAGE_VALID | __ACCESS_BITS | (x)) 142 143 #define _PAGE_P(x) _PAGE_NORMAL((x) | _PAGE_FOW) 144 #define _PAGE_S(x) _PAGE_NORMAL(x) 145 146 /* 147 * The hardware can handle write-only mappings, but as the Alpha 148 * architecture does byte-wide writes with a read-modify-write 149 * sequence, it's not practical to have write-without-read privs. 150 * Thus the "-w- -> rw-" and "-wx -> rwx" mapping here (and in 151 * arch/alpha/mm/fault.c) 152 */ 153 /* xwr */ 154 155 /* 156 * pgprot_noncached() is only for infiniband pci support, and a real 157 * implementation for RAM would be more complicated. 158 */ 159 #define pgprot_noncached(prot) (prot) 160 161 /* 162 * All caching attribute macros are identity on Alpha, so the generic 163 * pgprot_modify() degenerates to tautological self-comparisons. 164 * Override it to just return newprot directly. 165 */ 166 #define pgprot_modify pgprot_modify 167 static inline pgprot_t pgprot_modify(pgprot_t oldprot, pgprot_t newprot) 168 { 169 return newprot; 170 } 171 172 /* 173 * On certain platforms whose physical address space can overlap KSEG, 174 * namely EV6 and above, we must re-twiddle the physaddr to restore the 175 * correct high-order bits. 176 * 177 * This is extremely confusing until you realize that this is actually 178 * just working around a userspace bug. The X server was intending to 179 * provide the physical address but instead provided the KSEG address. 180 * Or tried to, except it's not representable. 181 * 182 * On Tsunami there's nothing meaningful at 0x40000000000, so this is 183 * a safe thing to do. Come the first core logic that does put something 184 * in this area -- memory or whathaveyou -- then this hack will have 185 * to go away. So be prepared! 186 */ 187 188 #if defined(CONFIG_ALPHA_GENERIC) && defined(USE_48_BIT_KSEG) 189 #error "EV6-only feature in a generic kernel" 190 #endif 191 #if defined(CONFIG_ALPHA_GENERIC) || \ 192 (defined(CONFIG_ALPHA_EV6) && !defined(USE_48_BIT_KSEG)) 193 #define KSEG_PFN (0xc0000000000UL >> PAGE_SHIFT) 194 #define PHYS_TWIDDLE(pfn) \ 195 ((((pfn) & KSEG_PFN) == (0x40000000000UL >> PAGE_SHIFT)) \ 196 ? ((pfn) ^= KSEG_PFN) : (pfn)) 197 #else 198 #define PHYS_TWIDDLE(pfn) (pfn) 199 #endif 200 201 /* 202 * Conversion functions: convert a page and protection to a page entry, 203 * and a page entry and page directory to the page they refer to. 204 */ 205 #define page_to_pa(page) (page_to_pfn(page) << PAGE_SHIFT) 206 #define PFN_PTE_SHIFT 32 207 #define pte_pfn(pte) (pte_val(pte) >> PFN_PTE_SHIFT) 208 209 #define pte_page(pte) pfn_to_page(pte_pfn(pte)) 210 211 extern inline pte_t pfn_pte(unsigned long physpfn, pgprot_t pgprot) 212 { pte_t pte; pte_val(pte) = (PHYS_TWIDDLE(physpfn) << 32) | pgprot_val(pgprot); return pte; } 213 214 extern inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 215 { pte_val(pte) = (pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot); return pte; } 216 217 extern inline void pmd_set(pmd_t * pmdp, pte_t * ptep) 218 { pmd_val(*pmdp) = _PAGE_TABLE | ((((unsigned long) ptep) - PAGE_OFFSET) << (32-PAGE_SHIFT)); } 219 220 extern inline void pud_set(pud_t * pudp, pmd_t * pmdp) 221 { pud_val(*pudp) = _PAGE_TABLE | ((((unsigned long) pmdp) - PAGE_OFFSET) << (32-PAGE_SHIFT)); } 222 223 224 extern void migrate_flush_tlb_page(struct vm_area_struct *vma, 225 unsigned long addr); 226 227 extern inline unsigned long 228 pmd_page_vaddr(pmd_t pmd) 229 { 230 return ((pmd_val(pmd) & _PFN_MASK) >> (32-PAGE_SHIFT)) + PAGE_OFFSET; 231 } 232 233 #define pmd_pfn(pmd) (pmd_val(pmd) >> 32) 234 #define pmd_page(pmd) (pfn_to_page(pmd_val(pmd) >> 32)) 235 #define pud_page(pud) (pfn_to_page(pud_val(pud) >> 32)) 236 237 extern inline pmd_t *pud_pgtable(pud_t pgd) 238 { 239 return (pmd_t *)(PAGE_OFFSET + ((pud_val(pgd) & _PFN_MASK) >> (32-PAGE_SHIFT))); 240 } 241 242 extern inline int pte_none(pte_t pte) { return !pte_val(pte); } 243 extern inline int pte_present(pte_t pte) { return pte_val(pte) & _PAGE_VALID; } 244 extern inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep) 245 { 246 WRITE_ONCE(pte_val(*ptep), 0); 247 } 248 249 extern inline int pmd_none(pmd_t pmd) { return !pmd_val(pmd); } 250 extern inline int pmd_bad(pmd_t pmd) { return (pmd_val(pmd) & ~_PFN_MASK) != _PAGE_TABLE; } 251 extern inline int pmd_present(pmd_t pmd) { return pmd_val(pmd) & _PAGE_VALID; } 252 extern inline void pmd_clear(pmd_t * pmdp) { pmd_val(*pmdp) = 0; } 253 254 extern inline int pud_none(pud_t pud) { return !pud_val(pud); } 255 extern inline int pud_bad(pud_t pud) { return (pud_val(pud) & ~_PFN_MASK) != _PAGE_TABLE; } 256 extern inline int pud_present(pud_t pud) { return pud_val(pud) & _PAGE_VALID; } 257 extern inline void pud_clear(pud_t * pudp) { pud_val(*pudp) = 0; } 258 259 /* 260 * The following only work if pte_present() is true. 261 * Undefined behaviour if not.. 262 */ 263 extern inline int pte_write(pte_t pte) { return !(pte_val(pte) & _PAGE_FOW); } 264 extern inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_DIRTY; } 265 extern inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; } 266 extern inline int pte_user(pte_t pte) { return pte_val(pte) & _PAGE_URE; } 267 268 static inline bool pte_user_accessible_page(struct mm_struct *mm, 269 unsigned long addr, pte_t pte) 270 { 271 return pte_present(pte) && pte_user(pte); 272 } 273 274 static inline bool pmd_user_accessible_page(struct mm_struct *mm, 275 unsigned long addr, pmd_t pmd) 276 { 277 return false; 278 } 279 280 static inline bool pud_user_accessible_page(struct mm_struct *mm, 281 unsigned long addr, pud_t pud) 282 { 283 return false; 284 } 285 286 extern inline pte_t pte_wrprotect(pte_t pte) { pte_val(pte) |= _PAGE_FOW; return pte; } 287 extern inline pte_t pte_mkclean(pte_t pte) { pte_val(pte) &= ~(__DIRTY_BITS); return pte; } 288 extern inline pte_t pte_mkold(pte_t pte) { pte_val(pte) &= ~(__ACCESS_BITS); return pte; } 289 extern inline pte_t pte_mkwrite_novma(pte_t pte){ pte_val(pte) &= ~_PAGE_FOW; return pte; } 290 extern inline pte_t pte_mkdirty(pte_t pte) { pte_val(pte) |= __DIRTY_BITS; return pte; } 291 extern inline pte_t pte_mkyoung(pte_t pte) { pte_val(pte) |= __ACCESS_BITS; return pte; } 292 extern inline int pte_special(pte_t pte) { return pte_val(pte) & _PAGE_SPECIAL; } 293 extern inline pte_t pte_mkspecial(pte_t pte) { pte_val(pte) |= _PAGE_SPECIAL; return pte; } 294 295 extern inline unsigned int pte_gh_order(pte_t pte) 296 { 297 return (pte_val(pte) & _PAGE_GH_MASK) >> _PAGE_GH_SHIFT; 298 } 299 300 extern inline pte_t pte_mkgh(pte_t pte, unsigned int order) 301 { 302 pte_val(pte) &= ~_PAGE_GH_MASK; 303 pte_val(pte) |= (unsigned long)order << _PAGE_GH_SHIFT; 304 return pte; 305 } 306 307 /* 308 * Swap PTEs leave bits <31:0> clear, so this is false for every swap, 309 * migration and marker entry, not just for ordinary small pages. 310 */ 311 extern inline int pte_huge(pte_t pte) { return pte_val(pte) & _PAGE_GH_MASK; } 312 313 /* 314 * The smp_rmb() in the following functions are required to order the load of 315 * *dir (the pointer in the top level page table) with any subsequent load of 316 * the returned pmd_t *ret (ret is data dependent on *dir). 317 * 318 * If this ordering is not enforced, the CPU might load an older value of 319 * *ret, which may be uninitialized data. See mm/memory.c:__pte_alloc for 320 * more details. 321 * 322 * Note that we never change the mm->pgd pointer after the task is running, so 323 * pgd_offset does not require such a barrier. 324 */ 325 326 /* Find an entry in the second-level page table.. */ 327 extern inline pmd_t * pmd_offset(pud_t * dir, unsigned long address) 328 { 329 pmd_t *ret = pud_pgtable(*dir) + ((address >> PMD_SHIFT) & (PTRS_PER_PAGE - 1)); 330 smp_rmb(); /* see above */ 331 return ret; 332 } 333 #define pmd_offset pmd_offset 334 335 /* Find an entry in the third-level page table.. */ 336 extern inline pte_t * pte_offset_kernel(pmd_t * dir, unsigned long address) 337 { 338 pte_t *ret = (pte_t *) pmd_page_vaddr(*dir) 339 + ((address >> PAGE_SHIFT) & (PTRS_PER_PAGE - 1)); 340 smp_rmb(); /* see above */ 341 return ret; 342 } 343 #define pte_offset_kernel pte_offset_kernel 344 345 extern pgd_t swapper_pg_dir[1024]; 346 347 #ifdef CONFIG_COMPACTION 348 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR 349 350 static inline pte_t ptep_get_and_clear(struct mm_struct *mm, 351 unsigned long address, 352 pte_t *ptep) 353 { 354 pte_t pte = READ_ONCE(*ptep); 355 356 pte_clear(mm, address, ptep); 357 page_table_check_pte_clear(mm, address, pte); 358 return pte; 359 } 360 361 #define __HAVE_ARCH_PTEP_CLEAR_FLUSH 362 363 static inline pte_t ptep_clear_flush(struct vm_area_struct *vma, 364 unsigned long addr, pte_t *ptep) 365 { 366 struct mm_struct *mm = vma->vm_mm; 367 pte_t pte = ptep_get_and_clear(mm, addr, ptep); 368 369 migrate_flush_tlb_page(vma, addr); 370 return pte; 371 } 372 373 #endif 374 /* 375 * The Alpha doesn't have any external MMU info: the kernel page 376 * tables contain all the necessary information. 377 */ 378 extern inline void update_mmu_cache(struct vm_area_struct * vma, 379 unsigned long address, pte_t *ptep) 380 { 381 } 382 383 static inline void update_mmu_cache_range(struct vm_fault *vmf, 384 struct vm_area_struct *vma, unsigned long address, 385 pte_t *ptep, unsigned int nr) 386 { 387 } 388 389 /* 390 * Encode/decode swap entries and swap PTEs. Swap PTEs are all PTEs that 391 * are !pte_none() && !pte_present(). 392 * 393 * Format of swap PTEs: 394 * 395 * 6 6 6 6 5 5 5 5 5 5 5 5 5 5 4 4 4 4 4 4 4 4 4 4 3 3 3 3 3 3 3 3 396 * 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 397 * <------------------- offset ------------------> E <--- type --> 398 * 399 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 400 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 401 * <--------------------------- zeroes --------------------------> 402 * 403 * E is the exclusive marker that is not stored in swap entries. 404 */ 405 extern inline pte_t mk_swap_pte(unsigned long type, unsigned long offset) 406 { pte_t pte; pte_val(pte) = ((type & 0x7f) << 32) | (offset << 40); return pte; } 407 408 #define __swp_type(x) (((x).val >> 32) & 0x7f) 409 #define __swp_offset(x) ((x).val >> 40) 410 #define __swp_entry(type, off) ((swp_entry_t) { pte_val(mk_swap_pte((type), (off))) }) 411 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) 412 #define __swp_entry_to_pte(x) ((pte_t) { (x).val }) 413 414 static inline bool pte_swp_exclusive(pte_t pte) 415 { 416 return pte_val(pte) & _PAGE_SWP_EXCLUSIVE; 417 } 418 419 static inline pte_t pte_swp_mkexclusive(pte_t pte) 420 { 421 pte_val(pte) |= _PAGE_SWP_EXCLUSIVE; 422 return pte; 423 } 424 425 static inline pte_t pte_swp_clear_exclusive(pte_t pte) 426 { 427 pte_val(pte) &= ~_PAGE_SWP_EXCLUSIVE; 428 return pte; 429 } 430 431 #define pte_ERROR(e) \ 432 printk("%s:%d: bad pte %016lx.\n", __FILE__, __LINE__, pte_val(e)) 433 #define pmd_ERROR(e) \ 434 printk("%s:%d: bad pmd %016lx.\n", __FILE__, __LINE__, pmd_val(e)) 435 #define pgd_ERROR(e) \ 436 printk("%s:%d: bad pgd %016lx.\n", __FILE__, __LINE__, pgd_val(e)) 437 438 extern void paging_init(void); 439 440 /* We have our own get_unmapped_area */ 441 #define HAVE_ARCH_UNMAPPED_AREA 442 443 #endif /* _ALPHA_PGTABLE_H */ 444