1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef __ALPHA_MMU_CONTEXT_H 3 #define __ALPHA_MMU_CONTEXT_H 4 5 /* 6 * get a new mmu context.. 7 * 8 * Copyright (C) 1996, Linus Torvalds 9 */ 10 11 #include <linux/mm_types.h> 12 #include <linux/sched.h> 13 14 #include <asm/machvec.h> 15 #include <asm/compiler.h> 16 #include <asm-generic/mm_hooks.h> 17 18 /* 19 * Force a context reload. This is needed when we change the page 20 * table pointer or when we update the ASN of the current process. 21 */ 22 23 /* Don't get into trouble with dueling __EXTERN_INLINEs. */ 24 #ifndef __EXTERN_INLINE 25 #include <asm/io.h> 26 #endif 27 28 29 static inline unsigned long 30 __reload_thread(struct pcb_struct *pcb) 31 { 32 register unsigned long a0 __asm__("$16"); 33 register unsigned long v0 __asm__("$0"); 34 35 a0 = virt_to_phys(pcb); 36 __asm__ __volatile__( 37 "call_pal %2 #__reload_thread" 38 : "=r"(v0), "=r"(a0) 39 : "i"(PAL_swpctx), "r"(a0) 40 : "$1", "$22", "$23", "$24", "$25"); 41 42 return v0; 43 } 44 45 46 /* 47 * The maximum ASN's the processor supports. On the EV4 this is 63 48 * but the PAL-code doesn't actually use this information. On the 49 * EV5 this is 127, and EV6 has 255. 50 * 51 * On the EV4, the ASNs are more-or-less useless anyway, as they are 52 * only used as an icache tag, not for TB entries. On the EV5 and EV6, 53 * ASN's also validate the TB entries, and thus make a lot more sense. 54 * 55 * The EV4 ASN's don't even match the architecture manual, ugh. And 56 * I quote: "If a processor implements address space numbers (ASNs), 57 * and the old PTE has the Address Space Match (ASM) bit clear (ASNs 58 * in use) and the Valid bit set, then entries can also effectively be 59 * made coherent by assigning a new, unused ASN to the currently 60 * running process and not reusing the previous ASN before calling the 61 * appropriate PALcode routine to invalidate the translation buffer (TB)". 62 * 63 * In short, the EV4 has a "kind of" ASN capability, but it doesn't actually 64 * work correctly and can thus not be used (explaining the lack of PAL-code 65 * support). 66 */ 67 #define EV4_MAX_ASN 63 68 #define EV5_MAX_ASN 127 69 #define EV6_MAX_ASN 255 70 71 #ifdef CONFIG_ALPHA_GENERIC 72 # define MAX_ASN (alpha_mv.max_asn) 73 #else 74 # if defined(CONFIG_ALPHA_EV56) 75 # define MAX_ASN EV5_MAX_ASN 76 # else 77 # define MAX_ASN EV6_MAX_ASN 78 # endif 79 #endif 80 81 /* 82 * cpu_last_asn(processor): 83 * 63 0 84 * +-------------+----------------+--------------+ 85 * | asn version | this processor | hardware asn | 86 * +-------------+----------------+--------------+ 87 */ 88 89 #include <asm/smp.h> 90 #ifdef CONFIG_SMP 91 #define cpu_last_asn(cpuid) (cpu_data[cpuid].last_asn) 92 #else 93 extern unsigned long last_asn; 94 #define cpu_last_asn(cpuid) last_asn 95 #endif /* CONFIG_SMP */ 96 97 #define WIDTH_HARDWARE_ASN 8 98 #define ASN_FIRST_VERSION (1UL << WIDTH_HARDWARE_ASN) 99 #define HARDWARE_ASN_MASK ((1UL << WIDTH_HARDWARE_ASN) - 1) 100 101 /* 102 * NOTE! The way this is set up, the high bits of the "asn_cache" (and 103 * the "mm->context") are the ASN _version_ code. A version of 0 is 104 * always considered invalid, so to invalidate another process you only 105 * need to do "p->mm->context = 0". 106 * 107 * If we need more ASN's than the processor has, we invalidate the old 108 * user TLB's (tbiap()) and start a new ASN version. That will automatically 109 * force a new asn for any other processes the next time they want to 110 * run. 111 */ 112 113 #ifndef __EXTERN_INLINE 114 #define __EXTERN_INLINE extern inline 115 #define __MMU_EXTERN_INLINE 116 #endif 117 118 extern inline unsigned long 119 __get_new_mm_context(struct mm_struct *mm, long cpu) 120 { 121 unsigned long asn = cpu_last_asn(cpu); 122 unsigned long next = asn + 1; 123 124 if ((asn & HARDWARE_ASN_MASK) >= MAX_ASN) { 125 tbiap(); 126 imb(); 127 next = (asn & ~HARDWARE_ASN_MASK) + ASN_FIRST_VERSION; 128 } 129 cpu_last_asn(cpu) = next; 130 return next; 131 } 132 133 extern void __load_new_mm_context(struct mm_struct *); 134 135 __EXTERN_INLINE void 136 ev5_switch_mm(struct mm_struct *prev_mm, struct mm_struct *next_mm, 137 struct task_struct *next) 138 { 139 /* Check if our ASN is of an older version, and thus invalid. */ 140 unsigned long asn; 141 unsigned long mmc; 142 long cpu = smp_processor_id(); 143 144 /* 145 * kthread_use_mm(), sched_force_init_mm() and do_shoot_lazy_tlb() 146 * switch current's mm without alpha_switch_to(), which loads the 147 * context. The latter two require options Alpha does not select. 148 */ 149 if (next == current) { 150 __load_new_mm_context(next_mm); 151 return; 152 } 153 154 #ifdef CONFIG_SMP 155 cpu_data[cpu].asn_lock = 1; 156 barrier(); 157 #endif 158 asn = cpu_last_asn(cpu); 159 mmc = next_mm->context[cpu]; 160 if ((mmc ^ asn) & ~HARDWARE_ASN_MASK) { 161 mmc = __get_new_mm_context(next_mm, cpu); 162 /* 163 * Ordered before any user access through the mm by the 164 * mb() in arch_spin_unlock(), when finish_lock_switch() 165 * drops the rq lock. 166 */ 167 WRITE_ONCE(next_mm->context[cpu], mmc); 168 } 169 #ifdef CONFIG_SMP 170 /* A deferred shootdown can also invalidate a newly allocated ASN. */ 171 cpu_data[cpu].need_new_asn = 1; 172 #endif 173 174 /* Always update the PCB ASN. Another thread may have allocated 175 a new mm->context (via flush_tlb_mm) without the ASN serial 176 number wrapping. We have no way to detect when this is needed. */ 177 task_thread_info(next)->pcb.asn = mmc & HARDWARE_ASN_MASK; 178 } 179 180 asmlinkage void do_page_fault(unsigned long address, unsigned long mmcsr, 181 long cause, struct pt_regs *regs); 182 183 #ifdef CONFIG_SMP 184 #define check_mmu_context() \ 185 do { \ 186 int cpu = smp_processor_id(); \ 187 cpu_data[cpu].asn_lock = 0; \ 188 barrier(); \ 189 if (cpu_data[cpu].need_new_asn) { \ 190 struct mm_struct * mm = current->active_mm; \ 191 cpu_data[cpu].need_new_asn = 0; \ 192 if (!mm->context[cpu]) \ 193 __load_new_mm_context(mm); \ 194 } \ 195 } while(0) 196 #else 197 #define check_mmu_context() do { } while(0) 198 #endif 199 200 /* 201 * Also called from kthread_use_mm() with preemption enabled. Alpha has 202 * no kernel preemption, so the task is still on the CPU that ran 203 * switch_mm(). 204 */ 205 #define finish_arch_post_lock_switch finish_arch_post_lock_switch 206 static inline void finish_arch_post_lock_switch(void) 207 { 208 check_mmu_context(); 209 } 210 211 __EXTERN_INLINE void 212 ev5_activate_mm(struct mm_struct *prev_mm, struct mm_struct *next_mm) 213 { 214 __load_new_mm_context(next_mm); 215 } 216 217 #define switch_mm(a,b,c) ev5_switch_mm((a),(b),(c)) 218 #define activate_mm(x,y) ev5_activate_mm((x),(y)) 219 220 #define init_new_context init_new_context 221 static inline int 222 init_new_context(struct task_struct *tsk, struct mm_struct *mm) 223 { 224 int i; 225 226 for_each_online_cpu(i) 227 mm->context[i] = 0; 228 if (tsk != current) 229 task_thread_info(tsk)->pcb.ptbr 230 = ((unsigned long)mm->pgd - IDENT_ADDR) >> PAGE_SHIFT; 231 return 0; 232 } 233 234 #define enter_lazy_tlb enter_lazy_tlb 235 static inline void 236 enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk) 237 { 238 task_thread_info(tsk)->pcb.ptbr 239 = ((unsigned long)mm->pgd - IDENT_ADDR) >> PAGE_SHIFT; 240 } 241 242 #include <asm-generic/mmu_context.h> 243 244 #ifdef __MMU_EXTERN_INLINE 245 #undef __EXTERN_INLINE 246 #undef __MMU_EXTERN_INLINE 247 #endif 248 249 #endif /* __ALPHA_MMU_CONTEXT_H */ 250