1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef __ALPHA_IO_H 3 #define __ALPHA_IO_H 4 5 #ifdef __KERNEL__ 6 7 #include <linux/kernel.h> 8 #include <linux/mm.h> 9 #include <asm/compiler.h> 10 #include <asm/machvec.h> 11 #include <asm/hwrpb.h> 12 13 /* The generic header contains only prototypes. Including it ensures that 14 the implementation we have here matches that interface. */ 15 #include <asm-generic/iomap.h> 16 17 /* 18 * Virtual -> physical identity mapping starts at this offset 19 */ 20 #ifdef USE_48_BIT_KSEG 21 #define IDENT_ADDR 0xffff800000000000UL 22 #else 23 #define IDENT_ADDR 0xfffffc0000000000UL 24 #endif 25 26 /* 27 * We try to avoid hae updates (thus the cache), but when we 28 * do need to update the hae, we need to do it atomically, so 29 * that any interrupts wouldn't get confused with the hae 30 * register not being up-to-date with respect to the hardware 31 * value. 32 */ 33 extern inline void __set_hae(unsigned long new_hae) 34 { 35 unsigned long flags = swpipl(IPL_MAX); 36 37 barrier(); 38 39 alpha_mv.hae_cache = new_hae; 40 *alpha_mv.hae_register = new_hae; 41 mb(); 42 /* Re-read to make sure it was written. */ 43 new_hae = *alpha_mv.hae_register; 44 45 setipl(flags); 46 barrier(); 47 } 48 49 extern inline void set_hae(unsigned long new_hae) 50 { 51 if (new_hae != alpha_mv.hae_cache) 52 __set_hae(new_hae); 53 } 54 55 /* 56 * Change virtual addresses to physical addresses and vv. 57 */ 58 #ifdef USE_48_BIT_KSEG 59 static inline unsigned long virt_to_phys(volatile void *address) 60 { 61 return (unsigned long)address - IDENT_ADDR; 62 } 63 64 static inline void * phys_to_virt(unsigned long address) 65 { 66 return (void *) (address + IDENT_ADDR); 67 } 68 #else 69 static inline unsigned long virt_to_phys(volatile void *address) 70 { 71 unsigned long phys = (unsigned long)address; 72 73 /* Sign-extend from bit 41. */ 74 phys <<= (64 - 41); 75 phys = (long)phys >> (64 - 41); 76 77 /* Crop to the physical address width of the processor. */ 78 phys &= (1ul << hwrpb->pa_bits) - 1; 79 80 return phys; 81 } 82 83 static inline void * phys_to_virt(unsigned long address) 84 { 85 return (void *)(IDENT_ADDR + (address & ((1ul << 41) - 1))); 86 } 87 #endif 88 89 #define virt_to_phys virt_to_phys 90 #define phys_to_virt phys_to_virt 91 #define page_to_phys(page) page_to_pa(page) 92 93 /* Maximum PIO space address supported? */ 94 #define IO_SPACE_LIMIT 0xffff 95 96 /* 97 * Change addresses as seen by the kernel (virtual) to addresses as 98 * seen by a device (bus), and vice versa. 99 * 100 * Note that this only works for a limited range of kernel addresses, 101 * and very well may not span all memory. Consider this interface 102 * deprecated in favour of the DMA-mapping API. 103 */ 104 extern unsigned long __direct_map_base; 105 extern unsigned long __direct_map_size; 106 107 static inline unsigned long __deprecated isa_virt_to_bus(volatile void *address) 108 { 109 unsigned long phys = virt_to_phys(address); 110 unsigned long bus = phys + __direct_map_base; 111 return phys <= __direct_map_size ? bus : 0; 112 } 113 #define isa_virt_to_bus isa_virt_to_bus 114 115 static inline void * __deprecated isa_bus_to_virt(unsigned long address) 116 { 117 void *virt; 118 119 /* This check is a sanity check but also ensures that bus address 0 120 maps to virtual address 0 which is useful to detect null pointers 121 (the NCR driver is much simpler if NULL pointers are preserved). */ 122 address -= __direct_map_base; 123 virt = phys_to_virt(address); 124 return (long)address <= 0 ? NULL : virt; 125 } 126 #define isa_bus_to_virt isa_bus_to_virt 127 128 /* 129 * There are different chipsets to interface the Alpha CPUs to the world. 130 */ 131 132 #define IO_CONCAT(a,b) _IO_CONCAT(a,b) 133 #define _IO_CONCAT(a,b) a ## _ ## b 134 135 #ifdef CONFIG_ALPHA_GENERIC 136 137 /* In a generic kernel, we always go through the machine vector. */ 138 139 #define REMAP1(TYPE, NAME, QUAL) \ 140 static inline TYPE generic_##NAME(QUAL void __iomem *addr) \ 141 { \ 142 return alpha_mv.mv_##NAME(addr); \ 143 } 144 145 #define REMAP2(TYPE, NAME, QUAL) \ 146 static inline void generic_##NAME(TYPE b, QUAL void __iomem *addr) \ 147 { \ 148 alpha_mv.mv_##NAME(b, addr); \ 149 } 150 151 REMAP1(unsigned int, ioread8, const) 152 REMAP1(unsigned int, ioread16, const) 153 REMAP1(unsigned int, ioread32, const) 154 REMAP1(u64, ioread64, const) 155 REMAP1(u8, readb, const volatile) 156 REMAP1(u16, readw, const volatile) 157 REMAP1(u32, readl, const volatile) 158 REMAP1(u64, readq, const volatile) 159 160 REMAP2(u8, iowrite8, /**/) 161 REMAP2(u16, iowrite16, /**/) 162 REMAP2(u32, iowrite32, /**/) 163 REMAP2(u64, iowrite64, /**/) 164 REMAP2(u8, writeb, volatile) 165 REMAP2(u16, writew, volatile) 166 REMAP2(u32, writel, volatile) 167 REMAP2(u64, writeq, volatile) 168 169 #undef REMAP1 170 #undef REMAP2 171 172 extern inline void __iomem *generic_ioportmap(unsigned long a) 173 { 174 return alpha_mv.mv_ioportmap(a); 175 } 176 177 static inline void __iomem *generic_ioremap(unsigned long a, unsigned long s) 178 { 179 return alpha_mv.mv_ioremap(a, s); 180 } 181 182 static inline void generic_iounmap(volatile void __iomem *a) 183 { 184 return alpha_mv.mv_iounmap(a); 185 } 186 187 static inline int generic_is_ioaddr(unsigned long a) 188 { 189 return alpha_mv.mv_is_ioaddr(a); 190 } 191 192 static inline int generic_is_mmio(const volatile void __iomem *a) 193 { 194 return alpha_mv.mv_is_mmio(a); 195 } 196 197 #define __IO_PREFIX generic 198 #define generic_trivial_rw_bw 0 199 #define generic_trivial_rw_lq 0 200 #define generic_trivial_io_bw 0 201 #define generic_trivial_io_lq 0 202 #define generic_trivial_iounmap 0 203 204 #else 205 206 #if defined(CONFIG_ALPHA_APECS) 207 # include <asm/core_apecs.h> 208 #elif defined(CONFIG_ALPHA_CIA) 209 # include <asm/core_cia.h> 210 #elif defined(CONFIG_ALPHA_IRONGATE) 211 # include <asm/core_irongate.h> 212 #elif defined(CONFIG_ALPHA_LCA) 213 # include <asm/core_lca.h> 214 #elif defined(CONFIG_ALPHA_MARVEL) 215 # include <asm/core_marvel.h> 216 #elif defined(CONFIG_ALPHA_MCPCIA) 217 # include <asm/core_mcpcia.h> 218 #elif defined(CONFIG_ALPHA_POLARIS) 219 # include <asm/core_polaris.h> 220 #elif defined(CONFIG_ALPHA_T2) 221 # include <asm/core_t2.h> 222 #elif defined(CONFIG_ALPHA_TSUNAMI) 223 # include <asm/core_tsunami.h> 224 #elif defined(CONFIG_ALPHA_TITAN) 225 # include <asm/core_titan.h> 226 #elif defined(CONFIG_ALPHA_WILDFIRE) 227 # include <asm/core_wildfire.h> 228 #else 229 #error "What system is this?" 230 #endif 231 232 #endif /* GENERIC */ 233 234 /* 235 * We always have external versions of these routines. 236 */ 237 extern u8 inb(unsigned long port); 238 extern u16 inw(unsigned long port); 239 extern u32 inl(unsigned long port); 240 extern void outb(u8 b, unsigned long port); 241 extern void outw(u16 b, unsigned long port); 242 extern void outl(u32 b, unsigned long port); 243 #define inb inb 244 #define inw inw 245 #define inl inl 246 #define outb outb 247 #define outw outw 248 #define outl outl 249 250 extern u8 readb(const volatile void __iomem *addr); 251 extern u16 readw(const volatile void __iomem *addr); 252 extern u32 readl(const volatile void __iomem *addr); 253 extern u64 readq(const volatile void __iomem *addr); 254 extern void writeb(u8 b, volatile void __iomem *addr); 255 extern void writew(u16 b, volatile void __iomem *addr); 256 extern void writel(u32 b, volatile void __iomem *addr); 257 extern void writeq(u64 b, volatile void __iomem *addr); 258 #define readb readb 259 #define readw readw 260 #define readl readl 261 #define readq readq 262 #define writeb writeb 263 #define writew writew 264 #define writel writel 265 #define writeq writeq 266 267 extern u8 __raw_readb(const volatile void __iomem *addr); 268 extern u16 __raw_readw(const volatile void __iomem *addr); 269 extern u32 __raw_readl(const volatile void __iomem *addr); 270 extern u64 __raw_readq(const volatile void __iomem *addr); 271 extern void __raw_writeb(u8 b, volatile void __iomem *addr); 272 extern void __raw_writew(u16 b, volatile void __iomem *addr); 273 extern void __raw_writel(u32 b, volatile void __iomem *addr); 274 extern void __raw_writeq(u64 b, volatile void __iomem *addr); 275 #define __raw_readb __raw_readb 276 #define __raw_readw __raw_readw 277 #define __raw_readl __raw_readl 278 #define __raw_readq __raw_readq 279 #define __raw_writeb __raw_writeb 280 #define __raw_writew __raw_writew 281 #define __raw_writel __raw_writel 282 #define __raw_writeq __raw_writeq 283 284 /* 285 * Mapping from port numbers to __iomem space is pretty easy. 286 */ 287 288 /* These two have to be extern inline because of the extern prototype from 289 <asm-generic/iomap.h>. It is not legal to mix "extern" and "static" for 290 the same declaration. */ 291 extern inline void __iomem *ioport_map(unsigned long port, unsigned int size) 292 { 293 return IO_CONCAT(__IO_PREFIX,ioportmap) (port); 294 } 295 296 extern inline void ioport_unmap(void __iomem *addr) 297 { 298 } 299 300 #define ioport_map ioport_map 301 #define ioport_unmap ioport_unmap 302 303 static inline void __iomem *ioremap(unsigned long port, unsigned long size) 304 { 305 return IO_CONCAT(__IO_PREFIX,ioremap) (port, size); 306 } 307 308 #define ioremap_wc ioremap 309 310 static inline void iounmap(volatile void __iomem *addr) 311 { 312 IO_CONCAT(__IO_PREFIX,iounmap)(addr); 313 } 314 315 static inline int __is_ioaddr(unsigned long addr) 316 { 317 return IO_CONCAT(__IO_PREFIX,is_ioaddr)(addr); 318 } 319 #define __is_ioaddr(a) __is_ioaddr((unsigned long)(a)) 320 321 static inline int __is_mmio(const volatile void __iomem *addr) 322 { 323 return IO_CONCAT(__IO_PREFIX,is_mmio)(addr); 324 } 325 326 327 /* 328 * If the actual I/O bits are sufficiently trivial, then expand inline. 329 */ 330 331 #if IO_CONCAT(__IO_PREFIX,trivial_io_bw) 332 extern inline unsigned int ioread8(const void __iomem *addr) 333 { 334 unsigned int ret; 335 mb(); 336 ret = IO_CONCAT(__IO_PREFIX,ioread8)(addr); 337 mb(); 338 return ret; 339 } 340 341 extern inline unsigned int ioread16(const void __iomem *addr) 342 { 343 unsigned int ret; 344 mb(); 345 ret = IO_CONCAT(__IO_PREFIX,ioread16)(addr); 346 mb(); 347 return ret; 348 } 349 350 extern inline void iowrite8(u8 b, void __iomem *addr) 351 { 352 mb(); 353 IO_CONCAT(__IO_PREFIX, iowrite8)(b, addr); 354 } 355 356 extern inline void iowrite16(u16 b, void __iomem *addr) 357 { 358 mb(); 359 IO_CONCAT(__IO_PREFIX, iowrite16)(b, addr); 360 } 361 362 extern inline u8 inb(unsigned long port) 363 { 364 return ioread8(ioport_map(port, 1)); 365 } 366 367 extern inline u16 inw(unsigned long port) 368 { 369 return ioread16(ioport_map(port, 2)); 370 } 371 372 extern inline void outb(u8 b, unsigned long port) 373 { 374 iowrite8(b, ioport_map(port, 1)); 375 } 376 377 extern inline void outw(u16 b, unsigned long port) 378 { 379 iowrite16(b, ioport_map(port, 2)); 380 } 381 #endif 382 383 #define ioread8 ioread8 384 #define ioread16 ioread16 385 #define iowrite8 iowrite8 386 #define iowrite16 iowrite16 387 388 #if IO_CONCAT(__IO_PREFIX,trivial_io_lq) 389 extern inline unsigned int ioread32(const void __iomem *addr) 390 { 391 unsigned int ret; 392 mb(); 393 ret = IO_CONCAT(__IO_PREFIX,ioread32)(addr); 394 mb(); 395 return ret; 396 } 397 398 extern inline u64 ioread64(const void __iomem *addr) 399 { 400 unsigned int ret; 401 mb(); 402 ret = IO_CONCAT(__IO_PREFIX,ioread64)(addr); 403 mb(); 404 return ret; 405 } 406 407 extern inline void iowrite32(u32 b, void __iomem *addr) 408 { 409 mb(); 410 IO_CONCAT(__IO_PREFIX, iowrite32)(b, addr); 411 } 412 413 extern inline void iowrite64(u64 b, void __iomem *addr) 414 { 415 mb(); 416 IO_CONCAT(__IO_PREFIX, iowrite64)(b, addr); 417 } 418 419 extern inline u32 inl(unsigned long port) 420 { 421 return ioread32(ioport_map(port, 4)); 422 } 423 424 extern inline void outl(u32 b, unsigned long port) 425 { 426 iowrite32(b, ioport_map(port, 4)); 427 } 428 #endif 429 430 #define ioread32 ioread32 431 #define ioread64 ioread64 432 #define iowrite32 iowrite32 433 #define iowrite64 iowrite64 434 435 #if IO_CONCAT(__IO_PREFIX,trivial_rw_bw) == 1 436 extern inline u8 __raw_readb(const volatile void __iomem *addr) 437 { 438 return IO_CONCAT(__IO_PREFIX,readb)(addr); 439 } 440 441 extern inline u16 __raw_readw(const volatile void __iomem *addr) 442 { 443 return IO_CONCAT(__IO_PREFIX,readw)(addr); 444 } 445 446 extern inline void __raw_writeb(u8 b, volatile void __iomem *addr) 447 { 448 IO_CONCAT(__IO_PREFIX,writeb)(b, addr); 449 } 450 451 extern inline void __raw_writew(u16 b, volatile void __iomem *addr) 452 { 453 IO_CONCAT(__IO_PREFIX,writew)(b, addr); 454 } 455 456 extern inline u8 readb(const volatile void __iomem *addr) 457 { 458 u8 ret; 459 mb(); 460 ret = __raw_readb(addr); 461 mb(); 462 return ret; 463 } 464 465 extern inline u16 readw(const volatile void __iomem *addr) 466 { 467 u16 ret; 468 mb(); 469 ret = __raw_readw(addr); 470 mb(); 471 return ret; 472 } 473 474 extern inline void writeb(u8 b, volatile void __iomem *addr) 475 { 476 mb(); 477 __raw_writeb(b, addr); 478 } 479 480 extern inline void writew(u16 b, volatile void __iomem *addr) 481 { 482 mb(); 483 __raw_writew(b, addr); 484 } 485 #endif 486 487 #if IO_CONCAT(__IO_PREFIX,trivial_rw_lq) == 1 488 extern inline u32 __raw_readl(const volatile void __iomem *addr) 489 { 490 return IO_CONCAT(__IO_PREFIX,readl)(addr); 491 } 492 493 extern inline u64 __raw_readq(const volatile void __iomem *addr) 494 { 495 return IO_CONCAT(__IO_PREFIX,readq)(addr); 496 } 497 498 extern inline void __raw_writel(u32 b, volatile void __iomem *addr) 499 { 500 IO_CONCAT(__IO_PREFIX,writel)(b, addr); 501 } 502 503 extern inline void __raw_writeq(u64 b, volatile void __iomem *addr) 504 { 505 IO_CONCAT(__IO_PREFIX,writeq)(b, addr); 506 } 507 508 extern inline u32 readl(const volatile void __iomem *addr) 509 { 510 u32 ret; 511 mb(); 512 ret = __raw_readl(addr); 513 mb(); 514 return ret; 515 } 516 517 extern inline u64 readq(const volatile void __iomem *addr) 518 { 519 u64 ret; 520 mb(); 521 ret = __raw_readq(addr); 522 mb(); 523 return ret; 524 } 525 526 extern inline void writel(u32 b, volatile void __iomem *addr) 527 { 528 mb(); 529 __raw_writel(b, addr); 530 } 531 532 extern inline void writeq(u64 b, volatile void __iomem *addr) 533 { 534 mb(); 535 __raw_writeq(b, addr); 536 } 537 #endif 538 539 #define ioread16be(p) swab16(ioread16(p)) 540 #define ioread32be(p) swab32(ioread32(p)) 541 #define iowrite16be(v,p) iowrite16(swab16(v), (p)) 542 #define iowrite32be(v,p) iowrite32(swab32(v), (p)) 543 544 #define inb_p inb 545 #define inw_p inw 546 #define inl_p inl 547 #define outb_p outb 548 #define outw_p outw 549 #define outl_p outl 550 551 extern u8 readb_relaxed(const volatile void __iomem *addr); 552 extern u16 readw_relaxed(const volatile void __iomem *addr); 553 extern u32 readl_relaxed(const volatile void __iomem *addr); 554 extern u64 readq_relaxed(const volatile void __iomem *addr); 555 #define readb_relaxed readb_relaxed 556 #define readw_relaxed readw_relaxed 557 #define readl_relaxed readl_relaxed 558 #define readq_relaxed readq_relaxed 559 560 #if IO_CONCAT(__IO_PREFIX,trivial_io_bw) 561 extern inline u8 readb_relaxed(const volatile void __iomem *addr) 562 { 563 mb(); 564 return __raw_readb(addr); 565 } 566 567 extern inline u16 readw_relaxed(const volatile void __iomem *addr) 568 { 569 mb(); 570 return __raw_readw(addr); 571 } 572 #endif 573 574 #if IO_CONCAT(__IO_PREFIX,trivial_io_lq) 575 extern inline u32 readl_relaxed(const volatile void __iomem *addr) 576 { 577 mb(); 578 return __raw_readl(addr); 579 } 580 581 extern inline u64 readq_relaxed(const volatile void __iomem *addr) 582 { 583 mb(); 584 return __raw_readq(addr); 585 } 586 #endif 587 588 #define writeb_relaxed writeb 589 #define writew_relaxed writew 590 #define writel_relaxed writel 591 #define writeq_relaxed writeq 592 593 /* 594 * String version of IO memory access ops: 595 */ 596 extern void memcpy_fromio(void *, const volatile void __iomem *, long); 597 extern void memcpy_toio(volatile void __iomem *, const void *, long); 598 extern void _memset_c_io(volatile void __iomem *, unsigned long, long); 599 600 static inline void memset_io(volatile void __iomem *addr, u8 c, long len) 601 { 602 _memset_c_io(addr, 0x0101010101010101UL * c, len); 603 } 604 605 #define __HAVE_ARCH_MEMSETW_IO 606 static inline void memsetw_io(volatile void __iomem *addr, u16 c, long len) 607 { 608 _memset_c_io(addr, 0x0001000100010001UL * c, len); 609 } 610 611 #define memset_io memset_io 612 #define memcpy_fromio memcpy_fromio 613 #define memcpy_toio memcpy_toio 614 615 /* 616 * String versions of in/out ops: 617 */ 618 extern void insb (unsigned long port, void *dst, unsigned long count); 619 extern void insw (unsigned long port, void *dst, unsigned long count); 620 extern void insl (unsigned long port, void *dst, unsigned long count); 621 extern void outsb (unsigned long port, const void *src, unsigned long count); 622 extern void outsw (unsigned long port, const void *src, unsigned long count); 623 extern void outsl (unsigned long port, const void *src, unsigned long count); 624 625 #define insb insb 626 #define insw insw 627 #define insl insl 628 #define outsb outsb 629 #define outsw outsw 630 #define outsl outsl 631 632 #define RTC_PORT(x) (0x70 + (x)) 633 #define RTC_ALWAYS_BCD 0 634 635 /* 636 * These get provided from <asm-generic/iomap.h> since alpha does not 637 * select GENERIC_IOMAP. 638 */ 639 #define ioread64 ioread64 640 #define iowrite64 iowrite64 641 #define ioread64be ioread64be 642 #define iowrite64be iowrite64be 643 #define ioread8_rep ioread8_rep 644 #define ioread16_rep ioread16_rep 645 #define ioread32_rep ioread32_rep 646 #define iowrite8_rep iowrite8_rep 647 #define iowrite16_rep iowrite16_rep 648 #define iowrite32_rep iowrite32_rep 649 #define pci_iounmap pci_iounmap 650 651 #include <asm-generic/io.h> 652 653 #endif /* __KERNEL__ */ 654 655 #endif /* __ALPHA_IO_H */ 656