1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef __ALPHA_IO_H 3 #define __ALPHA_IO_H 4 5 #ifdef __KERNEL__ 6 7 #include <linux/kernel.h> 8 #include <linux/mm.h> 9 #include <asm/compiler.h> 10 #include <asm/machvec.h> 11 #include <asm/hwrpb.h> 12 13 /* The generic header contains only prototypes. Including it ensures that 14 the implementation we have here matches that interface. */ 15 #include <asm-generic/iomap.h> 16 17 /* 18 * Virtual -> physical identity mapping starts at this offset 19 */ 20 #ifdef USE_48_BIT_KSEG 21 #define IDENT_ADDR 0xffff800000000000UL 22 #else 23 #define IDENT_ADDR 0xfffffc0000000000UL 24 #endif 25 26 /* 27 * We try to avoid hae updates (thus the cache), but when we 28 * do need to update the hae, we need to do it atomically, so 29 * that any interrupts wouldn't get confused with the hae 30 * register not being up-to-date with respect to the hardware 31 * value. 32 */ 33 extern inline void __set_hae(unsigned long new_hae) 34 { 35 unsigned long flags = swpipl(IPL_MAX); 36 37 barrier(); 38 39 alpha_mv.hae_cache = new_hae; 40 *alpha_mv.hae_register = new_hae; 41 mb(); 42 /* Re-read to make sure it was written. */ 43 new_hae = *alpha_mv.hae_register; 44 45 setipl(flags); 46 barrier(); 47 } 48 49 extern inline void set_hae(unsigned long new_hae) 50 { 51 if (new_hae != alpha_mv.hae_cache) 52 __set_hae(new_hae); 53 } 54 55 /* 56 * Change virtual addresses to physical addresses and vv. 57 */ 58 #ifdef USE_48_BIT_KSEG 59 static inline unsigned long virt_to_phys(volatile void *address) 60 { 61 return (unsigned long)address - IDENT_ADDR; 62 } 63 64 static inline void * phys_to_virt(unsigned long address) 65 { 66 return (void *) (address + IDENT_ADDR); 67 } 68 #else 69 static inline unsigned long virt_to_phys(volatile void *address) 70 { 71 unsigned long phys = (unsigned long)address; 72 73 /* Sign-extend from bit 41. */ 74 phys <<= (64 - 41); 75 phys = (long)phys >> (64 - 41); 76 77 /* Crop to the physical address width of the processor. */ 78 phys &= (1ul << hwrpb->pa_bits) - 1; 79 80 return phys; 81 } 82 83 static inline void * phys_to_virt(unsigned long address) 84 { 85 return (void *)(IDENT_ADDR + (address & ((1ul << 41) - 1))); 86 } 87 #endif 88 89 #define virt_to_phys virt_to_phys 90 #define phys_to_virt phys_to_virt 91 #define page_to_phys(page) page_to_pa(page) 92 93 /* Maximum PIO space address supported? */ 94 #define IO_SPACE_LIMIT 0xffff 95 96 /* 97 * Change addresses as seen by the kernel (virtual) to addresses as 98 * seen by a device (bus), and vice versa. 99 * 100 * Note that this only works for a limited range of kernel addresses, 101 * and very well may not span all memory. Consider this interface 102 * deprecated in favour of the DMA-mapping API. 103 */ 104 extern unsigned long __direct_map_base; 105 extern unsigned long __direct_map_size; 106 107 static inline unsigned long __deprecated isa_virt_to_bus(volatile void *address) 108 { 109 unsigned long phys = virt_to_phys(address); 110 unsigned long bus = phys + __direct_map_base; 111 return phys <= __direct_map_size ? bus : 0; 112 } 113 #define isa_virt_to_bus isa_virt_to_bus 114 115 static inline void * __deprecated isa_bus_to_virt(unsigned long address) 116 { 117 void *virt; 118 119 /* This check is a sanity check but also ensures that bus address 0 120 maps to virtual address 0 which is useful to detect null pointers 121 (the NCR driver is much simpler if NULL pointers are preserved). */ 122 address -= __direct_map_base; 123 virt = phys_to_virt(address); 124 return (long)address <= 0 ? NULL : virt; 125 } 126 #define isa_bus_to_virt isa_bus_to_virt 127 128 /* 129 * There are different chipsets to interface the Alpha CPUs to the world. 130 */ 131 132 #define IO_CONCAT(a,b) _IO_CONCAT(a,b) 133 #define _IO_CONCAT(a,b) a ## _ ## b 134 135 #ifdef CONFIG_ALPHA_GENERIC 136 137 /* In a generic kernel, we always go through the machine vector. */ 138 139 #define REMAP1(TYPE, NAME, QUAL) \ 140 static inline TYPE generic_##NAME(QUAL void __iomem *addr) \ 141 { \ 142 return alpha_mv.mv_##NAME(addr); \ 143 } 144 145 #define REMAP2(TYPE, NAME, QUAL) \ 146 static inline void generic_##NAME(TYPE b, QUAL void __iomem *addr) \ 147 { \ 148 alpha_mv.mv_##NAME(b, addr); \ 149 } 150 151 REMAP1(unsigned int, ioread8, const) 152 REMAP1(unsigned int, ioread16, const) 153 REMAP1(unsigned int, ioread32, const) 154 REMAP1(u64, ioread64, const) 155 REMAP1(u8, readb, const volatile) 156 REMAP1(u16, readw, const volatile) 157 REMAP1(u32, readl, const volatile) 158 REMAP1(u64, readq, const volatile) 159 160 REMAP2(u8, iowrite8, /**/) 161 REMAP2(u16, iowrite16, /**/) 162 REMAP2(u32, iowrite32, /**/) 163 REMAP2(u64, iowrite64, /**/) 164 REMAP2(u8, writeb, volatile) 165 REMAP2(u16, writew, volatile) 166 REMAP2(u32, writel, volatile) 167 REMAP2(u64, writeq, volatile) 168 169 #undef REMAP1 170 #undef REMAP2 171 172 extern inline void __iomem *generic_ioportmap(unsigned long a) 173 { 174 return alpha_mv.mv_ioportmap(a); 175 } 176 177 static inline void __iomem *generic_ioremap(unsigned long a, unsigned long s) 178 { 179 return alpha_mv.mv_ioremap(a, s); 180 } 181 182 static inline void generic_iounmap(volatile void __iomem *a) 183 { 184 return alpha_mv.mv_iounmap(a); 185 } 186 187 static inline int generic_is_ioaddr(unsigned long a) 188 { 189 return alpha_mv.mv_is_ioaddr(a); 190 } 191 192 static inline int generic_is_mmio(const volatile void __iomem *a) 193 { 194 return alpha_mv.mv_is_mmio(a); 195 } 196 197 #define __IO_PREFIX generic 198 #define generic_trivial_rw_bw 0 199 #define generic_trivial_rw_lq 0 200 #define generic_trivial_io_bw 0 201 #define generic_trivial_io_lq 0 202 #define generic_trivial_iounmap 0 203 204 #else 205 206 #if defined(CONFIG_ALPHA_CIA) 207 # include <asm/core_cia.h> 208 #elif defined(CONFIG_ALPHA_IRONGATE) 209 # include <asm/core_irongate.h> 210 #elif defined(CONFIG_ALPHA_MARVEL) 211 # include <asm/core_marvel.h> 212 #elif defined(CONFIG_ALPHA_MCPCIA) 213 # include <asm/core_mcpcia.h> 214 #elif defined(CONFIG_ALPHA_POLARIS) 215 # include <asm/core_polaris.h> 216 #elif defined(CONFIG_ALPHA_T2) 217 # include <asm/core_t2.h> 218 #elif defined(CONFIG_ALPHA_TSUNAMI) 219 # include <asm/core_tsunami.h> 220 #elif defined(CONFIG_ALPHA_TITAN) 221 # include <asm/core_titan.h> 222 #elif defined(CONFIG_ALPHA_WILDFIRE) 223 # include <asm/core_wildfire.h> 224 #else 225 #error "What system is this?" 226 #endif 227 228 #endif /* GENERIC */ 229 230 /* 231 * We always have external versions of these routines. 232 */ 233 extern u8 inb(unsigned long port); 234 extern u16 inw(unsigned long port); 235 extern u32 inl(unsigned long port); 236 extern void outb(u8 b, unsigned long port); 237 extern void outw(u16 b, unsigned long port); 238 extern void outl(u32 b, unsigned long port); 239 #define inb inb 240 #define inw inw 241 #define inl inl 242 #define outb outb 243 #define outw outw 244 #define outl outl 245 246 extern u8 readb(const volatile void __iomem *addr); 247 extern u16 readw(const volatile void __iomem *addr); 248 extern u32 readl(const volatile void __iomem *addr); 249 extern u64 readq(const volatile void __iomem *addr); 250 extern void writeb(u8 b, volatile void __iomem *addr); 251 extern void writew(u16 b, volatile void __iomem *addr); 252 extern void writel(u32 b, volatile void __iomem *addr); 253 extern void writeq(u64 b, volatile void __iomem *addr); 254 #define readb readb 255 #define readw readw 256 #define readl readl 257 #define readq readq 258 #define writeb writeb 259 #define writew writew 260 #define writel writel 261 #define writeq writeq 262 263 extern u8 __raw_readb(const volatile void __iomem *addr); 264 extern u16 __raw_readw(const volatile void __iomem *addr); 265 extern u32 __raw_readl(const volatile void __iomem *addr); 266 extern u64 __raw_readq(const volatile void __iomem *addr); 267 extern void __raw_writeb(u8 b, volatile void __iomem *addr); 268 extern void __raw_writew(u16 b, volatile void __iomem *addr); 269 extern void __raw_writel(u32 b, volatile void __iomem *addr); 270 extern void __raw_writeq(u64 b, volatile void __iomem *addr); 271 #define __raw_readb __raw_readb 272 #define __raw_readw __raw_readw 273 #define __raw_readl __raw_readl 274 #define __raw_readq __raw_readq 275 #define __raw_writeb __raw_writeb 276 #define __raw_writew __raw_writew 277 #define __raw_writel __raw_writel 278 #define __raw_writeq __raw_writeq 279 280 /* 281 * Mapping from port numbers to __iomem space is pretty easy. 282 */ 283 284 /* These two have to be extern inline because of the extern prototype from 285 <asm-generic/iomap.h>. It is not legal to mix "extern" and "static" for 286 the same declaration. */ 287 extern inline void __iomem *ioport_map(unsigned long port, unsigned int size) 288 { 289 return IO_CONCAT(__IO_PREFIX,ioportmap) (port); 290 } 291 292 extern inline void ioport_unmap(void __iomem *addr) 293 { 294 } 295 296 #define ioport_map ioport_map 297 #define ioport_unmap ioport_unmap 298 299 static inline void __iomem *ioremap(unsigned long port, unsigned long size) 300 { 301 return IO_CONCAT(__IO_PREFIX,ioremap) (port, size); 302 } 303 304 #define ioremap_wc ioremap 305 306 static inline void iounmap(volatile void __iomem *addr) 307 { 308 IO_CONCAT(__IO_PREFIX,iounmap)(addr); 309 } 310 311 static inline int __is_ioaddr(unsigned long addr) 312 { 313 return IO_CONCAT(__IO_PREFIX,is_ioaddr)(addr); 314 } 315 #define __is_ioaddr(a) __is_ioaddr((unsigned long)(a)) 316 317 static inline int __is_mmio(const volatile void __iomem *addr) 318 { 319 return IO_CONCAT(__IO_PREFIX,is_mmio)(addr); 320 } 321 322 323 /* 324 * If the actual I/O bits are sufficiently trivial, then expand inline. 325 */ 326 327 #if IO_CONCAT(__IO_PREFIX,trivial_io_bw) 328 extern inline unsigned int ioread8(const void __iomem *addr) 329 { 330 unsigned int ret; 331 mb(); 332 ret = IO_CONCAT(__IO_PREFIX,ioread8)(addr); 333 mb(); 334 return ret; 335 } 336 337 extern inline unsigned int ioread16(const void __iomem *addr) 338 { 339 unsigned int ret; 340 mb(); 341 ret = IO_CONCAT(__IO_PREFIX,ioread16)(addr); 342 mb(); 343 return ret; 344 } 345 346 extern inline void iowrite8(u8 b, void __iomem *addr) 347 { 348 mb(); 349 IO_CONCAT(__IO_PREFIX, iowrite8)(b, addr); 350 } 351 352 extern inline void iowrite16(u16 b, void __iomem *addr) 353 { 354 mb(); 355 IO_CONCAT(__IO_PREFIX, iowrite16)(b, addr); 356 } 357 358 extern inline u8 inb(unsigned long port) 359 { 360 return ioread8(ioport_map(port, 1)); 361 } 362 363 extern inline u16 inw(unsigned long port) 364 { 365 return ioread16(ioport_map(port, 2)); 366 } 367 368 extern inline void outb(u8 b, unsigned long port) 369 { 370 iowrite8(b, ioport_map(port, 1)); 371 } 372 373 extern inline void outw(u16 b, unsigned long port) 374 { 375 iowrite16(b, ioport_map(port, 2)); 376 } 377 #endif 378 379 #define ioread8 ioread8 380 #define ioread16 ioread16 381 #define iowrite8 iowrite8 382 #define iowrite16 iowrite16 383 384 #if IO_CONCAT(__IO_PREFIX,trivial_io_lq) 385 extern inline unsigned int ioread32(const void __iomem *addr) 386 { 387 unsigned int ret; 388 mb(); 389 ret = IO_CONCAT(__IO_PREFIX,ioread32)(addr); 390 mb(); 391 return ret; 392 } 393 394 extern inline u64 ioread64(const void __iomem *addr) 395 { 396 unsigned int ret; 397 mb(); 398 ret = IO_CONCAT(__IO_PREFIX,ioread64)(addr); 399 mb(); 400 return ret; 401 } 402 403 extern inline void iowrite32(u32 b, void __iomem *addr) 404 { 405 mb(); 406 IO_CONCAT(__IO_PREFIX, iowrite32)(b, addr); 407 } 408 409 extern inline void iowrite64(u64 b, void __iomem *addr) 410 { 411 mb(); 412 IO_CONCAT(__IO_PREFIX, iowrite64)(b, addr); 413 } 414 415 extern inline u32 inl(unsigned long port) 416 { 417 return ioread32(ioport_map(port, 4)); 418 } 419 420 extern inline void outl(u32 b, unsigned long port) 421 { 422 iowrite32(b, ioport_map(port, 4)); 423 } 424 #endif 425 426 #define ioread32 ioread32 427 #define ioread64 ioread64 428 #define iowrite32 iowrite32 429 #define iowrite64 iowrite64 430 431 #if IO_CONCAT(__IO_PREFIX,trivial_rw_bw) == 1 432 extern inline u8 __raw_readb(const volatile void __iomem *addr) 433 { 434 return IO_CONCAT(__IO_PREFIX,readb)(addr); 435 } 436 437 extern inline u16 __raw_readw(const volatile void __iomem *addr) 438 { 439 return IO_CONCAT(__IO_PREFIX,readw)(addr); 440 } 441 442 extern inline void __raw_writeb(u8 b, volatile void __iomem *addr) 443 { 444 IO_CONCAT(__IO_PREFIX,writeb)(b, addr); 445 } 446 447 extern inline void __raw_writew(u16 b, volatile void __iomem *addr) 448 { 449 IO_CONCAT(__IO_PREFIX,writew)(b, addr); 450 } 451 452 extern inline u8 readb(const volatile void __iomem *addr) 453 { 454 u8 ret; 455 mb(); 456 ret = __raw_readb(addr); 457 mb(); 458 return ret; 459 } 460 461 extern inline u16 readw(const volatile void __iomem *addr) 462 { 463 u16 ret; 464 mb(); 465 ret = __raw_readw(addr); 466 mb(); 467 return ret; 468 } 469 470 extern inline void writeb(u8 b, volatile void __iomem *addr) 471 { 472 mb(); 473 __raw_writeb(b, addr); 474 } 475 476 extern inline void writew(u16 b, volatile void __iomem *addr) 477 { 478 mb(); 479 __raw_writew(b, addr); 480 } 481 #endif 482 483 #if IO_CONCAT(__IO_PREFIX,trivial_rw_lq) == 1 484 extern inline u32 __raw_readl(const volatile void __iomem *addr) 485 { 486 return IO_CONCAT(__IO_PREFIX,readl)(addr); 487 } 488 489 extern inline u64 __raw_readq(const volatile void __iomem *addr) 490 { 491 return IO_CONCAT(__IO_PREFIX,readq)(addr); 492 } 493 494 extern inline void __raw_writel(u32 b, volatile void __iomem *addr) 495 { 496 IO_CONCAT(__IO_PREFIX,writel)(b, addr); 497 } 498 499 extern inline void __raw_writeq(u64 b, volatile void __iomem *addr) 500 { 501 IO_CONCAT(__IO_PREFIX,writeq)(b, addr); 502 } 503 504 extern inline u32 readl(const volatile void __iomem *addr) 505 { 506 u32 ret; 507 mb(); 508 ret = __raw_readl(addr); 509 mb(); 510 return ret; 511 } 512 513 extern inline u64 readq(const volatile void __iomem *addr) 514 { 515 u64 ret; 516 mb(); 517 ret = __raw_readq(addr); 518 mb(); 519 return ret; 520 } 521 522 extern inline void writel(u32 b, volatile void __iomem *addr) 523 { 524 mb(); 525 __raw_writel(b, addr); 526 } 527 528 extern inline void writeq(u64 b, volatile void __iomem *addr) 529 { 530 mb(); 531 __raw_writeq(b, addr); 532 } 533 #endif 534 535 #define ioread16be(p) swab16(ioread16(p)) 536 #define ioread32be(p) swab32(ioread32(p)) 537 #define iowrite16be(v,p) iowrite16(swab16(v), (p)) 538 #define iowrite32be(v,p) iowrite32(swab32(v), (p)) 539 540 #define inb_p inb 541 #define inw_p inw 542 #define inl_p inl 543 #define outb_p outb 544 #define outw_p outw 545 #define outl_p outl 546 547 extern u8 readb_relaxed(const volatile void __iomem *addr); 548 extern u16 readw_relaxed(const volatile void __iomem *addr); 549 extern u32 readl_relaxed(const volatile void __iomem *addr); 550 extern u64 readq_relaxed(const volatile void __iomem *addr); 551 #define readb_relaxed readb_relaxed 552 #define readw_relaxed readw_relaxed 553 #define readl_relaxed readl_relaxed 554 #define readq_relaxed readq_relaxed 555 556 #if IO_CONCAT(__IO_PREFIX,trivial_io_bw) 557 extern inline u8 readb_relaxed(const volatile void __iomem *addr) 558 { 559 mb(); 560 return __raw_readb(addr); 561 } 562 563 extern inline u16 readw_relaxed(const volatile void __iomem *addr) 564 { 565 mb(); 566 return __raw_readw(addr); 567 } 568 #endif 569 570 #if IO_CONCAT(__IO_PREFIX,trivial_io_lq) 571 extern inline u32 readl_relaxed(const volatile void __iomem *addr) 572 { 573 mb(); 574 return __raw_readl(addr); 575 } 576 577 extern inline u64 readq_relaxed(const volatile void __iomem *addr) 578 { 579 mb(); 580 return __raw_readq(addr); 581 } 582 #endif 583 584 #define writeb_relaxed writeb 585 #define writew_relaxed writew 586 #define writel_relaxed writel 587 #define writeq_relaxed writeq 588 589 /* 590 * String version of IO memory access ops: 591 */ 592 extern void memcpy_fromio(void *, const volatile void __iomem *, long); 593 extern void memcpy_toio(volatile void __iomem *, const void *, long); 594 extern void _memset_c_io(volatile void __iomem *, unsigned long, long); 595 596 static inline void memset_io(volatile void __iomem *addr, u8 c, long len) 597 { 598 _memset_c_io(addr, 0x0101010101010101UL * c, len); 599 } 600 601 #define __HAVE_ARCH_MEMSETW_IO 602 static inline void memsetw_io(volatile void __iomem *addr, u16 c, long len) 603 { 604 _memset_c_io(addr, 0x0001000100010001UL * c, len); 605 } 606 607 #define memset_io memset_io 608 #define memcpy_fromio memcpy_fromio 609 #define memcpy_toio memcpy_toio 610 611 /* 612 * String versions of in/out ops: 613 */ 614 extern void insb (unsigned long port, void *dst, unsigned long count); 615 extern void insw (unsigned long port, void *dst, unsigned long count); 616 extern void insl (unsigned long port, void *dst, unsigned long count); 617 extern void outsb (unsigned long port, const void *src, unsigned long count); 618 extern void outsw (unsigned long port, const void *src, unsigned long count); 619 extern void outsl (unsigned long port, const void *src, unsigned long count); 620 621 #define insb insb 622 #define insw insw 623 #define insl insl 624 #define outsb outsb 625 #define outsw outsw 626 #define outsl outsl 627 628 #define RTC_PORT(x) (0x70 + (x)) 629 #define RTC_ALWAYS_BCD 0 630 631 /* 632 * These get provided from <asm-generic/iomap.h> since alpha does not 633 * select GENERIC_IOMAP. 634 */ 635 #define ioread64 ioread64 636 #define iowrite64 iowrite64 637 #define ioread64be ioread64be 638 #define iowrite64be iowrite64be 639 #define ioread8_rep ioread8_rep 640 #define ioread16_rep ioread16_rep 641 #define ioread32_rep ioread32_rep 642 #define iowrite8_rep iowrite8_rep 643 #define iowrite16_rep iowrite16_rep 644 #define iowrite32_rep iowrite32_rep 645 #define pci_iounmap pci_iounmap 646 647 #include <asm-generic/io.h> 648 649 #endif /* __KERNEL__ */ 650 651 #endif /* __ALPHA_IO_H */ 652